From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A77C3C433F5 for ; Mon, 1 Nov 2021 08:46:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71EA760F36 for ; Mon, 1 Nov 2021 08:46:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 71EA760F36 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1067D6E176; Mon, 1 Nov 2021 08:46:47 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 318C66E176 for ; Mon, 1 Nov 2021 08:46:46 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10154"; a="211027269" X-IronPort-AV: E=Sophos;i="5.87,198,1631602800"; d="scan'208";a="211027269" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2021 01:46:45 -0700 X-IronPort-AV: E=Sophos;i="5.87,198,1631602800"; d="scan'208";a="499956695" Received: from unknown (HELO intel.com) ([10.237.72.167]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2021 01:46:44 -0700 Date: Mon, 1 Nov 2021 10:41:58 +0200 From: "Lisovskiy, Stanislav" To: Ville Syrjala Message-ID: <20211101084158.GA8858@intel.com> References: <20211029191802.18448-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20211029191802.18448-1-ville.syrjala@linux.intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't request GMBUS to generate irqs when called while irqs are off X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Oct 29, 2021 at 10:18:01PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > We will need to do some i2c poking from the encoder->shutdown() hook. > Currently that gets called after irqs have been turned off. We still > poll the gmbus status bits even if the interrupt never arrives so > things will work just fine. But seems like asking gmbus to generate > interrupts we will never see is a bit pointless, so don't. > > Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy > --- > drivers/gpu/drm/i915/display/intel_gmbus.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c > index ceb1bf8a8c3c..3b8b84177085 100644 > --- a/drivers/gpu/drm/i915/display/intel_gmbus.c > +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c > @@ -334,6 +334,15 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) > algo->data = bus; > } > > +static bool has_gmbus_irq(struct drm_i915_private *i915) > +{ > + /* > + * encoder->shutdown() may want to use GMBUS > + * after irqs have already been disabled. > + */ > + return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); > +} > + > static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) > { > DEFINE_WAIT(wait); > @@ -344,7 +353,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) > * we also need to check for NAKs besides the hw ready/idle signal, we > * need to wake up periodically and check that ourselves. > */ > - if (!HAS_GMBUS_IRQ(dev_priv)) > + if (!has_gmbus_irq(dev_priv)) > irq_en = 0; > > add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); > @@ -375,7 +384,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) > > /* Important: The hw handles only the first bit, so set only one! */ > irq_enable = 0; > - if (HAS_GMBUS_IRQ(dev_priv)) > + if (has_gmbus_irq(dev_priv)) > irq_enable = GMBUS_IDLE_EN; > > add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); > -- > 2.32.0 >