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Fri, 26 Nov 2021 00:21:15 -0800 (PST) Received: from eldfell ([194.136.85.206]) by smtp.gmail.com with ESMTPSA id b12sm449250lfb.41.2021.11.26.00.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Nov 2021 00:21:14 -0800 (PST) Date: Fri, 26 Nov 2021 10:21:05 +0200 From: Pekka Paalanen To: "Shankar, Uma" Message-ID: <20211126102105.567428f2@eldfell> In-Reply-To: <062cb4bfe0d94fb9aa34845b413e9021@intel.com> References: <20210906213904.27918-1-uma.shankar@intel.com> <20210906213904.27918-2-uma.shankar@intel.com> <2a2684e6-f5d6-c917-6f0c-8dc3704ddaf6@amd.com> <062cb4bfe0d94fb9aa34845b413e9021@intel.com> X-Mailer: Claws Mail 3.17.8 (GTK+ 2.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; boundary="Sig_/j6d_irybuesop7q7mi.S57v"; protocol="application/pgp-signature"; micalg=pgp-sha256 Subject: Re: [Intel-gfx] [RFC v2 01/22] drm: RFC for Plane Color Hardware Pipeline X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "intel-gfx@lists.freedesktop.org" , "dri-devel@lists.freedesktop.org" , "sebastian@sebastianwick.net" , Harry Wentland Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --Sig_/j6d_irybuesop7q7mi.S57v Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Thu, 25 Nov 2021 20:43:19 +0000 "Shankar, Uma" wrote: > > -----Original Message----- > > From: Harry Wentland > > Sent: Tuesday, November 23, 2021 8:35 PM > > To: Shankar, Uma ; intel-gfx@lists.freedesktop.o= rg; dri- > > devel@lists.freedesktop.org > > Cc: ville.syrjala@linux.intel.com; ppaalanen@gmail.com; brian.starkey@a= rm.com; > > sebastian@sebastianwick.net; Shashank.Sharma@amd.com > > Subject: Re: [RFC v2 01/22] drm: RFC for Plane Color Hardware Pipeline > >=20 > >=20 > >=20 > > On 2021-09-06 17:38, Uma Shankar wrote: =20 > > > This is a RFC proposal for plane color hardware blocks. > > > It exposes the property interface to userspace and calls out the > > > details or interfaces created and the intended purpose. > > > > > > Credits: Ville Syrj=C3=A4l=C3=A4 > > > Signed-off-by: Uma Shankar > > > --- > > > Documentation/gpu/rfc/drm_color_pipeline.rst | 167 > > > +++++++++++++++++++ > > > 1 file changed, 167 insertions(+) > > > create mode 100644 Documentation/gpu/rfc/drm_color_pipeline.rst > > > > > > diff --git a/Documentation/gpu/rfc/drm_color_pipeline.rst > > > b/Documentation/gpu/rfc/drm_color_pipeline.rst > > > new file mode 100644 > > > index 000000000000..0d1ca858783b > > > --- /dev/null > > > +++ b/Documentation/gpu/rfc/drm_color_pipeline.rst > > > @@ -0,0 +1,167 @@ > > > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D > > > +Display Color Pipeline: Proposed DRM Properties > > > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D > > > + > > > +This is how a typical display color hardware pipeline looks like: > > > + +-------------------------------------------+ > > > + | RAM | > > > + | +------+ +---------+ +---------+ | > > > + | | FB 1 | | FB 2 | | FB N | | > > > + | +------+ +---------+ +---------+ | > > > + +-------------------------------------------+ > > > + | Plane Color Hardware Block | > > > + +--------------------------------------------+ > > > + | +---v-----+ +---v-------+ +---v------+ | > > > + | | Plane A | | Plane B | | Plane N | | > > > + | | DeGamma | | Degamma | | Degamma | | > > > + | +---+-----+ +---+-------+ +---+------+ | > > > + | | | | | > > > + | +---v-----+ +---v-------+ +---v------+ | > > > + | |Plane A | | Plane B | | Plane N | | > > > + | |CSC/CTM | | CSC/CTM | | CSC/CTM | | > > > + | +---+-----+ +----+------+ +----+-----+ | > > > + | | | | | > > > + | +---v-----+ +----v------+ +----v-----+ | > > > + | | Plane A | | Plane B | | Plane N | | > > > + | | Gamma | | Gamma | | Gamma | | > > > + | +---+-----+ +----+------+ +----+-----+ | > > > + | | | | | > > > + +--------------------------------------------+ > > > ++------v--------------v---------------v-------| > > > +|| || > > > +|| Pipe Blender || > > > ++--------------------+------------------------+ > > > +| | | > > > +| +-----------v----------+ | > > > +| | Pipe DeGamma | | > > > +| | | | > > > +| +-----------+----------+ | > > > +| | Pipe Color | > > > +| +-----------v----------+ Hardware | > > > +| | Pipe CSC/CTM | | > > > +| | | | > > > +| +-----------+----------+ | > > > +| | | > > > +| +-----------v----------+ | > > > +| | Pipe Gamma | | > > > +| | | | > > > +| +-----------+----------+ | > > > +| | | > > > ++---------------------------------------------+ > > > + | > > > + v > > > + Pipe Output > > > + =20 > >=20 > > This diagram defines what happens before and after the blending space b= ut did > > where does scaling fit into it? Scaling can look different when perform= ed in linear or > > non-linear space so I think it is important to define where in the pipe= line it sits. > >=20 > > In my view scaling would happen between plane degamma and plane CSC. =20 >=20 > Yeah we can add scaling as well to make it clear. Scaling ideally should = happen after > Degamma. In intel's case it is after the CSC. Btw. are you aware that if a plane has an alpha channel which is used for pixel coverage (i.e. shape anti-aliasing), then non-nearest sampling and therefore also scaling must operate on alpha pre-multiplied optical (linear) values? For the best results, of course. So after degamma indeed, but you cannot degamma with pre-multiplied alpha, yet scaling should use pre-multiplied alpha. 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