From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1C9BC433EF for ; Fri, 3 Dec 2021 17:48:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 314A06FCC0; Fri, 3 Dec 2021 17:48:51 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 171606FCC0 for ; Fri, 3 Dec 2021 17:48:50 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10187"; a="217044117" X-IronPort-AV: E=Sophos;i="5.87,284,1631602800"; d="scan'208";a="217044117" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2021 09:48:49 -0800 X-IronPort-AV: E=Sophos;i="5.87,284,1631602800"; d="scan'208";a="541698029" Received: from ibrewste-mobl.amr.corp.intel.com (HELO mvcheng-desk2.intel.com) ([10.255.228.163]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2021 09:48:49 -0800 From: Michael Cheng To: intel-gfx@lists.freedesktop.org Date: Fri, 3 Dec 2021 09:48:42 -0800 Message-Id: <20211203174843.221641-1-michael.cheng@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH v5 0/1] Introduce new i915 macros for checking PTEs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.cheng@intel.com, wayne.boyer@intel.com, jani.nikula@intel.com, lucas.demarchi@intel.com, siva.mullati@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This series is to introduce new macros generic to i915 for checking 0 and 1 bits, instead on relying on whats defined by the mmu, since it could be different or non-exisitent between different platforms. v2: Corrected sender's email. v3: Corrected spelling error. v4: Clean up a few other macros that are checking 0 and 1 bits. Thanks to Lucas De Marchi for suggesting these cleanups. v5: Remove changes to GEN6_PTE_VALID/GEN6_PDE_VALID and BYT_PTE_WRITEABLE. Those macros checks for 32bit PTEs, and our new macro is checking for 64bit. Michael Cheng (1): drm/i915: Introduce new macros for i915 PTE drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +++ drivers/gpu/drm/i915/gvt/gtt.c | 12 ++++++------ 4 files changed, 13 insertions(+), 10 deletions(-) -- 2.25.1