From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2CCC0C433F5 for ; Wed, 8 Dec 2021 11:15:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C7936FAB5; Wed, 8 Dec 2021 11:15:37 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8032E6F947; Wed, 8 Dec 2021 11:15:35 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10191"; a="235321858" X-IronPort-AV: E=Sophos;i="5.87,297,1631602800"; d="scan'208";a="235321858" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2021 03:15:34 -0800 X-IronPort-AV: E=Sophos;i="5.87,297,1631602800"; d="scan'208";a="503018392" Received: from ramaling-i9x.iind.intel.com (HELO intel.com) ([10.99.66.205]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2021 03:15:32 -0800 Date: Wed, 8 Dec 2021 16:45:07 +0530 From: Ramalingam C To: Matthew Auld Message-ID: <20211208111507.GA4839@intel.com> References: <20211208102031.4397-1-ramalingam.c@intel.com> <20211208102031.4397-2-ramalingam.c@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915: Sanitycheck device iomem on probe X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andi , intel-gfx , dri-devel , Chris Wilson , CQ Tang , Hellstrom Thomas Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 2021-12-08 at 11:12:07 +0000, Matthew Auld wrote: > On 08/12/2021 10:20, Ramalingam C wrote: > > From: Chris Wilson > > > > As we setup the memory regions for the device, give each a quick test to > > verify that we can read and write to the full iomem range. This ensures > > that our physical addressing for the device's memory is correct, and > > some reassurance that the memory is functional. > > > > Signed-off-by: Chris Wilson > > Cc: Matthew Auld > > Cc: CQ Tang > > Signed-off-by: Ramalingam C > > For the series, assuming CI is happy now, > Reviewed-by: Matthew Auld Thank you! > > Also patch 3 should be moved to the start of the series. Sure I will do it. Ram. > > > --- > > drivers/gpu/drm/i915/intel_memory_region.c | 104 +++++++++++++++++++++ > > 1 file changed, 104 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c > > index b43121609e25..c53e07f1d0c0 100644 > > --- a/drivers/gpu/drm/i915/intel_memory_region.c > > +++ b/drivers/gpu/drm/i915/intel_memory_region.c > > @@ -3,6 +3,8 @@ > > * Copyright © 2019 Intel Corporation > > */ > > +#include > > + > > #include "intel_memory_region.h" > > #include "i915_drv.h" > > #include "i915_ttm_buddy_manager.h" > > @@ -29,6 +31,99 @@ static const struct { > > }, > > }; > > +static int __iopagetest(struct intel_memory_region *mem, > > + u8 __iomem *va, int pagesize, > > + u8 value, resource_size_t offset, > > + const void *caller) > > +{ > > + int byte = prandom_u32_max(pagesize); > > + u8 result[3]; > > + > > + memset_io(va, value, pagesize); /* or GPF! */ > > + wmb(); > > + > > + result[0] = ioread8(va); > > + result[1] = ioread8(va + byte); > > + result[2] = ioread8(va + pagesize - 1); > > + if (memchr_inv(result, value, sizeof(result))) { > > + dev_err(mem->i915->drm.dev, > > + "Failed to read back from memory region:%pR at [%pa + %pa] for %ps; wrote %x, read (%x, %x, %x)\n", > > + &mem->region, &mem->io_start, &offset, caller, > > + value, result[0], result[1], result[2]); > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > + > > +static int iopagetest(struct intel_memory_region *mem, > > + resource_size_t offset, > > + const void *caller) > > +{ > > + const u8 val[] = { 0x0, 0xa5, 0xc3, 0xf0 }; > > + void __iomem *va; > > + int err; > > + int i; > > + > > + va = ioremap_wc(mem->io_start + offset, PAGE_SIZE); > > + if (!va) { > > + dev_err(mem->i915->drm.dev, > > + "Failed to ioremap memory region [%pa + %px] for %ps\n", > > + &mem->io_start, &offset, caller); > > + return -EFAULT; > > + } > > + > > + for (i = 0; i < ARRAY_SIZE(val); i++) { > > + err = __iopagetest(mem, va, PAGE_SIZE, val[i], offset, caller); > > + if (err) > > + break; > > + > > + err = __iopagetest(mem, va, PAGE_SIZE, ~val[i], offset, caller); > > + if (err) > > + break; > > + } > > + > > + iounmap(va); > > + return err; > > +} > > + > > +static resource_size_t random_page(resource_size_t last) > > +{ > > + /* Limited to low 44b (16TiB), but should suffice for a spot check */ > > + return prandom_u32_max(last >> PAGE_SHIFT) << PAGE_SHIFT; > > +} > > + > > +static int iomemtest(struct intel_memory_region *mem, const void *caller) > > +{ > > + resource_size_t last = resource_size(&mem->region) - PAGE_SIZE; > > + int err; > > + > > + /* > > + * Quick test to check read/write access to the iomap (backing store). > > + * > > + * Write a byte, read it back. If the iomapping fails, we expect > > + * a GPF preventing further execution. If the backing store does not > > + * exist, the read back will return garbage. We check a couple of pages, > > + * the first and last of the specified region to confirm the backing > > + * store + iomap does cover the entire memory region; and we check > > + * a random offset within as a quick spot check for bad memory. > > + */ > > + > > + err = iopagetest(mem, 0, caller); > > + if (err) > > + return err; > > + > > + err = iopagetest(mem, last, caller); > > + if (err) > > + return err; > > + > > + err = iopagetest(mem, random_page(last), caller); > > + if (err) > > + return err; > > + > > + return 0; > > +} > > + > > struct intel_memory_region * > > intel_memory_region_lookup(struct drm_i915_private *i915, > > u16 class, u16 instance) > > @@ -126,8 +221,17 @@ intel_memory_region_create(struct drm_i915_private *i915, > > goto err_free; > > } > > + if (io_start && IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { > > + err = iomemtest(mem, (void *)_RET_IP_); > > + if (err) > > + goto err_release; > > + } > > + > > return mem; > > +err_release: > > + if (mem->ops->release) > > + mem->ops->release(mem); > > err_free: > > kfree(mem); > > return ERR_PTR(err); > >