From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>
Subject: [Intel-gfx] [PATCH v3 02/11] drm/i915: Parameterize PWRCTX_MAXCNT
Date: Mon, 10 Jan 2022 21:15:51 -0800 [thread overview]
Message-ID: <20220111051600.3429104-3-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20220111051600.3429104-1-matthew.d.roper@intel.com>
Rather than having separate definitions for each engine, create a single
parameterized macro that takes the engine base offset. This will also
ensure we get to the proper offset if we ever need to use these
registers on newer platforms (where the media engine offsets have
changed).
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 8 ++++----
drivers/gpu/drm/i915/i915_reg.h | 6 +-----
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index c3155ee58689..45891e6f0b98 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -449,10 +449,10 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
enable_rc6 = false;
}
- if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
- (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
+ if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
+ (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
drm_dbg(&i915->drm,
"Engine Idle wait time not set properly.\n");
enable_rc6 = false;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 149cf4d25569..3ef332833c4c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9048,11 +9048,7 @@ enum {
#define RC6_CTX_IN_DRAM (1 << 0)
#define RC6_CTX_BASE _MMIO(0xD48)
#define RC6_CTX_BASE_MASK 0xFFFFFFF0
-#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
-#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
-#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
-#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
-#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
+#define PWRCTX_MAXCNT(base) _MMIO((base) + 0x54)
#define IDLE_TIME_MASK 0xFFFFF
#define FORCEWAKE _MMIO(0xA18C)
#define FORCEWAKE_VLV _MMIO(0x1300b0)
--
2.34.1
next prev parent reply other threads:[~2022-01-11 5:16 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-11 5:15 [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 01/11] drm/i915: Use parameterized GPR register definitions everywhere Matt Roper
2022-01-11 5:15 ` Matt Roper [this message]
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 03/11] drm/i915: Parameterize ECOSKPD Matt Roper
2022-01-12 15:09 ` Ville Syrjälä
2022-01-13 4:14 ` Matt Roper
2022-01-13 9:06 ` Jani Nikula
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 04/11] drm/i915: Use RING_PSMI_CTL rather than per-engine macros Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 05/11] drm/i915: Replace GFX_MODE_GEN7 with RING_MODE_GEN7 Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 06/11] drm/i915: Introduce i915_reg_defs.h Matt Roper
2022-01-11 8:42 ` Jani Nikula
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 07/11] drm/i915/gt: Move engine registers to their own header Matt Roper
2022-01-11 16:29 ` Lucas De Marchi
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 08/11] drm/i915: Move SNPS PHY " Matt Roper
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 09/11] drm/i915: Move combo " Matt Roper
2022-01-11 13:44 ` Jani Nikula
2022-01-11 5:15 ` [Intel-gfx] [PATCH v3 10/11] drm/i915: Move TC " Matt Roper
2022-01-11 13:49 ` Jani Nikula
2022-01-11 5:16 ` [Intel-gfx] [PATCH v3 11/11] drm/i915: Drop unused _PORT3 and _PORT4 TC phy register offsets Matt Roper
2022-01-11 13:50 ` Jani Nikula
2022-01-11 5:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Start cleaning up register definitions (rev3) Patchwork
2022-01-11 5:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-11 6:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-11 10:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-01-11 22:17 ` Matt Roper
2022-01-11 22:19 ` Matt Roper
2022-01-12 21:41 ` [Intel-gfx] [PATCH v3 00/11] Start cleaning up register definitions Rodrigo Vivi
2022-01-13 16:58 ` Jani Nikula
2022-01-13 20:23 ` Rodrigo Vivi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220111051600.3429104-3-matthew.d.roper@intel.com \
--to=matthew.d.roper@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox