From: Matthew Brost <matthew.brost@intel.com>
To: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v5 09/10] drm/i915/guc: Follow legacy register names
Date: Thu, 3 Feb 2022 11:09:39 -0800 [thread overview]
Message-ID: <20220203190939.GA4485@jons-linux-dev-box> (raw)
In-Reply-To: <20220126104822.3653079-10-alan.previn.teres.alexis@intel.com>
On Wed, Jan 26, 2022 at 02:48:21AM -0800, Alan Previn wrote:
> Before we print the GuC provided register dumps, modify the
> register tables to use string names as per the legacy error
> capture execlist codes.
>
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
I'd just squash this to the patches early in the series where these are
initially defined.
Matt
> ---
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 70 +++++++++----------
> 1 file changed, 35 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 2f5dc413dddc..506496058daf 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -22,7 +22,7 @@
> * from the engine-mmio-base
> */
> #define COMMON_BASE_GLOBAL() \
> - {FORCEWAKE_MT, 0, 0, "FORCEWAKE_MT"}
> + {FORCEWAKE_MT, 0, 0, "FORCEWAKE"}
>
> #define COMMON_GEN9BASE_GLOBAL() \
> {GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0"}, \
> @@ -34,43 +34,43 @@
> #define COMMON_GEN12BASE_GLOBAL() \
> {GEN12_FAULT_TLB_DATA0, 0, 0, "GEN12_FAULT_TLB_DATA0"}, \
> {GEN12_FAULT_TLB_DATA1, 0, 0, "GEN12_FAULT_TLB_DATA1"}, \
> - {GEN12_AUX_ERR_DBG, 0, 0, "GEN12_AUX_ERR_DBG"}, \
> - {GEN12_GAM_DONE, 0, 0, "GEN12_GAM_DONE"}, \
> - {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
> + {GEN12_AUX_ERR_DBG, 0, 0, "AUX_ERR_DBG"}, \
> + {GEN12_GAM_DONE, 0, 0, "GAM_DONE"}, \
> + {GEN12_RING_FAULT_REG, 0, 0, "FAULT_REG"}
>
> #define COMMON_BASE_ENGINE_INSTANCE() \
> - {RING_PSMI_CTL(0), 0, 0, "RING_PSMI_CTL"}, \
> - {RING_ESR(0), 0, 0, "RING_ESR"}, \
> - {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LOW32"}, \
> - {RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UP32"}, \
> - {RING_IPEIR(0), 0, 0, "RING_IPEIR"}, \
> - {RING_IPEHR(0), 0, 0, "RING_IPEHR"}, \
> - {RING_INSTPS(0), 0, 0, "RING_INSTPS"}, \
> + {RING_PSMI_CTL(0), 0, 0, "RC PSMI"}, \
> + {RING_ESR(0), 0, 0, "ESR"}, \
> + {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LDW"}, \
> + {RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UDW"}, \
> + {RING_IPEIR(0), 0, 0, "IPEIR"}, \
> + {RING_IPEHR(0), 0, 0, "IPEHR"}, \
> + {RING_INSTPS(0), 0, 0, "INSTPS"}, \
> {RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32"}, \
> {RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32"}, \
> - {RING_BBSTATE(0), 0, 0, "RING_BBSTATE"}, \
> + {RING_BBSTATE(0), 0, 0, "BB_STATE"}, \
> {CCID(0), 0, 0, "CCID"}, \
> - {RING_ACTHD(0), 0, 0, "RING_ACTHD_LOW32"}, \
> - {RING_ACTHD_UDW(0), 0, 0, "RING_ACTHD_UP32"}, \
> - {RING_INSTPM(0), 0, 0, "RING_INSTPM"}, \
> + {RING_ACTHD(0), 0, 0, "ACTHD_LDW"}, \
> + {RING_ACTHD_UDW(0), 0, 0, "ACTHD_UDW"}, \
> + {RING_INSTPM(0), 0, 0, "INSTPM"}, \
> + {RING_INSTDONE(0), 0, 0, "INSTDONE"}, \
> {RING_NOPID(0), 0, 0, "RING_NOPID"}, \
> - {RING_START(0), 0, 0, "RING_START"}, \
> - {RING_HEAD(0), 0, 0, "RING_HEAD"}, \
> - {RING_TAIL(0), 0, 0, "RING_TAIL"}, \
> - {RING_CTL(0), 0, 0, "RING_CTL"}, \
> - {RING_MI_MODE(0), 0, 0, "RING_MI_MODE"}, \
> + {RING_START(0), 0, 0, "START"}, \
> + {RING_HEAD(0), 0, 0, "HEAD"}, \
> + {RING_TAIL(0), 0, 0, "TAIL"}, \
> + {RING_CTL(0), 0, 0, "CTL"}, \
> + {RING_MI_MODE(0), 0, 0, "MODE"}, \
> {RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL"}, \
> - {RING_INSTDONE(0), 0, 0, "RING_INSTDONE"}, \
> - {RING_HWS_PGA(0), 0, 0, "RING_HWS_PGA"}, \
> - {RING_MODE_GEN7(0), 0, 0, "RING_MODE_GEN7"}, \
> - {GEN8_RING_PDP_LDW(0, 0), 0, 0, "GEN8_RING_PDP0_LDW"}, \
> - {GEN8_RING_PDP_UDW(0, 0), 0, 0, "GEN8_RING_PDP0_UDW"}, \
> - {GEN8_RING_PDP_LDW(0, 1), 0, 0, "GEN8_RING_PDP1_LDW"}, \
> - {GEN8_RING_PDP_UDW(0, 1), 0, 0, "GEN8_RING_PDP1_UDW"}, \
> - {GEN8_RING_PDP_LDW(0, 2), 0, 0, "GEN8_RING_PDP2_LDW"}, \
> - {GEN8_RING_PDP_UDW(0, 2), 0, 0, "GEN8_RING_PDP2_UDW"}, \
> - {GEN8_RING_PDP_LDW(0, 3), 0, 0, "GEN8_RING_PDP3_LDW"}, \
> - {GEN8_RING_PDP_UDW(0, 3), 0, 0, "GEN8_RING_PDP3_UDW"}
> + {RING_HWS_PGA(0), 0, 0, "HWS"}, \
> + {RING_MODE_GEN7(0), 0, 0, "GFX_MODE"}, \
> + {GEN8_RING_PDP_LDW(0, 0), 0, 0, "PDP0_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 0), 0, 0, "PDP0_UDW"}, \
> + {GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW"}, \
> + {GEN8_RING_PDP_LDW(0, 2), 0, 0, "PDP2_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 2), 0, 0, "PDP2_UDW"}, \
> + {GEN8_RING_PDP_LDW(0, 3), 0, 0, "PDP3_LDW"}, \
> + {GEN8_RING_PDP_UDW(0, 3), 0, 0, "PDP3_UDW"}
>
> #define COMMON_BASE_HAS_EU() \
> {EIR, 0, 0, "EIR"}
> @@ -83,10 +83,10 @@
> {GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2"}
>
> #define COMMON_GEN12BASE_VEC() \
> - {GEN12_SFC_DONE(0), 0, 0, "GEN12_SFC_DONE0"}, \
> - {GEN12_SFC_DONE(1), 0, 0, "GEN12_SFC_DONE1"}, \
> - {GEN12_SFC_DONE(2), 0, 0, "GEN12_SFC_DONE2"}, \
> - {GEN12_SFC_DONE(3), 0, 0, "GEN12_SFC_DONE3"}
> + {GEN12_SFC_DONE(0), 0, 0, "SFC_DONE[0]"}, \
> + {GEN12_SFC_DONE(1), 0, 0, "SFC_DONE[1]"}, \
> + {GEN12_SFC_DONE(2), 0, 0, "SFC_DONE[2]"}, \
> + {GEN12_SFC_DONE(3), 0, 0, "SFC_DONE[3]"}
>
> /* XE_LPD - Global */
> static struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
> --
> 2.25.1
>
next prev parent reply other threads:[~2022-02-03 19:15 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 10:48 [Intel-gfx] [PATCH v5 00/10] Add GuC Error Capture Support Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 01/10] drm/i915/guc: Update GuC ADS size for error capture lists Alan Previn
2022-01-26 18:09 ` Jani Nikula
2022-01-26 18:15 ` Jani Nikula
2022-01-26 22:46 ` Lucas De Marchi
2022-02-03 19:03 ` Matthew Brost
2022-02-03 20:04 ` Lucas De Marchi
2022-02-03 20:37 ` Teres Alexis, Alan Previn
2022-02-03 20:40 ` Teres Alexis, Alan Previn
2022-02-03 21:40 ` Lucas De Marchi
2022-02-03 21:58 ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 02/10] drm/i915/guc: Add XE_LP registers for GuC error state capture Alan Previn
2022-01-26 18:13 ` Jani Nikula
2022-01-26 21:46 ` Teres Alexis, Alan Previn
2022-01-27 9:30 ` Jani Nikula
2022-01-28 16:54 ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 03/10] drm/i915/guc: Add DG2 " Alan Previn
2022-02-05 1:28 ` Umesh Nerlige Ramappa
2022-02-10 5:17 ` Teres Alexis, Alan Previn
2022-02-11 19:24 ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 04/10] drm/i915/guc: Add Gen9 " Alan Previn
2022-02-07 19:14 ` Umesh Nerlige Ramappa
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 05/10] drm/i915/guc: Add GuC's error state capture output structures Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 06/10] drm/i915/guc: Update GuC's log-buffer-state access for error capture Alan Previn
2022-01-27 4:26 ` Teres Alexis, Alan Previn
2022-02-04 18:19 ` Matthew Brost
2022-02-08 19:38 ` Teres Alexis, Alan Previn
2022-02-08 22:18 ` Matthew Brost
2022-02-08 22:55 ` Teres Alexis, Alan Previn
2022-02-09 3:34 ` Matthew Brost
2022-02-09 3:41 ` Matthew Brost
2022-02-09 3:51 ` Teres Alexis, Alan Previn
2022-02-14 19:20 ` Teres Alexis, Alan Previn
2022-02-15 1:22 ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 07/10] drm/i915/guc: Extract GuC error capture lists on G2H notification Alan Previn
2022-02-11 1:36 ` Umesh Nerlige Ramappa
2022-02-13 19:47 ` Teres Alexis, Alan Previn
2022-02-17 19:21 ` Umesh Nerlige Ramappa
2022-02-25 7:21 ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 08/10] drm/i915/guc: Plumb GuC-capture into gpu_coredump Alan Previn
2022-02-11 2:11 ` Umesh Nerlige Ramappa
2022-02-12 0:31 ` Teres Alexis, Alan Previn
2022-02-12 0:38 ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 09/10] drm/i915/guc: Follow legacy register names Alan Previn
2022-02-03 19:09 ` Matthew Brost [this message]
2022-02-04 18:53 ` Teres Alexis, Alan Previn
2022-01-26 10:48 ` [Intel-gfx] [PATCH v5 10/10] drm/i915/guc: Print the GuC error capture output register list Alan Previn
2022-02-07 21:43 ` Umesh Nerlige Ramappa
2022-01-26 18:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add GuC Error Capture Support (rev5) Patchwork
2022-01-26 18:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-26 19:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220203190939.GA4485@jons-linux-dev-box \
--to=matthew.brost@intel.com \
--cc=alan.previn.teres.alexis@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox