Re: [Intel-gfx] [PATCH v2 07/21] drm/i915/mtl: Add gmbus and gpio support

Matt Roper
2022-08-19T19:17:29Z

On Thu, Aug 18, 2022 at 04:41:48PM -0700, Radhakrishna Sripada wrote:
> Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
> From spec we have registers GPIO_CTL[1-5] mapped to native display phys and
> GPIO_CTL[9-14] are mapped to TC ports.
>
> BSpec: 49306
>
> Original Author: Brian J Lovin
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_gmbus.c | 17 +++++++++++++++++
> drivers/gpu/drm/i915/display/intel_gmbus.h | 1 +
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index a6ba7fb72339..542b8b2654be 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -116,6 +116,20 @@ static const struct gmbus_pin gmbus_pins_dg2[] = {
> [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> };
>
> +static const struct gmbus_pin gmbus_pins_mtp[] = {
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> + [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> + [GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> + [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
> + [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },

There's no GPIO_CTL registers for pin 13 or pin 14 on on MTP so these
last two entries shouldn't be here (and the commit message should be
fixed too).

Matt

> +};
> +
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
> unsigned int pin)
> {
> @@ -128,6 +142,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
> } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> pins = gmbus_pins_dg1;
> size = ARRAY_SIZE(gmbus_pins_dg1);
> + } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) {
> + pins = gmbus_pins_mtp;
> + size = ARRAY_SIZE(gmbus_pins_mtp);
> } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
> pins = gmbus_pins_icp;
> size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index 8edc2e99cf53..20f704bd4e70 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -24,6 +24,7 @@ struct i2c_adapter;
> #define GMBUS_PIN_2_BXT 2
> #define GMBUS_PIN_3_BXT 3
> #define GMBUS_PIN_4_CNP 4
> +#define GMBUS_PIN_5_MTP 5
> #define GMBUS_PIN_9_TC1_ICP 9
> #define GMBUS_PIN_10_TC2_ICP 10
> #define GMBUS_PIN_11_TC3_ICP 11
> --
> 2.25.1
>

--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation