Re: [Intel-gfx] [PULL] gvt-fixes

Zhenyu Wang
2020-06-23T03:23:34Z

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On 2020.06.18 15:48:01 +0300, Joonas Lahtinen wrote:
> Quoting Zhenyu Wang (2020-06-17 07:34:18)
> >
> > Hi,
> >
> > This contains misc fixes for gvt. Two MMIO handler fixes on SKL/CFL,
> > one mask register bit checking fix exposed in suspend/resume path and
> > one lockdep error fix for debugfs entry access.
>
> Could not pull this one due to the extra hassle with CI this week.
>
> Jani, can you please pull this next week.
>

Got it. Please help to pull then.

One thing I forgot to mention that change in "drm/i915/gvt: Fix incorrect check of enabled bits in mask registers"
would cause a minor conflict if backmerging from linux master to dinq, which
is because of new IS_COMETLAKE. Change like below could resolve that.

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 9f48db0bf9d5..78ba2857144e 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1734,14 +1734,9 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
return 0;
}

-<<<<<<< HEAD
if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
IS_COMETLAKE(vgpu->gvt->gt->i915)) &&
- data & _MASKED_BIT_ENABLE(2)) {
-=======
- if (IS_COFFEELAKE(vgpu->gvt->gt->i915) &&
IS_MASKED_BITS_ENABLED(data, 2)) {
->>>>>>> origin/gvt-next-fixes
enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
return 0;
}

>
> > Thanks.
> > --
> > The following changes since commit 8e68c6340d5833077b3753eabedab40755571383:
> >
> > drm/i915/display: Fix the encoder type check (2020-06-16 11:34:24 +0300)
> >
> > are available in the Git repository at:
> >
> > https://github.com/intel/gvt-linux tags/gvt-fixes-2020-06-17
> >
> > for you to fetch changes up to a291e4fba259a56a6a274c1989997acb6f0bb03a:
> >
> > drm/i915/gvt: Use GFP_ATOMIC instead of GFP_KERNEL in atomic context (2020-06-17 12:36:19 +0800)
> >
> > ----------------------------------------------------------------
> > gvt-fixes-2020-06-17
> >
> > - Two missed MMIO handler fixes for SKL/CFL (Colin)
> > - Fix mask register bits check (Colin)
> > - Fix one lockdep error for debugfs entry access (Colin)
> >
> > ----------------------------------------------------------------
> > Colin Xu (4):
> > drm/i915/gvt: Add one missing MMIO handler for D_SKL_PLUS
> > drm/i915/gvt: Fix two CFL MMIO handling caused by regression.
> > drm/i915/gvt: Fix incorrect check of enabled bits in mask registers
> > drm/i915/gvt: Use GFP_ATOMIC instead of GFP_KERNEL in atomic context
> >
> > drivers/gpu/drm/i915/gvt/debugfs.c | 2 +-
> > drivers/gpu/drm/i915/gvt/handlers.c | 24 +++++++++++++-----------
> > drivers/gpu/drm/i915/gvt/mmio_context.h | 6 +++---
> > drivers/gpu/drm/i915/gvt/reg.h | 5 +++++
> > 4 files changed, 22 insertions(+), 15 deletions(-)
> _______________________________________________
> intel-gvt-dev mailing list
> intel-gvt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

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