Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/uc: Enable version reduced firmware files for newest platforms

Ceraolo Spurio, Daniele
2022-09-06T20:30:13Z

On 8/26/2022 6:17 PM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Going forwards, the intention is for GuC firmware files to be named
> for their major version only and HuC firmware files to have no version
> number in the name at all. This patch adds those entries for DG1/2 and
> ADL-P/S.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

However, looks like a new GuC minor version might land in the next
couple of days, so IMO better wait until that is confirmed before
merging this so we can do a single pull request to linux-firmware.

Daniele

> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index af425916cdf64..78b1198bcf39b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -72,11 +72,14 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
> * security fixes, etc. to be enabled.
> */
> #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_maj, guc_mmp) \
> - fw_def(DG2, 0, guc_mmp(dg2, 70, 4, 1)) \
> + fw_def(DG2, 0, guc_maj(dg2, 70, 4)) \
> + fw_def(ALDERLAKE_P, 0, guc_maj(adlp, 70, 1)) \
> fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 70, 1, 1)) \
> fw_def(ALDERLAKE_P, 0, guc_mmp(adlp, 69, 0, 3)) \
> + fw_def(ALDERLAKE_S, 0, guc_maj(tgl, 70, 1)) \
> fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 70, 1, 1)) \
> fw_def(ALDERLAKE_S, 0, guc_mmp(tgl, 69, 0, 3)) \
> + fw_def(DG1, 0, guc_maj(dg1, 70, 1)) \
> fw_def(DG1, 0, guc_mmp(dg1, 70, 1, 1)) \
> fw_def(ROCKETLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \
> fw_def(TIGERLAKE, 0, guc_mmp(tgl, 70, 1, 1)) \
> @@ -92,8 +95,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
> fw_def(SKYLAKE, 0, guc_mmp(skl, 70, 1, 1))
>
> #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_raw, huc_mmp) \
> + fw_def(ALDERLAKE_P, 0, huc_raw(tgl)) \
> fw_def(ALDERLAKE_P, 0, huc_mmp(tgl, 7, 9, 3)) \
> + fw_def(ALDERLAKE_S, 0, huc_raw(tgl)) \
> fw_def(ALDERLAKE_S, 0, huc_mmp(tgl, 7, 9, 3)) \
> + fw_def(DG1, 0, huc_raw(dg1)) \
> fw_def(DG1, 0, huc_mmp(dg1, 7, 9, 3)) \
> fw_def(ROCKETLAKE, 0, huc_mmp(tgl, 7, 9, 3)) \
> fw_def(TIGERLAKE, 0, huc_mmp(tgl, 7, 9, 3)) \