Hi Imre, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-tip/drm-tip] url: https://github.com/intel-lab-lkp/linux/commits/Imre-Deak/drm-i915-tgl-Add-locking-around-DKL-PHY-register-accesses/20221019-012209 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip patch link: https://lore.kernel.org/r/20221018172042.1449885-3-imre.deak%40intel.com patch subject: [Intel-gfx] [PATCH 3/3] drm/i915/tgl+: Sanitize DKL PHY register definitions config: x86_64-randconfig-a011 compiler: gcc-11 (Debian 11.3.0-8) 11.3.0 reproduce (this is a W=1 build): # https://github.com/intel-lab-lkp/linux/commit/7829cf13e91885a6fca2628c8164adf7e16c8c39 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Imre-Deak/drm-i915-tgl-Add-locking-around-DKL-PHY-register-accesses/20221019-012209 git checkout 7829cf13e91885a6fca2628c8164adf7e16c8c39 # save the config file mkdir build_dir && cp config build_dir/.config make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot All warnings (new ones prefixed by >>): drivers/gpu/drm/i915/display/intel_tc.c:837: warning: Function parameter or member 'work' not described in 'intel_tc_port_disconnect_phy_work' drivers/gpu/drm/i915/display/intel_tc.c:837: warning: Excess function parameter 'dig_port' description in 'intel_tc_port_disconnect_phy_work' >> drivers/gpu/drm/i915/display/intel_tc.c:978: warning: expecting prototype for intel_tc_dkl_posting_read(). Prototype was for intel_tc_dkl_phy_posting_read() instead vim +978 drivers/gpu/drm/i915/display/intel_tc.c 8c10e226266395 Imre Deak 2019-06-28 827 3e0abc7661c822 Imre Deak 2021-09-29 828 /** 3e0abc7661c822 Imre Deak 2021-09-29 829 * intel_tc_port_disconnect_phy_work: disconnect TypeC PHY from display port 3e0abc7661c822 Imre Deak 2021-09-29 830 * @dig_port: digital port 3e0abc7661c822 Imre Deak 2021-09-29 831 * 3e0abc7661c822 Imre Deak 2021-09-29 832 * Disconnect the given digital port from its TypeC PHY (handing back the 3e0abc7661c822 Imre Deak 2021-09-29 833 * control of the PHY to the TypeC subsystem). This will happen in a delayed 3e0abc7661c822 Imre Deak 2021-09-29 834 * manner after each aux transactions and modeset disables. 3e0abc7661c822 Imre Deak 2021-09-29 835 */ 3e0abc7661c822 Imre Deak 2021-09-29 836 static void intel_tc_port_disconnect_phy_work(struct work_struct *work) 8c10e226266395 Imre Deak 2019-06-28 @837 { 3e0abc7661c822 Imre Deak 2021-09-29 838 struct intel_digital_port *dig_port = 3e0abc7661c822 Imre Deak 2021-09-29 839 container_of(work, struct intel_digital_port, tc_disconnect_phy_work.work); 24a7bfe0c2d7ae Imre Deak 2019-06-28 840 3e0abc7661c822 Imre Deak 2021-09-29 841 mutex_lock(&dig_port->tc_lock); 3e0abc7661c822 Imre Deak 2021-09-29 842 3e0abc7661c822 Imre Deak 2021-09-29 843 if (!dig_port->tc_link_refcount) 3e0abc7661c822 Imre Deak 2021-09-29 844 intel_tc_port_update_mode(dig_port, 1, true); 24a7bfe0c2d7ae Imre Deak 2019-06-28 845 3e0abc7661c822 Imre Deak 2021-09-29 846 mutex_unlock(&dig_port->tc_lock); 24a7bfe0c2d7ae Imre Deak 2019-06-28 847 } 24a7bfe0c2d7ae Imre Deak 2019-06-28 848 151ec347b06a2f Imre Deak 2021-06-10 849 /** 3e0abc7661c822 Imre Deak 2021-09-29 850 * intel_tc_port_flush_work: flush the work disconnecting the PHY 151ec347b06a2f Imre Deak 2021-06-10 851 * @dig_port: digital port 151ec347b06a2f Imre Deak 2021-06-10 852 * 3e0abc7661c822 Imre Deak 2021-09-29 853 * Flush the delayed work disconnecting an idle PHY. 151ec347b06a2f Imre Deak 2021-06-10 854 */ 3e0abc7661c822 Imre Deak 2021-09-29 855 void intel_tc_port_flush_work(struct intel_digital_port *dig_port) 151ec347b06a2f Imre Deak 2021-06-10 856 { 3e0abc7661c822 Imre Deak 2021-09-29 857 flush_delayed_work(&dig_port->tc_disconnect_phy_work); 3e0abc7661c822 Imre Deak 2021-09-29 858 } 3e0abc7661c822 Imre Deak 2021-09-29 859 3e0abc7661c822 Imre Deak 2021-09-29 860 void intel_tc_port_unlock(struct intel_digital_port *dig_port) 3e0abc7661c822 Imre Deak 2021-09-29 861 { 3e0abc7661c822 Imre Deak 2021-09-29 862 if (!dig_port->tc_link_refcount && dig_port->tc_mode != TC_PORT_DISCONNECTED) 3e0abc7661c822 Imre Deak 2021-09-29 863 queue_delayed_work(system_unbound_wq, &dig_port->tc_disconnect_phy_work, 3e0abc7661c822 Imre Deak 2021-09-29 864 msecs_to_jiffies(1000)); 3e0abc7661c822 Imre Deak 2021-09-29 865 3e0abc7661c822 Imre Deak 2021-09-29 866 mutex_unlock(&dig_port->tc_lock); 151ec347b06a2f Imre Deak 2021-06-10 867 } 151ec347b06a2f Imre Deak 2021-06-10 868 d0d392a8deed84 Jani Nikula 2019-08-06 869 bool intel_tc_port_ref_held(struct intel_digital_port *dig_port) d0d392a8deed84 Jani Nikula 2019-08-06 870 { d0d392a8deed84 Jani Nikula 2019-08-06 871 return mutex_is_locked(&dig_port->tc_lock) || d0d392a8deed84 Jani Nikula 2019-08-06 872 dig_port->tc_link_refcount; d0d392a8deed84 Jani Nikula 2019-08-06 873 } d0d392a8deed84 Jani Nikula 2019-08-06 874 24a7bfe0c2d7ae Imre Deak 2019-06-28 875 void intel_tc_port_get_link(struct intel_digital_port *dig_port, 24a7bfe0c2d7ae Imre Deak 2019-06-28 876 int required_lanes) 24a7bfe0c2d7ae Imre Deak 2019-06-28 877 { 3e0abc7661c822 Imre Deak 2021-09-29 878 __intel_tc_port_lock(dig_port, required_lanes); 24a7bfe0c2d7ae Imre Deak 2019-06-28 879 dig_port->tc_link_refcount++; 24a7bfe0c2d7ae Imre Deak 2019-06-28 880 intel_tc_port_unlock(dig_port); 24a7bfe0c2d7ae Imre Deak 2019-06-28 881 } 24a7bfe0c2d7ae Imre Deak 2019-06-28 882 24a7bfe0c2d7ae Imre Deak 2019-06-28 883 void intel_tc_port_put_link(struct intel_digital_port *dig_port) 24a7bfe0c2d7ae Imre Deak 2019-06-28 884 { 3e0abc7661c822 Imre Deak 2021-09-29 885 intel_tc_port_lock(dig_port); 3e0abc7661c822 Imre Deak 2021-09-29 886 --dig_port->tc_link_refcount; 3e0abc7661c822 Imre Deak 2021-09-29 887 intel_tc_port_unlock(dig_port); b58a88682093b3 Imre Deak 2021-09-29 888 b58a88682093b3 Imre Deak 2021-09-29 889 /* b58a88682093b3 Imre Deak 2021-09-29 890 * Disconnecting the PHY after the PHY's PLL gets disabled may b58a88682093b3 Imre Deak 2021-09-29 891 * hang the system on ADL-P, so disconnect the PHY here synchronously. b58a88682093b3 Imre Deak 2021-09-29 892 * TODO: remove this once the root cause of the ordering requirement b58a88682093b3 Imre Deak 2021-09-29 893 * is found/fixed. b58a88682093b3 Imre Deak 2021-09-29 894 */ b58a88682093b3 Imre Deak 2021-09-29 895 intel_tc_port_flush_work(dig_port); bc85328ff431e4 Imre Deak 2019-06-28 896 } bc85328ff431e4 Imre Deak 2019-06-28 897 7829cf13e91885 Imre Deak 2022-10-18 898 static void dkl_set_hip_idx(struct drm_i915_private *i915, struct intel_tc_dkl_reg reg) 1e6345b5b55c37 Imre Deak 2022-10-18 899 { 1e6345b5b55c37 Imre Deak 2022-10-18 900 enum tc_port tc_port = DKL_REG_TC_PORT(reg); 1e6345b5b55c37 Imre Deak 2022-10-18 901 1e6345b5b55c37 Imre Deak 2022-10-18 902 drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); 1e6345b5b55c37 Imre Deak 2022-10-18 903 1e6345b5b55c37 Imre Deak 2022-10-18 904 intel_de_write(i915, 1e6345b5b55c37 Imre Deak 2022-10-18 905 HIP_INDEX_REG(tc_port), 7829cf13e91885 Imre Deak 2022-10-18 906 HIP_INDEX_VAL(tc_port, reg.bank_idx)); 1e6345b5b55c37 Imre Deak 2022-10-18 907 } 1e6345b5b55c37 Imre Deak 2022-10-18 908 1e6345b5b55c37 Imre Deak 2022-10-18 909 /** 1e6345b5b55c37 Imre Deak 2022-10-18 910 * intel_tc_dkl_read - read a Dekel PHY register 1e6345b5b55c37 Imre Deak 2022-10-18 911 * @i915: i915 device instance 1e6345b5b55c37 Imre Deak 2022-10-18 912 * @reg: Dekel PHY register 1e6345b5b55c37 Imre Deak 2022-10-18 913 * 1e6345b5b55c37 Imre Deak 2022-10-18 914 * Read the @reg Dekel PHY register. 1e6345b5b55c37 Imre Deak 2022-10-18 915 * 1e6345b5b55c37 Imre Deak 2022-10-18 916 * Returns the read value. 1e6345b5b55c37 Imre Deak 2022-10-18 917 */ 7829cf13e91885 Imre Deak 2022-10-18 918 u32 intel_tc_dkl_read(struct drm_i915_private *i915, struct intel_tc_dkl_reg reg) 1e6345b5b55c37 Imre Deak 2022-10-18 919 { 1e6345b5b55c37 Imre Deak 2022-10-18 920 u32 val; 1e6345b5b55c37 Imre Deak 2022-10-18 921 1e6345b5b55c37 Imre Deak 2022-10-18 922 spin_lock(&i915->display.tc.dkl_lock); 1e6345b5b55c37 Imre Deak 2022-10-18 923 7829cf13e91885 Imre Deak 2022-10-18 924 dkl_set_hip_idx(i915, reg); 7829cf13e91885 Imre Deak 2022-10-18 925 val = intel_de_read(i915, DKL_REG_MMIO(reg)); 1e6345b5b55c37 Imre Deak 2022-10-18 926 1e6345b5b55c37 Imre Deak 2022-10-18 927 spin_unlock(&i915->display.tc.dkl_lock); 1e6345b5b55c37 Imre Deak 2022-10-18 928 1e6345b5b55c37 Imre Deak 2022-10-18 929 return val; 1e6345b5b55c37 Imre Deak 2022-10-18 930 } 1e6345b5b55c37 Imre Deak 2022-10-18 931 1e6345b5b55c37 Imre Deak 2022-10-18 932 /** 1e6345b5b55c37 Imre Deak 2022-10-18 933 * intel_tc_dkl_write - write a Dekel PHY register 1e6345b5b55c37 Imre Deak 2022-10-18 934 * @i915: i915 device instance 1e6345b5b55c37 Imre Deak 2022-10-18 935 * @reg: Dekel PHY register 1e6345b5b55c37 Imre Deak 2022-10-18 936 * @val: value to write 1e6345b5b55c37 Imre Deak 2022-10-18 937 * 1e6345b5b55c37 Imre Deak 2022-10-18 938 * Write @val to the @reg Dekel PHY register. 1e6345b5b55c37 Imre Deak 2022-10-18 939 */ 7829cf13e91885 Imre Deak 2022-10-18 940 void intel_tc_dkl_write(struct drm_i915_private *i915, struct intel_tc_dkl_reg reg, u32 val) 1e6345b5b55c37 Imre Deak 2022-10-18 941 { 1e6345b5b55c37 Imre Deak 2022-10-18 942 spin_lock(&i915->display.tc.dkl_lock); 1e6345b5b55c37 Imre Deak 2022-10-18 943 7829cf13e91885 Imre Deak 2022-10-18 944 dkl_set_hip_idx(i915, reg); 7829cf13e91885 Imre Deak 2022-10-18 945 intel_de_write(i915, DKL_REG_MMIO(reg), val); 1e6345b5b55c37 Imre Deak 2022-10-18 946 1e6345b5b55c37 Imre Deak 2022-10-18 947 spin_unlock(&i915->display.tc.dkl_lock); 1e6345b5b55c37 Imre Deak 2022-10-18 948 } 1e6345b5b55c37 Imre Deak 2022-10-18 949 1e6345b5b55c37 Imre Deak 2022-10-18 950 /** 1e6345b5b55c37 Imre Deak 2022-10-18 951 * intel_tc_dkl_rmw - read-modify-write a Dekel PHY register 1e6345b5b55c37 Imre Deak 2022-10-18 952 * @i915: i915 device instance 1e6345b5b55c37 Imre Deak 2022-10-18 953 * @reg: Dekel PHY register 1e6345b5b55c37 Imre Deak 2022-10-18 954 * @clear: mask to clear 1e6345b5b55c37 Imre Deak 2022-10-18 955 * @set: mask to set 1e6345b5b55c37 Imre Deak 2022-10-18 956 * 1e6345b5b55c37 Imre Deak 2022-10-18 957 * Read the @reg Dekel PHY register, clearing then setting the @clear/@set bits in it, and writing 1e6345b5b55c37 Imre Deak 2022-10-18 958 * this value back to the register if the value differs from the read one. 1e6345b5b55c37 Imre Deak 2022-10-18 959 */ 7829cf13e91885 Imre Deak 2022-10-18 960 void intel_tc_dkl_rmw(struct drm_i915_private *i915, struct intel_tc_dkl_reg reg, u32 clear, u32 set) 1e6345b5b55c37 Imre Deak 2022-10-18 961 { 1e6345b5b55c37 Imre Deak 2022-10-18 962 spin_lock(&i915->display.tc.dkl_lock); 1e6345b5b55c37 Imre Deak 2022-10-18 963 7829cf13e91885 Imre Deak 2022-10-18 964 dkl_set_hip_idx(i915, reg); 7829cf13e91885 Imre Deak 2022-10-18 965 intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set); 1e6345b5b55c37 Imre Deak 2022-10-18 966 1e6345b5b55c37 Imre Deak 2022-10-18 967 spin_unlock(&i915->display.tc.dkl_lock); 1e6345b5b55c37 Imre Deak 2022-10-18 968 } 1e6345b5b55c37 Imre Deak 2022-10-18 969 1e6345b5b55c37 Imre Deak 2022-10-18 970 /** 1e6345b5b55c37 Imre Deak 2022-10-18 971 * intel_tc_dkl_posting_read - do a posting read from a Dekel PHY register 1e6345b5b55c37 Imre Deak 2022-10-18 972 * @i915: i915 device instance 1e6345b5b55c37 Imre Deak 2022-10-18 973 * @reg: Dekel PHY register 1e6345b5b55c37 Imre Deak 2022-10-18 974 * 1e6345b5b55c37 Imre Deak 2022-10-18 975 * Read the @reg Dekel PHY register without returning the read value. 1e6345b5b55c37 Imre Deak 2022-10-18 976 */ 7829cf13e91885 Imre Deak 2022-10-18 977 void intel_tc_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_tc_dkl_reg reg) 1e6345b5b55c37 Imre Deak 2022-10-18 @978 { 1e6345b5b55c37 Imre Deak 2022-10-18 979 spin_lock(&i915->display.tc.dkl_lock); 1e6345b5b55c37 Imre Deak 2022-10-18 980 7829cf13e91885 Imre Deak 2022-10-18 981 dkl_set_hip_idx(i915, reg); 7829cf13e91885 Imre Deak 2022-10-18 982 intel_de_posting_read(i915, DKL_REG_MMIO(reg)); 1e6345b5b55c37 Imre Deak 2022-10-18 983 1e6345b5b55c37 Imre Deak 2022-10-18 984 spin_unlock(&i915->display.tc.dkl_lock); 1e6345b5b55c37 Imre Deak 2022-10-18 985 } 1e6345b5b55c37 Imre Deak 2022-10-18 986 -- 0-DAY CI Kernel Test Service https://01.org/lkp