Re: [Intel-gfx] [PATCH 3/3] drm/i915/irq: split out display irq handling

kernel test robot
2023-05-04T20:15:56Z

Hi Jani,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-tip/drm-tip]

url: https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-i915-irq-relocate-gmbus-and-dp-aux-irq-handlers/20230505-005945
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/d175e7571d188e791a3b691919d22b6a55ba8b16.1683219363.git.jani.nikula%40intel.com
patch subject: [Intel-gfx] [PATCH 3/3] drm/i915/irq: split out display irq handling
config: x86_64-randconfig-a002-20230501 (https://download.01.org/0day-ci/archive/20230505/202305050427.FtwE2pE7-lkp@intel.com/config)
compiler: gcc-11 (Debian 11.3.0-12) 11.3.0
reproduce (this is a W=1 build):
# https://github.com/intel-lab-lkp/linux/commit/8ace6b1f9c8d5dce9faa2181a85d61b33d550b8e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jani-Nikula/drm-i915-irq-relocate-gmbus-and-dp-aux-irq-handlers/20230505-005945
git checkout 8ace6b1f9c8d5dce9faa2181a85d61b33d550b8e
# save the config file
mkdir build_dir && cp config build_dir/.config
make W=1 O=build_dir ARCH=x86_64 olddefconfig
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305050427.FtwE2pE7-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_display_irq.c:411:41: warning: argument 3 of type 'u32[4]' {aka 'unsigned int[4]'} with mismatched bound [-Warray-parameter=]
411 | u32 iir, u32 pipe_stats[I915_MAX_PIPES])
| ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/i915/display/intel_display_irq.c:10:
drivers/gpu/drm/i915/display/intel_display_irq.h:72:73: note: previously declared as 'u32 *' {aka 'unsigned int *'}
72 | void i9xx_pipestat_irq_ack(struct drm_i915_private *i915, u32 iir, u32 *pipe_stats);
| ~~~~~^~~~~~~~~~
drivers/gpu/drm/i915/display/intel_display_irq.c:477:45: warning: argument 3 of type 'u32[4]' {aka 'unsigned int[4]'} with mismatched bound [-Warray-parameter=]
477 | u16 iir, u32 pipe_stats[I915_MAX_PIPES])
| ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/i915/display/intel_display_irq.c:10:
drivers/gpu/drm/i915/display/intel_display_irq.h:77:77: note: previously declared as 'u32 *' {aka 'unsigned int *'}
77 | void i8xx_pipestat_irq_handler(struct drm_i915_private *i915, u16 iir, u32 *pipe_stats);
| ~~~~~^~~~~~~~~~
drivers/gpu/drm/i915/display/intel_display_irq.c:494:45: warning: argument 3 of type 'u32[4]' {aka 'unsigned int[4]'} with mismatched bound [-Warray-parameter=]
494 | u32 iir, u32 pipe_stats[I915_MAX_PIPES])
| ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/i915/display/intel_display_irq.c:10:
drivers/gpu/drm/i915/display/intel_display_irq.h:74:77: note: previously declared as 'u32 *' {aka 'unsigned int *'}
74 | void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 *pipe_stats);
| ~~~~~^~~~~~~~~~
drivers/gpu/drm/i915/display/intel_display_irq.c:518:45: warning: argument 3 of type 'u32[4]' {aka 'unsigned int[4]'} with mismatched bound [-Warray-parameter=]
518 | u32 iir, u32 pipe_stats[I915_MAX_PIPES])
| ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/i915/display/intel_display_irq.c:10:
drivers/gpu/drm/i915/display/intel_display_irq.h:75:77: note: previously declared as 'u32 *' {aka 'unsigned int *'}
75 | void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 *pipe_stats);
| ~~~~~^~~~~~~~~~
drivers/gpu/drm/i915/display/intel_display_irq.c:545:42: warning: argument 2 of type 'u32[4]' {aka 'unsigned int[4]'} with mismatched bound [-Warray-parameter=]
545 | u32 pipe_stats[I915_MAX_PIPES])
| ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/i915/display/intel_display_irq.c:10:
drivers/gpu/drm/i915/display/intel_display_irq.h:76:74: note: previously declared as 'u32 *' {aka 'unsigned int *'}
76 | void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 *pipe_stats);
| ~~~~~^~~~~~~~~~

vim +411 drivers/gpu/drm/i915/display/intel_display_irq.c

409
410 void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
> 411 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
412 {
413 enum pipe pipe;
414
415 spin_lock(&dev_priv->irq_lock);
416
417 if (!dev_priv->display_irqs_enabled) {
418 spin_unlock(&dev_priv->irq_lock);
419 return;
420 }
421
422 for_each_pipe(dev_priv, pipe) {
423 i915_reg_t reg;
424 u32 status_mask, enable_mask, iir_bit = 0;
425
426 /*
427 * PIPESTAT bits get signalled even when the interrupt is
428 * disabled with the mask bits, and some of the status bits do
429 * not generate interrupts at all (like the underrun bit). Hence
430 * we need to be careful that we only handle what we want to
431 * handle.
432 */
433
434 /* fifo underruns are filterered in the underrun handler. */
435 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
436
437 switch (pipe) {
438 default:
439 case PIPE_A:
440 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
441 break;
442 case PIPE_B:
443 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
444 break;
445 case PIPE_C:
446 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
447 break;
448 }
449 if (iir & iir_bit)
450 status_mask |= dev_priv->pipestat_irq_mask[pipe];
451
452 if (!status_mask)
453 continue;
454
455 reg = PIPESTAT(pipe);
456 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;
457 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
458
459 /*
460 * Clear the PIPE*STAT regs before the IIR
461 *
462 * Toggle the enable bits to make sure we get an
463 * edge in the ISR pipe event bit if we don't clear
464 * all the enabled status bits. Otherwise the edge
465 * triggered IIR on i965/g4x wouldn't notice that
466 * an interrupt is still pending.
467 */
468 if (pipe_stats[pipe]) {
469 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]);
470 intel_uncore_write(&dev_priv->uncore, reg, enable_mask);
471 }
472 }
473 spin_unlock(&dev_priv->irq_lock);
474 }
475

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