[Intel-gfx] [CI DO_NOT_MERGE 1/2] drm/i915/mtl: do not enable render power-gating on MTL

Andrzej Hajda
2023-05-16T22:04:01Z

Multiple CI tests fails if render power gatins is enabled,
with forcewake ack timeouts.
BSpec 52698 clearly states it should be 0.
Media gate seems also problematic.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---

Let's try disabling render and media pg.
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 908a3d0f2343f4..cd63eaf0d0c8de 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -117,9 +117,12 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
GEN6_RC_CTL_RC6_ENABLE |
GEN6_RC_CTL_EI_MODE(1);

+ /* BSpec: 52698, GEN9_RENDER_PG_ENABLE must be 0 for MTL */
+ if (IS_METEORLAKE(gt->i915))
+ pg_enable = 0;
/* Wa_16011777198 - Render powergating must remain disabled */
- if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
- IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
+ else if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
+ IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
pg_enable =
GEN9_MEDIA_PG_ENABLE |
GEN11_MEDIA_SAMPLER_PG_ENABLE;
--
2.34.1