[Intel-gfx] [PATCH 00/11] Add DSC fractional bpp support

[Intel-gfx] [PATCH 00/11] Add DSC fractional bpp support

[Ankit Nautiyal]

This patch series adds support for having fractional compressed bpp
for MTL+. The initial patches that lay groundwork to iterate over valid
compressed bpps to select the 'best' compressed bpp with optimal link
configuration are taken from upstream pending series:
https://patchwork.freedesktop.org/series/105200/

The later patches, add changes to accommodate compressed bpp with
fractional part, including changes to QP calculations.
To get the 'best' compressed bpp, we iterate over the valid compressed
bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
sink support.

The last 2 patches add support to depict DSC sink's fractional support,
and debugfs to enforce use of fractional bpp, while choosing an
appropriate compressed bpp.

Ankit Nautiyal (8):
  drm/i915/dp: Check if force dsc bpc <= max requested bpc
  drm/display/dp: Add helper function to get DSC bpp prescision
  drm/i915/dp: Rename helpers to get DSC max pipe bpp and max output bpp
  drm/i915/dp: Get optimal link config to have best compressed bpp
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
  drm/i915/dp: Iterate over output bpp with fractional step size

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

 drivers/gpu/drm/display/drm_dp_helper.c       |  27 ++
 drivers/gpu/drm/i915/display/icl_dsi.c        |  10 +-
 drivers/gpu/drm/i915/display/intel_audio.c    |  12 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_display.h  |   2 +-
 .../drm/i915/display/intel_display_debugfs.c  |  84 +++++
 .../drm/i915/display/intel_display_types.h    |  17 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 318 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   3 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |   2 +-
 .../gpu/drm/i915/display/intel_qp_tables.c    |   3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  16 +-
 include/drm/display/drm_dp_helper.h           |   1 +
 14 files changed, 421 insertions(+), 82 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH 00/11] Add DSC fractional bpp support

[Ankit Nautiyal]

This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series: https://patchwork.freedesktop.org/series/105200/).

The later patches, add changes to accommodate compressed bpp with
fractional part, including changes to QP calculations.
To get the 'best' compressed bpp, we iterate over the valid compressed
bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
sink support.

The last 2 patches add support to depict DSC sink's fractional support,
and debugfs to enforce use of fractional bpp, while choosing an
appropriate compressed bpp.

Rev10: Rebased and added DSC Fractional support for DP MST.

Ankit Nautiyal (8):
  drm/display/dp: Add helper function to get DSC bpp precision
  drm/i915/display: Store compressed bpp in U6.4 format
  drm/i915/display: Consider fractional vdsc bpp while computing m_n
    values
  drm/i915/audio: Consider fractional vdsc bpp while computing tu_data
  drm/i915/dp: Iterate over output bpp with fractional step size
  drm/i915/dp_mst: Use precision of 1/16 for computing bpp
  drm/i916/dp_mst: Iterate over the DSC bpps as per DSC precision
    support
  drm/i915/dp_mst: Add support for forcing dsc fractional bpp via
    debugfs

Swati Sharma (2):
  drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
  drm/i915/dsc: Allow DSC only with fractional bpp when forced from
    debugfs

Vandita Kulkarni (1):
  drm/i915/dsc/mtl: Add support for fractional bpp

 drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
 drivers/gpu/drm/i915/display/icl_dsi.c        | 10 +--
 drivers/gpu/drm/i915/display/intel_audio.c    | 16 ++--
 drivers/gpu/drm/i915/display/intel_bios.c     |  4 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  5 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  6 +-
 .../drm/i915/display/intel_display_debugfs.c  | 84 ++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  4 +-
 drivers/gpu/drm/i915/display/intel_dp.c       | 87 +++++++++++--------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 85 +++++++++++-------
 drivers/gpu/drm/i915/display/intel_fdi.c      |  3 +-
 drivers/gpu/drm/i915/display/intel_link_bw.c  |  2 +-
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 29 +++++--
 include/drm/display/drm_dp_helper.h           |  1 +
 15 files changed, 266 insertions(+), 100 deletions(-)

-- 
2.40.1

[Intel-gfx] [PATCH 01/11] drm/display/dp: Add helper function to get DSC bpp precision

[Ankit Nautiyal]

Add helper to get the DSC bits_per_pixel precision for the DP sink.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
Acked-by: Maxime Ripard <mripard@kernel.org>
---
 drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
 include/drm/display/drm_dp_helper.h     |  1 +
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 72ba9ae89f86..d72b6f9a352c 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2328,6 +2328,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
 }
 EXPORT_SYMBOL(drm_dp_read_desc);
 
+/**
+ * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
+ * @dsc_dpcd: DSC capabilities from DPCD
+ *
+ * Returns the bpp precision supported by the DP sink.
+ */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
+
+	switch (bpp_increment_dpcd) {
+	case DP_DSC_BITS_PER_PIXEL_1_16:
+		return 16;
+	case DP_DSC_BITS_PER_PIXEL_1_8:
+		return 8;
+	case DP_DSC_BITS_PER_PIXEL_1_4:
+		return 4;
+	case DP_DSC_BITS_PER_PIXEL_1_2:
+		return 2;
+	case DP_DSC_BITS_PER_PIXEL_1_1:
+		return 1;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
+
 /**
  * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
  * supported by the DSC sink.
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index caee29d28463..c5f1079acb3b 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 }
 
 /* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
 				   bool is_edp);
 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
-- 
2.40.1

[Intel-gfx] [PATCH 02/11] drm/i915/display: Store compressed bpp in U6.4 format

[Ankit Nautiyal]

DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.

v2:
-Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
 with compressed bpp. (Suraj)
-Fix comment styling. (Suraj)

v3:
-Add separate file for 6.4 fixed point helper(Jani, Nikula)
-Add comment for magic values(Suraj)

v4:
-Fix checkpatch warnings caused by renaming(Suraj)

v5:
-Rebase.
-Use existing helpers for conversion of bpp_int to bpp_x16
 and vice versa.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        | 10 +++----
 drivers/gpu/drm/i915/display/intel_audio.c    |  2 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |  4 +--
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  5 ++--
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../drm/i915/display/intel_display_types.h    |  3 ++-
 drivers/gpu/drm/i915/display/intel_dp.c       | 27 ++++++++++---------
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_link_bw.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  4 +--
 10 files changed, 33 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c4585e445198..481fcb650850 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
 	int bpp;
 
 	if (crtc_state->dsc.compression_enable)
-		bpp = crtc_state->dsc.compressed_bpp;
+		bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
 	else
 		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
@@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	 * compressed and non-compressed bpp.
 	 */
 	if (crtc_state->dsc.compression_enable) {
-		mul = crtc_state->dsc.compressed_bpp;
+		mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
 		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 	}
 
@@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 		int bpp, line_time_us, byte_clk_period_ns;
 
 		if (crtc_state->dsc.compression_enable)
-			bpp = crtc_state->dsc.compressed_bpp;
+			bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
 		else
 			bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
@@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode =
 					&pipe_config->hw.adjusted_mode;
 
-	if (pipe_config->dsc.compressed_bpp) {
-		int div = pipe_config->dsc.compressed_bpp;
+	if (pipe_config->dsc.compressed_bpp_x16) {
+		int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
 		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
 		adjusted_mode->crtc_htotal =
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 19605264a35c..aa93ccd6c2aa 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
-	vdsc_bpp = crtc_state->dsc.compressed_bpp;
+	vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
 	cdclk = i915->display.cdclk.hw.cdclk;
 	/* fec= 0.972261, using rounding multiplier of 1000000 */
 	fec_coeff = 972261;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 719fb550342b..2fd72b2fd109 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3414,8 +3414,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
 
 	crtc_state->pipe_bpp = bpc * 3;
 
-	crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
-					     VBT_DSC_MAX_BPP(dsc->max_bpp));
+	crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state->pipe_bpp,
+							    VBT_DSC_MAX_BPP(dsc->max_bpp)));
 
 	/*
 	 * FIXME: This is ugly, and slice count should take DSC engine
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c4839c67cb0f..b93d1ad7936d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2598,8 +2598,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits
 		 */
 		int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
-		int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
-				   (2 * bigjoiner_interface_bits);
+		int min_cdclk_bj =
+			(to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
+			 pixel_clock) / (2 * bigjoiner_interface_bits);
 
 		min_cdclk = max(min_cdclk, min_cdclk_bj);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3effafcbb411..b4a8e3087e50 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5434,7 +5434,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_I(dsc.compression_enable);
 	PIPE_CONF_CHECK_I(dsc.dsc_split);
-	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
+	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
 
 	PIPE_CONF_CHECK_BOOL(splitter.enable);
 	PIPE_CONF_CHECK_I(splitter.link_count);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 926bf9c1a3ed..19e7e6e2e7a6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1362,7 +1362,8 @@ struct intel_crtc_state {
 	struct {
 		bool compression_enable;
 		bool dsc_split;
-		u16 compressed_bpp;
+		/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
+		u16 compressed_bpp_x16;
 		u8 slice_count;
 		struct drm_dsc_config config;
 	} dsc;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 37d7c9c2d695..4ad3718c3c7d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1885,7 +1885,8 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      valid_dsc_bpp[i],
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
+			pipe_config->dsc.compressed_bpp_x16 =
+				to_bpp_x16(valid_dsc_bpp[i]);
 			return 0;
 		}
 	}
@@ -1923,7 +1924,8 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      compressed_bpp,
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp = compressed_bpp;
+			pipe_config->dsc.compressed_bpp_x16 =
+				to_bpp_x16(compressed_bpp);
 			return 0;
 		}
 	}
@@ -2120,7 +2122,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	/* Compressed BPP should be less than the Input DSC bpp */
 	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
 
-	pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
+	pipe_config->dsc.compressed_bpp_x16 =
+		to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
 
 	pipe_config->pipe_bpp = pipe_bpp;
 
@@ -2209,18 +2212,18 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	ret = intel_dp_dsc_compute_params(connector, pipe_config);
 	if (ret < 0) {
 		drm_dbg_kms(&dev_priv->drm,
-			    "Cannot compute valid DSC parameters for Input Bpp = %d "
-			    "Compressed BPP = %d\n",
+			    "Cannot compute valid DSC parameters for Input Bpp = %d"
+			    "Compressed BPP = " BPP_X16_FMT "\n",
 			    pipe_config->pipe_bpp,
-			    pipe_config->dsc.compressed_bpp);
+			    BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
 		return ret;
 	}
 
 	pipe_config->dsc.compression_enable = true;
 	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
-		    "Compressed Bpp = %d Slice Count = %d\n",
+		    "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
 		    pipe_config->pipe_bpp,
-		    pipe_config->dsc.compressed_bpp,
+		    BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
 		    pipe_config->dsc.slice_count);
 
 	return 0;
@@ -2393,15 +2396,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 
 	if (pipe_config->dsc.compression_enable) {
 		drm_dbg_kms(&i915->drm,
-			    "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
+			    "DP lane count %d clock %d Input bpp %d Compressed bpp " BPP_X16_FMT "\n",
 			    pipe_config->lane_count, pipe_config->port_clock,
 			    pipe_config->pipe_bpp,
-			    pipe_config->dsc.compressed_bpp);
+			    BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
 
 		drm_dbg_kms(&i915->drm,
 			    "DP link rate required %i available %i\n",
 			    intel_dp_link_required(adjusted_mode->crtc_clock,
-						   pipe_config->dsc.compressed_bpp),
+						   to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),
 			    intel_dp_max_data_rate(pipe_config->port_clock,
 						   pipe_config->lane_count));
 	} else {
@@ -2838,7 +2841,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
 
 	if (pipe_config->dsc.compression_enable)
-		link_bpp = pipe_config->dsc.compressed_bpp;
+		link_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
 	else
 		link_bpp = intel_dp_output_bpp(pipe_config->output_format,
 					       pipe_config->pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 107f7418ddc5..31461ea25f7c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -227,7 +227,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 		if (!dsc)
 			crtc_state->pipe_bpp = bpp;
 		else
-			crtc_state->dsc.compressed_bpp = bpp;
+			crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
 		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c b/drivers/gpu/drm/i915/display/intel_link_bw.c
index 390db5c0c24a..02a0af2aa5ba 100644
--- a/drivers/gpu/drm/i915/display/intel_link_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_link_bw.c
@@ -70,7 +70,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
 			return PTR_ERR(crtc_state);
 
 		if (crtc_state->dsc.compression_enable)
-			link_bpp = crtc_state->dsc.compressed_bpp;
+			link_bpp = crtc_state->dsc.compressed_bpp_x16;
 		else
 			/*
 			 * TODO: for YUV420 the actual link bpp is only half
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 6757dbae9ee5..3a1ed574edbb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
-	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
+	u16 compressed_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
 	int err;
 	int ret;
 
@@ -874,7 +874,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 	if (vdsc_cfg->native_420)
 		vdsc_cfg->bits_per_pixel >>= 1;
 
-	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+	crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
 
 	/* PPS 2 */
 	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
-- 
2.40.1

[Intel-gfx] [PATCH 03/11] drm/i915/display: Consider fractional vdsc bpp while computing m_n values

[Ankit Nautiyal]

MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.

v1:
Replace the computation of 'data_clock' with 'data_clock =
DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng).

v2:
Rebase and pass bits_per_pixel in U6.4 format.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
---
 drivers/gpu/drm/i915/display/intel_display.c |  4 ++--
 drivers/gpu/drm/i915/display/intel_dp.c      | 16 ++++++++--------
 drivers/gpu/drm/i915/display/intel_dp_mst.c  | 14 +++++++-------
 drivers/gpu/drm/i915/display/intel_fdi.c     |  3 ++-
 4 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b4a8e3087e50..125903007a29 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2415,12 +2415,12 @@ add_bw_alloc_overhead(int link_clock, int bw_overhead,
 }
 
 void
-intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
+intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
 		       int pixel_clock, int link_clock,
 		       int bw_overhead,
 		       struct intel_link_m_n *m_n)
 {
-	u32 data_clock = bits_per_pixel * pixel_clock;
+	u32 data_clock = DIV_ROUND_UP(bits_per_pixel_x16 * pixel_clock, 16);
 	u32 data_m;
 	u32 data_n;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4ad3718c3c7d..246f50d1f030 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2663,7 +2663,7 @@ static bool can_enable_drrs(struct intel_connector *connector,
 static void
 intel_dp_drrs_compute_config(struct intel_connector *connector,
 			     struct intel_crtc_state *pipe_config,
-			     int link_bpp)
+			     int link_bpp_x16)
 {
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	const struct drm_display_mode *downclock_mode =
@@ -2688,7 +2688,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
 	if (pipe_config->splitter.enable)
 		pixel_clock /= pipe_config->splitter.link_count;
 
-	intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
+	intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
 			       pipe_config->port_clock,
 			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),
 			       &pipe_config->dp_m2_n2);
@@ -2792,7 +2792,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	const struct drm_display_mode *fixed_mode;
 	struct intel_connector *connector = intel_dp->attached_connector;
-	int ret = 0, link_bpp;
+	int ret = 0, link_bpp_x16;
 
 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
 		pipe_config->has_pch_encoder = true;
@@ -2841,10 +2841,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
 
 	if (pipe_config->dsc.compression_enable)
-		link_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
+		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
 	else
-		link_bpp = intel_dp_output_bpp(pipe_config->output_format,
-					       pipe_config->pipe_bpp);
+		link_bpp_x16 = to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
+							      pipe_config->pipe_bpp));
 
 	if (intel_dp->mso_link_count) {
 		int n = intel_dp->mso_link_count;
@@ -2868,7 +2868,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 
-	intel_link_compute_m_n(link_bpp,
+	intel_link_compute_m_n(link_bpp_x16,
 			       pipe_config->lane_count,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
@@ -2884,7 +2884,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	intel_vrr_compute_config(pipe_config, conn_state);
 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
-	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
+	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 31461ea25f7c..5c7e9d296483 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -70,7 +70,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
 
 static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
 				    const struct intel_connector *connector,
-				    bool ssc, bool dsc, int bpp)
+				    bool ssc, bool dsc, int bpp_x16)
 {
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
@@ -94,7 +94,7 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
 	overhead = drm_dp_bw_overhead(crtc_state->lane_count,
 				      adjusted_mode->hdisplay,
 				      dsc_slice_count,
-				      to_bpp_x16(bpp),
+				      bpp_x16,
 				      flags);
 
 	/*
@@ -107,16 +107,16 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
 static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
 				     const struct intel_connector *connector,
 				     bool ssc, bool dsc,
-				     int bpp,
+				     int bpp_x16,
 				     struct intel_link_m_n *m_n)
 {
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 	int overhead = intel_dp_mst_bw_overhead(crtc_state,
 						connector,
-						ssc, dsc, bpp);
+						ssc, dsc, bpp_x16);
 
-	intel_link_compute_m_n(bpp, crtc_state->lane_count,
+	intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,
 			       adjusted_mode->crtc_clock,
 			       crtc_state->port_clock,
 			       overhead,
@@ -180,9 +180,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 		link_bpp = dsc ? bpp :
 			intel_dp_output_bpp(crtc_state->output_format, bpp);
 
-		intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp,
+		intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, to_bpp_x16(link_bpp),
 					 &crtc_state->dp_m_n);
-		intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp,
+		intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, to_bpp_x16(link_bpp),
 					 &remote_m_n);
 
 		/*
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 1d87fbc1e813..295a0f24ebbf 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -339,7 +339,8 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
 
 	pipe_config->fdi_lanes = lane;
 
-	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
+	intel_link_compute_m_n(to_bpp_x16(pipe_config->pipe_bpp),
+			       lane, fdi_dotclock,
 			       link_bw,
 			       intel_dp_bw_fec_overhead(false),
 			       &pipe_config->fdi_m_n);
-- 
2.40.1

[Intel-gfx] [PATCH 04/11] drm/i915/audio: Consider fractional vdsc bpp while computing tu_data

[Ankit Nautiyal]

MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.

v2:
-Fix tu_data calculation while dealing with U6.4 format. (Stan)

v3:
-Use BPP_X16_FMT to print vdsc bpp.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
---
 drivers/gpu/drm/i915/display/intel_audio.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index aa93ccd6c2aa..8796d90c46a6 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -521,25 +521,25 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 	unsigned int link_clks_available, link_clks_required;
 	unsigned int tu_data, tu_line, link_clks_active;
 	unsigned int h_active, h_total, hblank_delta, pixel_clk;
-	unsigned int fec_coeff, cdclk, vdsc_bpp;
+	unsigned int fec_coeff, cdclk, vdsc_bppx16;
 	unsigned int link_clk, lanes;
 	unsigned int hblank_rise;
 
 	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
 	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
-	vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
+	vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
 	cdclk = i915->display.cdclk.hw.cdclk;
 	/* fec= 0.972261, using rounding multiplier of 1000000 */
 	fec_coeff = 972261;
 	link_clk = crtc_state->port_clock;
 	lanes = crtc_state->lane_count;
 
-	drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
-		    "lanes = %u vdsc_bpp = %u cdclk = %u\n",
-		    h_active, link_clk, lanes, vdsc_bpp, cdclk);
+	drm_dbg_kms(&i915->drm,
+		    "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " BPP_X16_FMT " cdclk = %u\n",
+		    h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16), cdclk);
 
-	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
+	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
 		return 0;
 
 	link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
@@ -551,8 +551,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
 		hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
 						  mul_u32_u32(link_clk, cdclk));
 
-	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
-			    mul_u32_u32(link_clk * lanes, fec_coeff));
+	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
+			    mul_u32_u32(link_clk * lanes * 16, fec_coeff));
 	tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
 			    mul_u32_u32(64 * pixel_clk, 1000000));
 	link_clks_active  = (tu_line - 1) * 64 + tu_data;
-- 
2.40.1

[Intel-gfx] [PATCH 05/11] drm/i915/dsc/mtl: Add support for fractional bpp

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Consider the fractional bpp while reading the qp values.

v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
---
 .../gpu/drm/i915/display/intel_qp_tables.c    |  3 ---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 25 +++++++++++++++----
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 543cdc46aa1d..600c815e37e4 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -34,9 +34,6 @@
  * These qp tables are as per the C model
  * and it has the rows pointing to bpps which increment
  * in steps of 0.5
- * We do not support fractional bpps as of today,
- * hence we would skip the fractional bpps during
- * our references for qp calclulations.
  */
 static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
 	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 3a1ed574edbb..5f2fb702e367 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -77,8 +77,8 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
 static void
 calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 {
+	int bpp = to_bpp_int(vdsc_cfg->bits_per_pixel);
 	int bpc = vdsc_cfg->bits_per_component;
-	int bpp = vdsc_cfg->bits_per_pixel >> 4;
 	int qp_bpc_modifier = (bpc - 8) * 2;
 	int uncompressed_bpg_rate;
 	int first_line_bpg_offset;
@@ -148,7 +148,13 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 		static const s8 ofs_und8[] = {
 			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
 		};
-
+		/*
+		 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,
+		 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are
+		 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
+		 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
+		 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
+		 */
 		bpp_i  = bpp - 8;
 		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 			u8 range_bpg_offset;
@@ -178,6 +184,9 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 				range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
 		}
 	} else {
+		/* fractional bpp part * 10000 (for precision up to 4 decimal places) */
+		int fractional_bits = to_bpp_frac(vdsc_cfg->bits_per_pixel);
+
 		static const s8 ofs_und6[] = {
 			0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
 		};
@@ -191,7 +200,14 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
 			10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
 		};
 
-		bpp_i  = (2 * (bpp - 6));
+		/*
+		 * QP table rows have values in increment of 0.5.
+		 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,
+		 * and so on.
+		 * 0.5 fractional part with 4 decimal precision becomes 5000
+		 */
+		bpp_i  = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1));
+
 		for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 			u8 range_bpg_offset;
 
@@ -279,8 +295,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 
-	/* Gen 11 only supports integral values of bpp */
-	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+	vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;
 
 	/*
 	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
-- 
2.40.1

[Intel-gfx] [PATCH 06/11] drm/i915/dp: Iterate over output bpp with fractional step size

[Ankit Nautiyal]

This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.

v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 41 +++++++++++++++----------
 1 file changed, 25 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 246f50d1f030..e53c87825194 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1737,15 +1737,15 @@ static bool intel_dp_dsc_supports_format(const struct intel_connector *connector
 	return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
 }
 
-static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
 					    u32 lane_count, u32 mode_clock,
 					    enum intel_output_format output_format,
 					    int timeslots)
 {
 	u32 available_bw, required_bw;
 
-	available_bw = (link_clock * lane_count * timeslots)  / 8;
-	required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+	available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
+	required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
 
 	return available_bw > required_bw;
 }
@@ -1753,7 +1753,7 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
 static int dsc_compute_link_config(struct intel_dp *intel_dp,
 				   struct intel_crtc_state *pipe_config,
 				   struct link_config_limits *limits,
-				   u16 compressed_bpp,
+				   u16 compressed_bppx16,
 				   int timeslots)
 {
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
@@ -1768,8 +1768,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
 		for (lane_count = limits->min_lane_count;
 		     lane_count <= limits->max_lane_count;
 		     lane_count <<= 1) {
-			if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
-							     adjusted_mode->clock,
+			if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
+							     lane_count, adjusted_mode->clock,
 							     pipe_config->output_format,
 							     timeslots))
 				continue;
@@ -1882,7 +1882,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
-					      valid_dsc_bpp[i],
+					      valid_dsc_bpp[i] << 4,
 					      timeslots);
 		if (ret == 0) {
 			pipe_config->dsc.compressed_bpp_x16 =
@@ -1902,6 +1902,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
  */
 static int
 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
+			      const struct intel_connector *connector,
 			      struct intel_crtc_state *pipe_config,
 			      struct link_config_limits *limits,
 			      int dsc_max_bpp,
@@ -1909,23 +1910,31 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 			      int pipe_bpp,
 			      int timeslots)
 {
-	u16 compressed_bpp;
+	u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	u16 compressed_bppx16;
+	u8 bppx16_step;
 	int ret;
 
+	if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
+		bppx16_step = 16;
+	else
+		bppx16_step = 16 / bppx16_incr;
+
 	/* Compressed BPP should be less than the Input DSC bpp */
-	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+	dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
+	dsc_min_bpp = dsc_min_bpp << 4;
 
-	for (compressed_bpp = dsc_max_bpp;
-	     compressed_bpp >= dsc_min_bpp;
-	     compressed_bpp--) {
+	for (compressed_bppx16 = dsc_max_bpp;
+	     compressed_bppx16 >= dsc_min_bpp;
+	     compressed_bppx16 -= bppx16_step) {
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
-					      compressed_bpp,
+					      compressed_bppx16,
 					      timeslots);
 		if (ret == 0) {
-			pipe_config->dsc.compressed_bpp_x16 =
-				to_bpp_x16(compressed_bpp);
+			pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
 			return 0;
 		}
 	}
@@ -1963,7 +1972,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
 	dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
 
 	if (DISPLAY_VER(i915) >= 13)
-		return xelpd_dsc_compute_link_config(intel_dp, pipe_config, limits,
+		return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,
 						     dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
 	return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
 					   dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
-- 
2.40.1

[Intel-gfx] [PATCH 07/11] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp

[Ankit Nautiyal]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.

v2:
Add drm_modeset_unlock to new line(Suraj)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
---
 .../drm/i915/display/intel_display_debugfs.c  | 84 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 85 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f3700c18d685..915420d0cef8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1256,6 +1256,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 								      DP_DSC_YCbCr420_Native)),
 			   str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd,
 								      DP_DSC_YCbCr444)));
+		seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+			   drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1448,6 +1450,85 @@ static const struct file_operations i915_dsc_output_format_fops = {
 	.write = i915_dsc_output_format_write
 };
 
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_dp *intel_dp;
+	struct intel_connector *intel_connector = to_intel_connector(connector);
+	struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	intel_dp = intel_attached_dp(intel_connector);
+	seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out:
+	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+					     const char __user *ubuf,
+					     size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	bool dsc_fractional_bpp_enable = false;
+	int ret;
+
+	if (len == 0)
+		return 0;
+
+	drm_dbg(&i915->drm,
+		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+	if (ret < 0)
+		return ret;
+
+	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+		(dsc_fractional_bpp_enable) ? "true" : "false");
+	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+					struct file *file)
+{
+	return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_fractional_bpp_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_fractional_bpp_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1525,6 +1606,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_output_format", 0644, root,
 				    connector, &i915_dsc_output_format_fops);
+
+		debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+				    connector, &i915_dsc_fractional_bpp_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 19e7e6e2e7a6..900515c30e73 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1811,6 +1811,7 @@ struct intel_dp {
 	/* Display stream compression testing */
 	bool force_dsc_en;
 	int force_dsc_output_format;
+	bool force_dsc_fractional_bpp_en;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
-- 
2.40.1

[Intel-gfx] [PATCH 08/11] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs

[Ankit Nautiyal]

From: Swati Sharma <swati2.sharma@intel.com>

If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.

v2:
-Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
-Fix comment (Suraj)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e53c87825194..607d03382db8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1928,6 +1928,9 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 	for (compressed_bppx16 = dsc_max_bpp;
 	     compressed_bppx16 >= dsc_min_bpp;
 	     compressed_bppx16 -= bppx16_step) {
+		if (intel_dp->force_dsc_fractional_bpp_en &&
+		    !to_bpp_frac(compressed_bppx16))
+			continue;
 		ret = dsc_compute_link_config(intel_dp,
 					      pipe_config,
 					      limits,
@@ -1935,6 +1938,10 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
 					      timeslots);
 		if (ret == 0) {
 			pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
+			if (intel_dp->force_dsc_fractional_bpp_en &&
+			    to_bpp_frac(compressed_bppx16))
+				drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
+
 			return 0;
 		}
 	}
-- 
2.40.1

[Intel-gfx] [PATCH 09/11] drm/i915/dp_mst: Use precision of 1/16 for computing bpp

[Ankit Nautiyal]

Modify the functions to deal with bpps with 1/16 precision.
This will make way for cases when DSC with fractional bpp is used.
For bpp without DSC, there is no change, as we still use whole numbers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 56 +++++++++++----------
 1 file changed, 30 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5c7e9d296483..e7806fe11b9d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -47,20 +47,21 @@
 #include "intel_vdsc.h"
 #include "skl_scaler.h"
 
-static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
+static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp_x16,
 					  const struct drm_display_mode *adjusted_mode,
 					  struct intel_crtc_state *crtc_state,
 					  bool dsc)
 {
 	if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) <= 13 && dsc) {
-		int output_bpp = bpp;
+		int output_bpp_x16 = bpp_x16;
 		/* DisplayPort 2 128b/132b, bits per lane is always 32 */
 		int symbol_clock = crtc_state->port_clock / 32;
 
-		if (output_bpp * adjusted_mode->crtc_clock >=
+		if (DIV_ROUND_UP(output_bpp_x16 * adjusted_mode->crtc_clock, 16) >=
 		    symbol_clock * 72) {
 			drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n",
-				    output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72);
+				    DIV_ROUND_UP(output_bpp_x16 * adjusted_mode->crtc_clock, 16),
+				    symbol_clock * 72);
 			return -EINVAL;
 		}
 	}
@@ -127,8 +128,8 @@ static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
 
 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 						struct intel_crtc_state *crtc_state,
-						int max_bpp,
-						int min_bpp,
+						int max_bpp_x16,
+						int min_bpp_x16,
 						struct link_config_limits *limits,
 						struct drm_connector_state *conn_state,
 						int step,
@@ -143,7 +144,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
-	int bpp, slots = -EINVAL;
+	int bpp_x16, slots = -EINVAL;
 	int ret = 0;
 
 	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
@@ -164,25 +165,25 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 						      crtc_state->port_clock,
 						      crtc_state->lane_count);
 
-	drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
-		    min_bpp, max_bpp);
+	drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp " BPP_X16_FMT " max bpp " BPP_X16_FMT "\n",
+		    BPP_X16_ARGS(min_bpp_x16), BPP_X16_ARGS(max_bpp_x16));
 
-	for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
+	for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= step) {
 		struct intel_link_m_n remote_m_n;
-		int link_bpp;
+		int link_bpp_x16;
 
-		drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
+		drm_dbg_kms(&i915->drm, "Trying bpp " BPP_X16_FMT "\n", BPP_X16_ARGS(bpp_x16));
 
-		ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
+		ret = intel_dp_mst_check_constraints(i915, bpp_x16, adjusted_mode, crtc_state, dsc);
 		if (ret)
 			continue;
 
-		link_bpp = dsc ? bpp :
-			intel_dp_output_bpp(crtc_state->output_format, bpp);
+		link_bpp_x16 = dsc ? bpp_x16 :
+			intel_dp_output_bpp(crtc_state->output_format, to_bpp_int(bpp_x16));
 
-		intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, to_bpp_x16(link_bpp),
+		intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp_x16,
 					 &crtc_state->dp_m_n);
-		intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, to_bpp_x16(link_bpp),
+		intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp_x16,
 					 &remote_m_n);
 
 		/*
@@ -225,10 +226,11 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 			    slots);
 	} else {
 		if (!dsc)
-			crtc_state->pipe_bpp = bpp;
+			crtc_state->pipe_bpp = to_bpp_int(bpp_x16);
 		else
-			crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
-		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
+			crtc_state->dsc.compressed_bpp_x16 = bpp_x16;
+		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp " BPP_X16_FMT " dsc %d\n",
+			    slots, BPP_X16_ARGS(bpp_x16), dsc);
 	}
 
 	return slots;
@@ -246,10 +248,10 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 	 * YUV420 is only half of the pipe bpp value.
 	 */
 	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
-						     to_bpp_int(limits->link.max_bpp_x16),
-						     to_bpp_int(limits->link.min_bpp_x16),
+						     limits->link.max_bpp_x16,
+						     limits->link.min_bpp_x16,
 						     limits,
-						     conn_state, 2 * 3, false);
+						     conn_state, 2 * 3 * 16, false);
 
 	if (slots < 0)
 		return slots;
@@ -325,9 +327,11 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 	min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
 							    crtc_state->pipe_bpp);
 
-	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,
-						     min_compressed_bpp, limits,
-						     conn_state, 1, true);
+	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
+						     to_bpp_x16(max_compressed_bpp),
+						     to_bpp_x16(min_compressed_bpp),
+						     limits,
+						     conn_state, 16, true);
 
 	if (slots < 0)
 		return slots;
-- 
2.40.1

[Intel-gfx] [PATCH 10/11] drm/i916/dp_mst: Iterate over the DSC bpps as per DSC precision support

[Ankit Nautiyal]

Currently we iterate over the bpp_x16 in step of 16.
Use DSC fractional bpp precision supported by the sink to compute
the appropriate steps to iterate over the bpps.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e7806fe11b9d..322046bb7d42 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -273,6 +273,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 	int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
 	u8 dsc_max_bpc;
 	int min_compressed_bpp, max_compressed_bpp;
+	int bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
+	int bppx16_step;
 
 	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
 	if (DISPLAY_VER(i915) >= 12)
@@ -327,11 +329,16 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 	min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
 							    crtc_state->pipe_bpp);
 
+	if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
+		bppx16_step = 16;
+	else
+		bppx16_step = 16 / bppx16_incr;
+
 	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
 						     to_bpp_x16(max_compressed_bpp),
 						     to_bpp_x16(min_compressed_bpp),
 						     limits,
-						     conn_state, 16, true);
+						     conn_state, bppx16_step, true);
 
 	if (slots < 0)
 		return slots;
-- 
2.40.1

[Intel-gfx] [PATCH 11/11] drm/i915/dp_mst: Add support for forcing dsc fractional bpp via debugfs

[Ankit Nautiyal]

If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 322046bb7d42..26b51ba6871d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -172,6 +172,10 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 		struct intel_link_m_n remote_m_n;
 		int link_bpp_x16;
 
+		if (dsc && intel_dp->force_dsc_fractional_bpp_en &&
+		    !to_bpp_frac(bpp_x16))
+			continue;
+
 		drm_dbg_kms(&i915->drm, "Trying bpp " BPP_X16_FMT "\n", BPP_X16_ARGS(bpp_x16));
 
 		ret = intel_dp_mst_check_constraints(i915, bpp_x16, adjusted_mode, crtc_state, dsc);
@@ -225,12 +229,16 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 		drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
 			    slots);
 	} else {
-		if (!dsc)
-			crtc_state->pipe_bpp = to_bpp_int(bpp_x16);
-		else
+		if (dsc) {
 			crtc_state->dsc.compressed_bpp_x16 = bpp_x16;
+			if (intel_dp->force_dsc_fractional_bpp_en && to_bpp_frac(bpp_x16))
+				drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
+		} else {
+			crtc_state->pipe_bpp = to_bpp_int(bpp_x16);
+		}
 		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp " BPP_X16_FMT " dsc %d\n",
 			    slots, BPP_X16_ARGS(bpp_x16), dsc);
+
 	}
 
 	return slots;
-- 
2.40.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev10)

[Patchwork]

== Series Details ==

Series: Add DSC fractional bpp support (rev10)
URL   : https://patchwork.freedesktop.org/series/111391/
State : warning

== Summary ==

Error: dim checkpatch failed
83db4cff7777 drm/display/dp: Add helper function to get DSC bpp precision
f72f3f2aa067 drm/i915/display: Store compressed bpp in U6.4 format
-:190: WARNING:MISSING_SPACE: break quoted strings at a space character
#190: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2216:
+			    "Cannot compute valid DSC parameters for Input Bpp = %d"
+			    "Compressed BPP = " BPP_X16_FMT "\n",

-:222: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#222: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2407:
+						   to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),

total: 0 errors, 2 warnings, 0 checks, 188 lines checked
01fb8003d41c drm/i915/display: Consider fractional vdsc bpp while computing m_n values
57ed990aae02 drm/i915/audio: Consider fractional vdsc bpp while computing tu_data
2740e517bfd7 drm/i915/dsc/mtl: Add support for fractional bpp
63e6de65f109 drm/i915/dp: Iterate over output bpp with fractional step size
8dfd5cbd96cf drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
c5cf2099ecf2 drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
0cb1cafe567e drm/i915/dp_mst: Use precision of 1/16 for computing bpp
-:68: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#68: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:169:
+	drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp " BPP_X16_FMT " max bpp " BPP_X16_FMT "\n",

total: 0 errors, 1 warnings, 0 checks, 119 lines checked
513f074fefef drm/i916/dp_mst: Iterate over the DSC bpps as per DSC precision support
da4e0d8b6686 drm/i915/dp_mst: Add support for forcing dsc fractional bpp via debugfs

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DSC fractional bpp support (rev10)

[Patchwork]

== Series Details ==

Series: Add DSC fractional bpp support (rev10)
URL   : https://patchwork.freedesktop.org/series/111391/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Add DSC fractional bpp support (rev10)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8431 bytes --]

== Series Details ==

Series: Add DSC fractional bpp support (rev10)
URL   : https://patchwork.freedesktop.org/series/111391/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13863 -> Patchwork_111391v10
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/index.html

Participating hosts (33 -> 34)
------------------------------

  Additional (2): fi-kbl-soraka fi-hsw-4770 
  Missing    (1): bat-atsm-1 

Known issues
------------

  Here are the changes found in Patchwork_111391v10 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - bat-adlp-11:        [PASS][1] -> [DMESG-WARN][2] ([i915#7507]) +28 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/bat-adlp-11/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-adlp-11/igt@debugfs_test@read_all_entries.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-adlp-11:        NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-adlp-11/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_pm_rpm@module-reload:
    - bat-adlp-11:        NOTRUN -> [DMESG-WARN][6] ([i915#7507]) +3 other tests dmesg-warn
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-adlp-11/igt@i915_pm_rpm@module-reload.html

  * igt@i915_pm_rps@basic-api:
    - bat-adlp-11:        NOTRUN -> [SKIP][7] ([i915#6621])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-adlp-11/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][8] ([i915#1886])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@mman:
    - fi-hsw-4770:        NOTRUN -> [INCOMPLETE][9] ([i915#9527])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/fi-hsw-4770/igt@i915_selftest@live@mman.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - fi-hsw-4770:        NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#5190])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_dsc@dsc-basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][11] ([fdo#109271]) +9 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/fi-kbl-soraka/igt@kms_dsc@dsc-basic.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-adlp-11:        [PASS][12] -> [DMESG-FAIL][13] ([i915#7507]) +22 other tests dmesg-fail
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/bat-adlp-11/igt@kms_frontbuffer_tracking@basic.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-adlp-11/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
    - fi-hsw-4770:        NOTRUN -> [SKIP][14] ([fdo#109271]) +12 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         NOTRUN -> [SKIP][15] ([i915#1845] / [i915#9197]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-5:
    - bat-adlp-11:        NOTRUN -> [DMESG-FAIL][16] ([i915#7507]) +4 other tests dmesg-fail
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-adlp-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-5.html

  * igt@kms_psr@primary_page_flip:
    - bat-adlp-11:        NOTRUN -> [SKIP][17] ([i915#1072]) +3 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-adlp-11/igt@kms_psr@primary_page_flip.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-jsl-3:          [PASS][18] -> [SKIP][19] ([i915#9648]) +3 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/bat-jsl-3/igt@kms_psr@sprite_plane_onoff.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-jsl-3/igt@kms_psr@sprite_plane_onoff.html
    - fi-hsw-4770:        NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#1072]) +3 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-adlp-11:        NOTRUN -> [SKIP][21] ([i915#3555])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-adlp-11/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
    - bat-adlp-11:        NOTRUN -> [SKIP][22] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/bat-adlp-11/igt@prime_vgem@basic-fence-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#7507]: https://gitlab.freedesktop.org/drm/intel/issues/7507
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#9197]: https://gitlab.freedesktop.org/drm/intel/issues/9197
  [i915#9527]: https://gitlab.freedesktop.org/drm/intel/issues/9527
  [i915#9648]: https://gitlab.freedesktop.org/drm/intel/issues/9648


Build changes
-------------

  * Linux: CI_DRM_13863 -> Patchwork_111391v10

  CI-20190529: 20190529
  CI_DRM_13863: ba137561f6c6c0e18d87d8ae9ec71f327d6f5168 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7582: 453b9df12fbc9fff561bdb4eb97992983e74c3d4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111391v10: ba137561f6c6c0e18d87d8ae9ec71f327d6f5168 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

4571f78e0829 drm/i915/dp_mst: Add support for forcing dsc fractional bpp via debugfs
8c27ee0f67e2 drm/i916/dp_mst: Iterate over the DSC bpps as per DSC precision support
747bf799b061 drm/i915/dp_mst: Use precision of 1/16 for computing bpp
178ce0b254cc drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
92a5d26ddaef drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
5257e8160960 drm/i915/dp: Iterate over output bpp with fractional step size
abe31e3de7fe drm/i915/dsc/mtl: Add support for fractional bpp
438305b1027f drm/i915/audio: Consider fractional vdsc bpp while computing tu_data
fa25c9aa7568 drm/i915/display: Consider fractional vdsc bpp while computing m_n values
72a1ff216dc5 drm/i915/display: Store compressed bpp in U6.4 format
0551d123ae74 drm/display/dp: Add helper function to get DSC bpp precision

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/index.html

[-- Attachment #2: Type: text/html, Size: 10170 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for Add DSC fractional bpp support (rev10)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 96792 bytes --]

== Series Details ==

Series: Add DSC fractional bpp support (rev10)
URL   : https://patchwork.freedesktop.org/series/111391/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13863_full -> Patchwork_111391v10_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/index.html

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_111391v10_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@kms_pm_rpm@fences}:
    - shard-rkl:          [SKIP][1] ([i915#1849]) -> [SKIP][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_pm_rpm@fences.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_pm_rpm@fences.html

  
Known issues
------------

  Here are the changes found in Patchwork_111391v10_full that come from known issues:

### CI changes ###

#### Possible fixes ####

  * boot:
    - shard-apl:          ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [FAIL][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) ([i915#8293]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl6/boot.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl6/boot.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl6/boot.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl7/boot.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl7/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl7/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl7/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl7/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl7/boot.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl1/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl1/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl1/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl1/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl1/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl2/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl2/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl2/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl2/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl2/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl3/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl3/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl6/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl6/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl6/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl6/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl7/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl7/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl7/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl7/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl7/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl1/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl6/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl6/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl6/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl6/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl6/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl3/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl3/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl3/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/boot.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/boot.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/boot.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/boot.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl1/boot.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/boot.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl1/boot.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl1/boot.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl1/boot.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/boot.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl1/boot.html
    - shard-glk:          ([PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [FAIL][74], [PASS][75], [PASS][76], [PASS][77]) ([i915#8293]) -> ([PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk9/boot.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk9/boot.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk9/boot.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk8/boot.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk8/boot.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk8/boot.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk2/boot.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk2/boot.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk3/boot.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk3/boot.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk3/boot.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk2/boot.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk3/boot.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk4/boot.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk4/boot.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk4/boot.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk2/boot.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk4/boot.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk5/boot.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk5/boot.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk5/boot.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk6/boot.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk6/boot.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk6/boot.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk8/boot.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk9/boot.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk9/boot.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk9/boot.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk9/boot.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk8/boot.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk8/boot.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk8/boot.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk8/boot.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk6/boot.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk6/boot.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk5/boot.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk5/boot.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk5/boot.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk5/boot.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk4/boot.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk4/boot.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk4/boot.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk3/boot.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk3/boot.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk3/boot.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk3/boot.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk2/boot.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk2/boot.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk2/boot.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk2/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-keep-cache:
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#8411]) +1 other test skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@api_intel_bb@blit-reloc-keep-cache.html

  * igt@api_intel_bb@object-reloc-keep-cache:
    - shard-rkl:          [PASS][104] -> [SKIP][105] ([i915#8411])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@api_intel_bb@object-reloc-keep-cache.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-4/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-rkl:          NOTRUN -> [SKIP][106] ([i915#7701])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@device_reset@unbind-cold-reset-rebind.html
    - shard-dg2:          NOTRUN -> [SKIP][107] ([i915#7701])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@device_reset@unbind-reset-rebind:
    - shard-rkl:          [PASS][108] -> [FAIL][109] ([i915#4778])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@device_reset@unbind-reset-rebind.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@device_reset@unbind-reset-rebind.html

  * igt@drm_fdinfo@most-busy-check-all@bcs0:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#8414]) +20 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@drm_fdinfo@most-busy-check-all@bcs0.html

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
    - shard-rkl:          [PASS][111] -> [FAIL][112] ([i915#7742])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html

  * igt@drm_fdinfo@virtual-busy-hang-all:
    - shard-mtlp:         NOTRUN -> [SKIP][113] ([i915#8414])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@drm_fdinfo@virtual-busy-hang-all.html

  * igt@fbdev@unaligned-read:
    - shard-rkl:          [PASS][114] -> [SKIP][115] ([i915#2582]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@fbdev@unaligned-read.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@fbdev@unaligned-read.html

  * igt@gem_busy@semaphore:
    - shard-dg2:          NOTRUN -> [SKIP][116] ([i915#3936])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_busy@semaphore.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-rkl:          NOTRUN -> [SKIP][117] ([i915#4098] / [i915#9323])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_ccs@suspend-resume:
    - shard-mtlp:         NOTRUN -> [SKIP][118] ([i915#9323])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@gem_ccs@suspend-resume.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-mtlp:         [PASS][119] -> [ABORT][120] ([i915#9414]) +2 other tests abort
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-mtlp-2/igt@gem_ctx_isolation@preservation-s3@rcs0.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-5/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_ctx_persistence@hang:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([i915#8555])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@gem_ctx_persistence@hang.html

  * igt@gem_eio@hibernate:
    - shard-tglu:         [PASS][122] -> [ABORT][123] ([i915#7975] / [i915#8213] / [i915#8398])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-tglu-7/igt@gem_eio@hibernate.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-tglu-10/igt@gem_eio@hibernate.html

  * igt@gem_exec_balancer@sliced:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#4812])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-11/igt@gem_exec_balancer@sliced.html

  * igt@gem_exec_capture@many-4k-incremental:
    - shard-apl:          NOTRUN -> [FAIL][125] ([i915#9606])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl7/igt@gem_exec_capture@many-4k-incremental.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-apl:          NOTRUN -> [FAIL][126] ([i915#2846])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-rkl:          NOTRUN -> [FAIL][127] ([i915#2842])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][128] ([i915#2842])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk8/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-sync:
    - shard-dg2:          NOTRUN -> [SKIP][129] ([i915#3539]) +2 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_exec_fair@basic-sync.html

  * igt@gem_exec_flush@basic-wb-rw-before-default:
    - shard-dg2:          NOTRUN -> [SKIP][130] ([i915#3539] / [i915#4852]) +2 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@gem_exec_flush@basic-wb-rw-before-default.html

  * igt@gem_exec_reloc@basic-concurrent16:
    - shard-rkl:          NOTRUN -> [SKIP][131] ([i915#3281])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@gem_exec_reloc@basic-concurrent16.html

  * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
    - shard-dg2:          NOTRUN -> [SKIP][132] ([i915#3281]) +12 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html

  * igt@gem_exec_reloc@basic-gtt-read:
    - shard-rkl:          [PASS][133] -> [SKIP][134] ([i915#3281]) +4 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-read.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@gem_exec_reloc@basic-gtt-read.html
    - shard-mtlp:         NOTRUN -> [SKIP][135] ([i915#3281]) +1 other test skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@gem_exec_reloc@basic-gtt-read.html

  * igt@gem_exec_schedule@preempt-queue:
    - shard-dg2:          NOTRUN -> [SKIP][136] ([i915#4537] / [i915#4812])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_exec_schedule@preempt-queue.html

  * igt@gem_exec_suspend@basic-s0@lmem0:
    - shard-dg1:          [PASS][137] -> [DMESG-WARN][138] ([i915#4423])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-dg1-16/igt@gem_exec_suspend@basic-s0@lmem0.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg1-13/igt@gem_exec_suspend@basic-s0@lmem0.html

  * igt@gem_fenced_exec_thrash@no-spare-fences:
    - shard-dg2:          NOTRUN -> [SKIP][139] ([i915#4860])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_fenced_exec_thrash@no-spare-fences.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-apl:          NOTRUN -> [SKIP][140] ([fdo#109271] / [i915#4613]) +1 other test skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          [PASS][141] -> [TIMEOUT][142] ([i915#5493])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-dg2-6/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-11/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_media_vme:
    - shard-dg2:          NOTRUN -> [SKIP][143] ([i915#284])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_media_vme.html

  * igt@gem_mmap_gtt@flink-race:
    - shard-mtlp:         NOTRUN -> [SKIP][144] ([i915#4077]) +1 other test skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-8/igt@gem_mmap_gtt@flink-race.html

  * igt@gem_mmap_gtt@medium-copy-xy:
    - shard-dg2:          NOTRUN -> [SKIP][145] ([i915#4077]) +8 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_mmap_gtt@medium-copy-xy.html

  * igt@gem_mmap_wc@close:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#4083]) +4 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_mmap_wc@close.html

  * igt@gem_mmap_wc@write-gtt-read-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][147] ([i915#4083])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@gem_mmap_wc@write-gtt-read-wc.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-dg2:          NOTRUN -> [SKIP][148] ([i915#3282]) +4 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_pread@exhaustion:
    - shard-rkl:          NOTRUN -> [SKIP][149] ([i915#3282])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite_snooped:
    - shard-rkl:          [PASS][150] -> [SKIP][151] ([i915#3282])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@gem_pwrite_snooped.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@gem_pwrite_snooped.html

  * igt@gem_pxp@create-regular-context-1:
    - shard-mtlp:         NOTRUN -> [SKIP][152] ([i915#4270]) +1 other test skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-8/igt@gem_pxp@create-regular-context-1.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-dg2:          NOTRUN -> [SKIP][153] ([i915#4270]) +3 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - shard-rkl:          NOTRUN -> [SKIP][154] ([i915#4270])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@gem_pxp@reject-modify-context-protection-off-1.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
    - shard-glk:          NOTRUN -> [SKIP][155] ([fdo#109271]) +43 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk8/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][156] ([i915#768]) +1 other test skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html

  * igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][157] ([i915#8428])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][158] ([i915#4885])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_tiled_pread_pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#4079]) +4 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_tiled_pread_pwrite.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-mtlp:         NOTRUN -> [SKIP][160] ([i915#3297])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][161] ([i915#3297]) +2 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy:
    - shard-dg2:          NOTRUN -> [SKIP][162] ([i915#3297] / [i915#4880]) +1 other test skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html

  * igt@gen9_exec_parse@batch-zero-length:
    - shard-rkl:          NOTRUN -> [SKIP][163] ([i915#2527])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@gen9_exec_parse@batch-zero-length.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-dg2:          NOTRUN -> [SKIP][164] ([i915#2856]) +4 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@gen9_exec_parse@bb-start-far.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-rkl:          [PASS][165] -> [SKIP][166] ([i915#2527]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@gen9_exec_parse@bb-start-param.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-4/igt@gen9_exec_parse@bb-start-param.html

  * igt@gen9_exec_parse@cmd-crossing-page:
    - shard-mtlp:         NOTRUN -> [SKIP][167] ([i915#2856])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@gen9_exec_parse@cmd-crossing-page.html

  * igt@i915_pm_rc6_residency@rc6-idle@bcs0:
    - shard-dg1:          [PASS][168] -> [FAIL][169] ([i915#3591])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html

  * igt@i915_pm_rps@thresholds-idle-park@gt0:
    - shard-dg2:          NOTRUN -> [SKIP][170] ([i915#8925])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@i915_pm_rps@thresholds-idle-park@gt0.html

  * igt@i915_pm_sseu@full-enable:
    - shard-dg2:          NOTRUN -> [SKIP][171] ([i915#4387])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@i915_pm_sseu@full-enable.html

  * igt@i915_query@query-topology-coherent-slice-mask:
    - shard-dg2:          NOTRUN -> [SKIP][172] ([i915#6188])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@i915_query@query-topology-coherent-slice-mask.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-rkl:          [PASS][173] -> [SKIP][174] ([fdo#109315]) +9 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@i915_suspend@fence-restore-untiled.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][175] ([i915#4212])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-8/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_addfb_basic@basic-x-tiled-legacy:
    - shard-dg2:          NOTRUN -> [SKIP][176] ([i915#4212]) +1 other test skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_addfb_basic@basic-x-tiled-legacy.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([i915#4212] / [i915#5608])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [FAIL][178] ([i915#8247]) +3 other tests fail
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html

  * igt@kms_async_flips@crc@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [FAIL][179] ([i915#8247]) +3 other tests fail
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg1-15/igt@kms_async_flips@crc@pipe-d-hdmi-a-4.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg2:          NOTRUN -> [SKIP][180] ([i915#9531])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-transition-fencing:
    - shard-rkl:          NOTRUN -> [SKIP][181] ([i915#1845] / [i915#4098]) +15 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_atomic_transition@plane-all-transition-fencing.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-rkl:          NOTRUN -> [SKIP][182] ([i915#5286])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-mtlp:         [PASS][183] -> [FAIL][184] ([i915#5138])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][185] ([fdo#111614]) +3 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_big_fb@linear-32bpp-rotate-270.html
    - shard-rkl:          NOTRUN -> [SKIP][186] ([fdo#111614] / [i915#3638])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
    - shard-rkl:          [PASS][187] -> [SKIP][188] ([i915#1845] / [i915#4098]) +23 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-mtlp:         NOTRUN -> [SKIP][189] ([fdo#111614])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2:          NOTRUN -> [SKIP][190] ([i915#5190]) +13 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][191] ([fdo#111615]) +2 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-dg2:          NOTRUN -> [SKIP][192] ([i915#4538] / [i915#5190]) +7 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-rkl:          NOTRUN -> [SKIP][193] ([fdo#110723]) +1 other test skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_joiner@basic:
    - shard-dg2:          NOTRUN -> [SKIP][194] ([i915#2705])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_big_joiner@basic.html
    - shard-rkl:          NOTRUN -> [SKIP][195] ([i915#2705])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_big_joiner@basic.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][196] ([i915#4087] / [i915#7213]) +3 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-mtlp:         NOTRUN -> [SKIP][197] ([fdo#111827])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-dg2:          NOTRUN -> [SKIP][198] ([fdo#111827]) +2 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-rkl:          NOTRUN -> [SKIP][199] ([i915#7828]) +2 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - shard-dg2:          NOTRUN -> [SKIP][200] ([i915#7828]) +13 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_chamelium_frames@hdmi-crc-fast.html

  * igt@kms_color@ctm-green-to-red@pipe-b:
    - shard-rkl:          [PASS][201] -> [SKIP][202] ([i915#4098]) +5 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_color@ctm-green-to-red@pipe-b.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_color@ctm-green-to-red@pipe-b.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][203] ([i915#7118]) +2 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_content_protection@atomic-dpms.html
    - shard-rkl:          NOTRUN -> [SKIP][204] ([i915#7118])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@atomic@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][205] ([i915#7173])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-11/igt@kms_content_protection@atomic@pipe-a-dp-4.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][206] ([i915#3299])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-dg2:          NOTRUN -> [SKIP][207] ([i915#3359]) +2 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_cursor_crc@cursor-onscreen-512x512.html
    - shard-rkl:          NOTRUN -> [SKIP][208] ([i915#3359])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][209] ([fdo#109274] / [i915#5354]) +3 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][210] ([i915#3546])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][211] ([fdo#109274] / [fdo#111767] / [i915#5354])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#4103] / [i915#4213])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-dg2:          NOTRUN -> [SKIP][213] ([i915#8588])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][214] ([i915#3804])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          NOTRUN -> [SKIP][215] ([i915#3555]) +5 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_draw_crc@draw-method-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][216] ([i915#8812])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_draw_crc@draw-method-mmap-wc.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-dg2:          NOTRUN -> [SKIP][217] ([i915#3555] / [i915#3840])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_fence_pin_leak:
    - shard-dg2:          NOTRUN -> [SKIP][218] ([i915#4881])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_fence_pin_leak.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-rkl:          NOTRUN -> [SKIP][219] ([fdo#111825]) +3 other tests skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-snb:          NOTRUN -> [SKIP][220] ([fdo#109271]) +12 other tests skip
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-snb2/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-apl:          NOTRUN -> [SKIP][221] ([fdo#109271] / [fdo#111767])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][222] ([i915#8381])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-snb:          NOTRUN -> [SKIP][223] ([fdo#109271] / [fdo#111767])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-snb2/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-dg2:          NOTRUN -> [SKIP][224] ([fdo#109274]) +6 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_flip@2x-wf_vblank-ts-check.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][225] ([i915#3637] / [i915#4098]) +8 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][226] ([i915#2672])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][227] ([i915#2672]) +4 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
    - shard-rkl:          NOTRUN -> [SKIP][228] ([i915#2672])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][229] ([i915#3555]) +6 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][230] ([i915#2672] / [i915#3555])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_tiling@flip-change-tiling:
    - shard-rkl:          NOTRUN -> [SKIP][231] ([i915#3555] / [i915#4098]) +1 other test skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_flip_tiling@flip-change-tiling.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-dg2:          NOTRUN -> [SKIP][232] ([fdo#109285])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - shard-dg2:          NOTRUN -> [SKIP][233] ([i915#5274])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
    - shard-dg2:          [PASS][234] -> [FAIL][235] ([i915#6880])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          [PASS][236] -> [SKIP][237] ([i915#1849] / [i915#4098]) +13 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
    - shard-rkl:          NOTRUN -> [SKIP][238] ([fdo#111825] / [i915#1825]) +10 other tests skip
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][239] ([i915#8708])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-apl:          NOTRUN -> [SKIP][240] ([fdo#109271]) +80 other tests skip
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][241] ([i915#3023]) +5 other tests skip
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][242] ([i915#5354]) +41 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][243] ([i915#5460])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-1p-rte:
    - shard-dg2:          NOTRUN -> [SKIP][244] ([i915#3458]) +18 other tests skip
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-rte.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-pwrite:
    - shard-mtlp:         NOTRUN -> [SKIP][245] ([i915#1825]) +4 other tests skip
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][246] ([i915#8708]) +17 other tests skip
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][247] ([i915#3555] / [i915#8228])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-2/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-swap:
    - shard-mtlp:         NOTRUN -> [SKIP][248] ([i915#3555] / [i915#8228])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-8/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][249] ([i915#3555] / [i915#8228]) +2 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_hdr@static-toggle.html

  * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
    - shard-dg2:          NOTRUN -> [SKIP][250] ([fdo#109289]) +3 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html

  * igt@kms_plane@plane-panning-bottom-right:
    - shard-rkl:          NOTRUN -> [SKIP][251] ([i915#4098] / [i915#8825])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_plane@plane-panning-bottom-right.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][252] ([i915#5176] / [i915#9423]) +3 other tests skip
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg1-18/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
    - shard-rkl:          NOTRUN -> [SKIP][253] ([i915#6953] / [i915#8152])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][254] ([i915#5235]) +7 other tests skip
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75:
    - shard-rkl:          NOTRUN -> [SKIP][255] ([i915#3555] / [i915#4098] / [i915#6953] / [i915#8152])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
    - shard-rkl:          NOTRUN -> [SKIP][256] ([i915#4098] / [i915#6953] / [i915#8152]) +1 other test skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][257] ([i915#5235]) +11 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg1-13/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
    - shard-apl:          NOTRUN -> [SKIP][258] ([fdo#109271] / [i915#658]) +2 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-dg2:          NOTRUN -> [SKIP][259] ([i915#658]) +1 other test skip
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-mtlp:         NOTRUN -> [SKIP][260] ([i915#4348])
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@cursor_mmap_cpu:
    - shard-rkl:          NOTRUN -> [SKIP][261] ([i915#1072]) +1 other test skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_psr@cursor_mmap_cpu.html

  * igt@kms_psr@psr2_dpms:
    - shard-dg2:          NOTRUN -> [SKIP][262] ([i915#1072]) +8 other tests skip
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_psr@psr2_dpms.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-rkl:          NOTRUN -> [SKIP][263] ([i915#5461] / [i915#658])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
    - shard-dg2:          NOTRUN -> [SKIP][264] ([i915#5461] / [i915#658])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@exhaust-fences:
    - shard-dg2:          NOTRUN -> [SKIP][265] ([i915#4235])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_rotation_crc@exhaust-fences.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg2:          NOTRUN -> [SKIP][266] ([i915#4235] / [i915#5190])
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-dg2:          NOTRUN -> [SKIP][267] ([i915#3555] / [i915#4098]) +3 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg2:          NOTRUN -> [FAIL][268] ([IGT#2])
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@kms_sysfs_edid_timing.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][269] -> [FAIL][270] ([i915#9196])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][271] ([i915#4098]) +15 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-dg2:          NOTRUN -> [SKIP][272] ([i915#2436])
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf@invalid-oa-metric-set-id:
    - shard-rkl:          [PASS][273] -> [SKIP][274] ([i915#5608])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@perf@invalid-oa-metric-set-id.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@perf@invalid-oa-metric-set-id.html

  * igt@perf@non-zero-reason@0-rcs0:
    - shard-dg2:          [PASS][275] -> [FAIL][276] ([i915#7484])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-dg2-6/igt@perf@non-zero-reason@0-rcs0.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html

  * igt@perf_pmu@busy-hang@rcs0:
    - shard-mtlp:         [PASS][277] -> [FAIL][278] ([i915#4349])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-mtlp-5/igt@perf_pmu@busy-hang@rcs0.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-7/igt@perf_pmu@busy-hang@rcs0.html

  * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
    - shard-dg2:          NOTRUN -> [CRASH][279] ([i915#9351])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html

  * igt@prime_vgem@coherency-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][280] ([i915#3708] / [i915#4077])
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@prime_vgem@coherency-gtt.html

  * igt@prime_vgem@fence-write-hang:
    - shard-dg2:          NOTRUN -> [SKIP][281] ([i915#3708])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-1/igt@prime_vgem@fence-write-hang.html
    - shard-rkl:          NOTRUN -> [SKIP][282] ([fdo#109295] / [i915#3708])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@prime_vgem@fence-write-hang.html

  * igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-submitted-signaled:
    - shard-glk:          NOTRUN -> [FAIL][283] ([i915#9583])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk8/igt@syncobj_timeline@invalid-multi-wait-all-available-unsubmitted-submitted-signaled.html

  * igt@syncobj_timeline@single-wait-available-signaled:
    - shard-rkl:          [PASS][284] -> [SKIP][285] ([i915#2575])
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@syncobj_timeline@single-wait-available-signaled.html
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@syncobj_timeline@single-wait-available-signaled.html

  * igt@v3d/v3d_submit_cl@valid-multisync-submission:
    - shard-dg2:          NOTRUN -> [SKIP][286] ([i915#2575]) +15 other tests skip
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@v3d/v3d_submit_cl@valid-multisync-submission.html

  * igt@v3d/v3d_submit_cl@valid-submission:
    - shard-mtlp:         NOTRUN -> [SKIP][287] ([i915#2575]) +1 other test skip
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@v3d/v3d_submit_cl@valid-submission.html

  * igt@v3d/v3d_submit_csd@bad-multisync-out-sync:
    - shard-rkl:          NOTRUN -> [SKIP][288] ([fdo#109315]) +4 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@v3d/v3d_submit_csd@bad-multisync-out-sync.html

  * igt@vc4/vc4_create_bo@create-bo-zeroed:
    - shard-mtlp:         NOTRUN -> [SKIP][289] ([i915#7711])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@vc4/vc4_create_bo@create-bo-zeroed.html

  * igt@vc4/vc4_perfmon@get-values-valid-perfmon:
    - shard-rkl:          NOTRUN -> [SKIP][290] ([i915#7711]) +1 other test skip
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@vc4/vc4_perfmon@get-values-valid-perfmon.html

  * igt@vc4/vc4_wait_bo@unused-bo-1ns:
    - shard-dg2:          NOTRUN -> [SKIP][291] ([i915#7711]) +7 other tests skip
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-6/igt@vc4/vc4_wait_bo@unused-bo-1ns.html

  
#### Possible fixes ####

  * igt@fbdev@info:
    - shard-rkl:          [SKIP][292] ([i915#1849] / [i915#2582]) -> [PASS][293]
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@fbdev@info.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-4/igt@fbdev@info.html

  * igt@gem_busy@close-race:
    - shard-mtlp:         [INCOMPLETE][294] -> [PASS][295]
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-mtlp-4/igt@gem_busy@close-race.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@gem_busy@close-race.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          [INCOMPLETE][296] ([i915#7297]) -> [PASS][297]
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-dg2-1/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-11/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
    - shard-rkl:          [SKIP][298] ([i915#6252]) -> [PASS][299]
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@gem_ctx_persistence@legacy-engines-hang@blt.html

  * igt@gem_eio@hibernate:
    - shard-mtlp:         [ABORT][300] ([i915#7975] / [i915#8213] / [i915#9414]) -> [PASS][301]
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-mtlp-2/igt@gem_eio@hibernate.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-8/igt@gem_eio@hibernate.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][302] ([i915#2842]) -> [PASS][303]
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-rkl:          [FAIL][304] ([i915#2842]) -> [PASS][305] +2 other tests pass
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@gem_exec_fair@basic-pace@vecs0.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-rkl:          [SKIP][306] ([fdo#109313]) -> [PASS][307]
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-rkl:          [SKIP][308] ([i915#3282]) -> [PASS][309]
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@gem_partial_pwrite_pread@reads.html
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_userptr_blits@relocations:
    - shard-rkl:          [SKIP][310] ([i915#3281]) -> [PASS][311] +6 other tests pass
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-1/igt@gem_userptr_blits@relocations.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@gem_userptr_blits@relocations.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-rkl:          [SKIP][312] ([i915#2527]) -> [PASS][313] +3 other tests pass
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-1/igt@gen9_exec_parse@allowed-all.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - shard-dg1:          [FAIL][314] ([i915#3591]) -> [PASS][315] +1 other test pass
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-rkl:          [WARN][316] ([i915#2681]) -> [PASS][317]
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-tglu:         [FAIL][318] ([i915#3743]) -> [PASS][319] +3 other tests pass
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-tglu-8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-tglu-4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_color@legacy-gamma-reset@pipe-b:
    - shard-rkl:          [SKIP][320] ([i915#4098]) -> [PASS][321] +3 other tests pass
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_color@legacy-gamma-reset@pipe-b.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_color@legacy-gamma-reset@pipe-b.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
    - shard-rkl:          [SKIP][322] ([i915#1845] / [i915#4098]) -> [PASS][323] +8 other tests pass
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [FAIL][324] ([i915#2346]) -> [PASS][325]
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-rkl:          [SKIP][326] ([i915#1849] / [i915#4098]) -> [PASS][327] +4 other tests pass
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_fbcon_fbt@fbc.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-dg2:          [FAIL][328] ([i915#6880]) -> [PASS][329]
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * {igt@kms_pm_dc@dc6-dpms}:
    - shard-tglu:         [FAIL][330] ([i915#9295]) -> [PASS][331]
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-tglu-8/igt@kms_pm_dc@dc6-dpms.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-tglu-9/igt@kms_pm_dc@dc6-dpms.html

  * {igt@kms_pm_rpm@fences-dpms}:
    - shard-rkl:          [SKIP][332] ([i915#1849]) -> [PASS][333]
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_pm_rpm@fences-dpms.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_pm_rpm@fences-dpms.html

  * {igt@kms_pm_rpm@modeset-lpsp-stress}:
    - shard-rkl:          [SKIP][334] ([i915#9519]) -> [PASS][335]
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1:
    - shard-mtlp:         [FAIL][336] ([i915#9196]) -> [PASS][337]
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-mtlp-5/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-2/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
    - shard-tglu:         [FAIL][338] ([i915#9196]) -> [PASS][339]
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html

  * {igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-dp-1}:
    - shard-apl:          [INCOMPLETE][340] ([i915#180] / [i915#9159]) -> [PASS][341]
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-apl6/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-dp-1.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-apl2/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-dp-1.html

  * igt@perf_pmu@busy-double-start@bcs0:
    - shard-mtlp:         [FAIL][342] ([i915#4349]) -> [PASS][343] +1 other test pass
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-mtlp-5/igt@perf_pmu@busy-double-start@bcs0.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-2/igt@perf_pmu@busy-double-start@bcs0.html

  * igt@prime_vgem@basic-fence-read:
    - shard-rkl:          [SKIP][344] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][345] +2 other tests pass
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-1/igt@prime_vgem@basic-fence-read.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@prime_vgem@basic-fence-read.html

  
#### Warnings ####

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-rkl:          [SKIP][346] ([i915#3555]) -> [SKIP][347] ([i915#7957])
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@gem_ccs@block-multicopy-inplace.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_ccs@suspend-resume:
    - shard-rkl:          [SKIP][348] ([i915#7957]) -> [SKIP][349] ([i915#9323])
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@gem_ccs@suspend-resume.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@gem_ccs@suspend-resume.html

  * igt@gem_eio@kms:
    - shard-dg1:          [FAIL][350] ([i915#5784]) -> [DMESG-FAIL][351] ([i915#4423])
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-dg1-16/igt@gem_eio@kms.html
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg1-13/igt@gem_eio@kms.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-rkl:          [FAIL][352] ([i915#2842]) -> [SKIP][353] ([i915#9591])
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@gem_exec_fair@basic-pace@bcs0.html
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-rkl:          [SKIP][354] ([i915#3282]) -> [WARN][355] ([i915#2658])
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@gem_pwrite@basic-exhaustion.html
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@gem_pwrite@basic-exhaustion.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-snb:          [INCOMPLETE][356] -> [INCOMPLETE][357] ([i915#4528])
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-snb2/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_suspend@forcewake:
    - shard-mtlp:         [ABORT][358] ([i915#9414]) -> [ABORT][359] ([fdo#103375] / [i915#9414])
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-mtlp-8/igt@i915_suspend@forcewake.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-5/igt@i915_suspend@forcewake.html

  * igt@kms_async_flips@crc@pipe-b-edp-1:
    - shard-mtlp:         [FAIL][360] ([i915#8247]) -> [DMESG-FAIL][361] ([i915#8561])
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-mtlp-2/igt@kms_async_flips@crc@pipe-b-edp-1.html
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-mtlp-4/igt@kms_async_flips@crc@pipe-b-edp-1.html

  * igt@kms_atomic_interruptible@atomic-setmode:
    - shard-rkl:          [SKIP][362] ([i915#1845] / [i915#4098]) -> [SKIP][363] ([i915#2575]) +4 other tests skip
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_atomic_interruptible@atomic-setmode.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_atomic_interruptible@atomic-setmode.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-rkl:          [SKIP][364] ([i915#1769] / [i915#3555]) -> [SKIP][365] ([i915#1845] / [i915#4098])
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-rkl:          [SKIP][366] ([i915#1845] / [i915#4098]) -> [SKIP][367] ([i915#5286]) +1 other test skip
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-rkl:          [SKIP][368] ([i915#5286]) -> [SKIP][369] ([i915#1845] / [i915#4098]) +5 other tests skip
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-rkl:          [SKIP][370] ([i915#1845] / [i915#4098]) -> [SKIP][371] ([fdo#111614] / [i915#3638]) +1 other test skip
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_big_fb@linear-8bpp-rotate-90.html
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-rkl:          [SKIP][372] ([fdo#111614] / [i915#3638]) -> [SKIP][373] ([i915#1845] / [i915#4098])
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
    - shard-rkl:          [SKIP][374] ([fdo#110723]) -> [SKIP][375] ([i915#1845] / [i915#4098]) +4 other tests skip
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
    - shard-rkl:          [SKIP][376] ([i915#1845] / [i915#4098]) -> [SKIP][377] ([fdo#110723]) +1 other test skip
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-rkl:          [SKIP][378] ([i915#1845] / [i915#4098]) -> [SKIP][379] ([fdo#109315]) +4 other tests skip
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_chamelium_color@gamma:
    - shard-rkl:          [SKIP][380] ([fdo#111827]) -> [SKIP][381] ([i915#2575]) +1 other test skip
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_chamelium_color@gamma.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_frames@hdmi-crc-multiple:
    - shard-rkl:          [SKIP][382] ([i915#7828]) -> [SKIP][383] ([i915#2575])
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_chamelium_frames@hdmi-crc-multiple.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_chamelium_frames@hdmi-crc-multiple.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          [SKIP][384] ([i915#1845] / [i915#4098]) -> [SKIP][385] ([i915#7118])
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_content_protection@atomic.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@type1:
    - shard-rkl:          [SKIP][386] ([i915#7118]) -> [SKIP][387] ([i915#1845] / [i915#4098])
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-1/igt@kms_content_protection@type1.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-rkl:          [SKIP][388] ([i915#1845] / [i915#4098]) -> [SKIP][389] ([i915#3359])
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_cursor_crc@cursor-offscreen-512x512.html
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-4/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-rkl:          [SKIP][390] ([fdo#109279] / [i915#3359]) -> [SKIP][391] ([i915#1845] / [i915#4098])
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_cursor_crc@cursor-onscreen-512x170.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-rkl:          [SKIP][392] ([i915#3359]) -> [SKIP][393] ([i915#1845] / [i915#4098])
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_cursor_crc@cursor-random-512x170.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-rkl:          [SKIP][394] ([i915#1845] / [i915#4098]) -> [SKIP][395] ([i915#3555])
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_cursor_crc@cursor-random-max-size.html
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-7/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          [SKIP][396] ([i915#3555]) -> [SKIP][397] ([i915#1845] / [i915#4098]) +3 other tests skip
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-max-size:
    - shard-dg1:          [SKIP][398] ([i915#3555]) -> [SKIP][399] ([i915#3555] / [i915#4423])
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-dg1-16/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-dg1-13/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html

  * igt@kms_cursor_edge_walk@128x128-top-edge:
    - shard-rkl:          [SKIP][400] ([i915#4098]) -> [SKIP][401] ([i915#2575]) +1 other test skip
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_cursor_edge_walk@128x128-top-edge.html
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_cursor_edge_walk@128x128-top-edge.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-rkl:          [SKIP][402] ([fdo#111767] / [fdo#111825]) -> [SKIP][403] ([i915#1845] / [i915#4098])
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-rkl:          [SKIP][404] ([i915#4103]) -> [SKIP][405] ([i915#1845] / [i915#4098]) +1 other test skip
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-rkl:          [SKIP][406] ([i915#1845] / [i915#4098]) -> [SKIP][407] ([i915#4103])
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-rkl:          [SKIP][408] ([fdo#111825]) -> [SKIP][409] ([i915#1845] / [i915#4098]) +2 other tests skip
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-rkl:          [SKIP][410] ([i915#1845] / [i915#4098]) -> [SKIP][411] ([fdo#111767] / [fdo#111825])
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          [SKIP][412] ([fdo#110189] / [i915#3955]) -> [SKIP][413] ([i915#3955])
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@flip-vs-fences:
    - shard-rkl:          [SKIP][414] ([i915#3637] / [i915#4098]) -> [SKIP][415] ([i915#2575])
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_flip@flip-vs-fences.html
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling:
    - shard-rkl:          [SKIP][416] ([i915#3555]) -> [SKIP][417] ([fdo#109315])
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling.html
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
    - shard-rkl:          [SKIP][418] ([fdo#111825] / [i915#1825]) -> [SKIP][419] ([i915#1849] / [i915#4098]) +33 other tests skip
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][420] ([i915#1849] / [i915#4098]) -> [SKIP][421] ([fdo#111825] / [i915#1825]) +12 other tests skip
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][422] ([i915#1849] / [i915#4098]) -> [SKIP][423] ([fdo#109315]) +8 other tests skip
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt:
    - shard-rkl:          [SKIP][424] ([i915#1849] / [i915#4098]) -> [SKIP][425] ([i915#3023]) +11 other tests skip
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt.html
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-rkl:          [SKIP][426] ([i915#3023]) -> [SKIP][427] ([i915#1849] / [i915#4098]) +17 other tests skip
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-suspend.html
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_invalid_mode@zero-hdisplay:
    - shard-rkl:          [SKIP][428] ([i915#3555]) -> [SKIP][429] ([i915#2575])
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_invalid_mode@zero-hdisplay.html
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_invalid_mode@zero-hdisplay.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          [SKIP][430] ([i915#6301]) -> [SKIP][431] ([i915#1845] / [i915#4098])
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_panel_fitting@legacy.html
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_panel_fitting@legacy.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-rkl:          [SKIP][432] ([fdo#111068] / [i915#658]) -> [SKIP][433] ([fdo#109315])
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_psr2_sf@cursor-plane-update-sf.html
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr@sprite_blt:
    - shard-rkl:          [SKIP][434] ([i915#1072]) -> [SKIP][435] ([fdo#109315])
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-5/igt@kms_psr@sprite_blt.html
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_psr@sprite_blt.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-rkl:          [SKIP][436] ([i915#5289]) -> [SKIP][437] ([i915#1845] / [i915#4098])
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-4/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-rkl:          [SKIP][438] ([fdo#111615] / [i915#5289]) -> [SKIP][439] ([i915#1845] / [i915#4098])
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13863/shard-rkl-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/shard-rkl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4778]: https://gitlab.freedesktop.org/drm/intel/issues/4778
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6188]: https://gitlab.freedesktop.org/drm/intel/issues/6188
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
  [i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
  [i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
  [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
  [i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
  [i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
  [i915#8825]: https://gitlab.freedesktop.org/drm/intel/issues/8825
  [i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
  [i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
  [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
  [i915#9292]: https://gitlab.freedesktop.org/drm/intel/issues/9292
  [i915#9295]: https://gitlab.freedesktop.org/drm/intel/issues/9295
  [i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/intel/issues/9340
  [i915#9351]: https://gitlab.freedesktop.org/drm/intel/issues/9351
  [i915#9412]: https://gitlab.freedesktop.org/drm/intel/issues/9412
  [i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414
  [i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
  [i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
  [i915#9531]: https://gitlab.freedesktop.org/drm/intel/issues/9531
  [i915#9581]: https://gitlab.freedesktop.org/drm/intel/issues/9581
  [i915#9583]: https://gitlab.freedesktop.org/drm/intel/issues/9583
  [i915#9591]: https://gitlab.freedesktop.org/drm/intel/issues/9591
  [i915#9606]: https://gitlab.freedesktop.org/drm/intel/issues/9606


Build changes
-------------

  * Linux: CI_DRM_13863 -> Patchwork_111391v10

  CI-20190529: 20190529
  CI_DRM_13863: ba137561f6c6c0e18d87d8ae9ec71f327d6f5168 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7582: 453b9df12fbc9fff561bdb4eb97992983e74c3d4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111391v10: ba137561f6c6c0e18d87d8ae9ec71f327d6f5168 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v10/index.html

[-- Attachment #2: Type: text/html, Size: 119679 bytes --]

Re: [Intel-gfx] [PATCH 09/11] drm/i915/dp_mst: Use precision of 1/16 for computing bpp

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Friday, November 10, 2023 3:40 PM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sharma, Swati2 <swati2.sharma@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>;
> suijingfeng@loongson.cn
> Subject: [PATCH 09/11] drm/i915/dp_mst: Use precision of 1/16 for computing
> bpp
> 
> Modify the functions to deal with bpps with 1/16 precision.
> This will make way for cases when DSC with fractional bpp is used.
> For bpp without DSC, there is no change, as we still use whole numbers.
> 

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 56 +++++++++++----------
>  1 file changed, 30 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 5c7e9d296483..e7806fe11b9d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -47,20 +47,21 @@
>  #include "intel_vdsc.h"
>  #include "skl_scaler.h"
> 
> -static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int
> bpp,
> +static int intel_dp_mst_check_constraints(struct drm_i915_private
> +*i915, int bpp_x16,
>  					  const struct drm_display_mode
> *adjusted_mode,
>  					  struct intel_crtc_state *crtc_state,
>  					  bool dsc)
>  {
>  	if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) <= 13 && dsc) {
> -		int output_bpp = bpp;
> +		int output_bpp_x16 = bpp_x16;
>  		/* DisplayPort 2 128b/132b, bits per lane is always 32 */
>  		int symbol_clock = crtc_state->port_clock / 32;
> 
> -		if (output_bpp * adjusted_mode->crtc_clock >=
> +		if (DIV_ROUND_UP(output_bpp_x16 * adjusted_mode-
> >crtc_clock, 16) >=
>  		    symbol_clock * 72) {
>  			drm_dbg_kms(&i915->drm, "UHBR check
> failed(required bw %d available %d)\n",
> -				    output_bpp * adjusted_mode->crtc_clock,
> symbol_clock * 72);
> +				    DIV_ROUND_UP(output_bpp_x16 *
> adjusted_mode->crtc_clock, 16),
> +				    symbol_clock * 72);
>  			return -EINVAL;
>  		}
>  	}
> @@ -127,8 +128,8 @@ static void intel_dp_mst_compute_m_n(const struct
> intel_crtc_state *crtc_state,
> 
>  static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder
> *encoder,
>  						struct intel_crtc_state
> *crtc_state,
> -						int max_bpp,
> -						int min_bpp,
> +						int max_bpp_x16,
> +						int min_bpp_x16,
>  						struct link_config_limits
> *limits,
>  						struct drm_connector_state
> *conn_state,
>  						int step,
> @@ -143,7 +144,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
> intel_encoder *encoder,
>  	struct drm_i915_private *i915 = to_i915(connector->base.dev);
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> -	int bpp, slots = -EINVAL;
> +	int bpp_x16, slots = -EINVAL;
>  	int ret = 0;
> 
>  	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp-
> >mst_mgr); @@ -164,25 +165,25 @@ static int
> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
>  						      crtc_state->port_clock,
>  						      crtc_state->lane_count);
> 
> -	drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d
> max bpp %d\n",
> -		    min_bpp, max_bpp);
> +	drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp "
> BPP_X16_FMT " max bpp " BPP_X16_FMT "\n",
> +		    BPP_X16_ARGS(min_bpp_x16),
> BPP_X16_ARGS(max_bpp_x16));
> 
> -	for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
> +	for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -=
> step) {
>  		struct intel_link_m_n remote_m_n;
> -		int link_bpp;
> +		int link_bpp_x16;
> 
> -		drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
> +		drm_dbg_kms(&i915->drm, "Trying bpp " BPP_X16_FMT "\n",
> +BPP_X16_ARGS(bpp_x16));
> 
> -		ret = intel_dp_mst_check_constraints(i915, bpp,
> adjusted_mode, crtc_state, dsc);
> +		ret = intel_dp_mst_check_constraints(i915, bpp_x16,
> adjusted_mode,
> +crtc_state, dsc);
>  		if (ret)
>  			continue;
> 
> -		link_bpp = dsc ? bpp :
> -			intel_dp_output_bpp(crtc_state->output_format,
> bpp);
> +		link_bpp_x16 = dsc ? bpp_x16 :
> +			intel_dp_output_bpp(crtc_state->output_format,
> to_bpp_int(bpp_x16));
> 
> -		intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc,
> to_bpp_x16(link_bpp),
> +		intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc,
> +link_bpp_x16,
>  					 &crtc_state->dp_m_n);
> -		intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc,
> to_bpp_x16(link_bpp),
> +		intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc,
> +link_bpp_x16,
>  					 &remote_m_n);
> 
>  		/*
> @@ -225,10 +226,11 @@ static int
> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
>  			    slots);
>  	} else {
>  		if (!dsc)
> -			crtc_state->pipe_bpp = bpp;
> +			crtc_state->pipe_bpp = to_bpp_int(bpp_x16);
>  		else
> -			crtc_state->dsc.compressed_bpp_x16 =
> to_bpp_x16(bpp);
> -		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc
> %d\n", slots, bpp, dsc);
> +			crtc_state->dsc.compressed_bpp_x16 = bpp_x16;
> +		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp "
> BPP_X16_FMT " dsc %d\n",
> +			    slots, BPP_X16_ARGS(bpp_x16), dsc);
>  	}
> 
>  	return slots;
> @@ -246,10 +248,10 @@ static int intel_dp_mst_compute_link_config(struct
> intel_encoder *encoder,
>  	 * YUV420 is only half of the pipe bpp value.
>  	 */
>  	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> -						     to_bpp_int(limits-
> >link.max_bpp_x16),
> -						     to_bpp_int(limits-
> >link.min_bpp_x16),
> +						     limits->link.max_bpp_x16,
> +						     limits->link.min_bpp_x16,
>  						     limits,
> -						     conn_state, 2 * 3, false);
> +						     conn_state, 2 * 3 * 16,
> false);
> 
>  	if (slots < 0)
>  		return slots;
> @@ -325,9 +327,11 @@ static int
> intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
>  	min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
> min_compressed_bpp,
>  							    crtc_state-
> >pipe_bpp);
> 
> -	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> max_compressed_bpp,
> -						     min_compressed_bpp,
> limits,
> -						     conn_state, 1, true);
> +	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> +
> to_bpp_x16(max_compressed_bpp),
> +
> to_bpp_x16(min_compressed_bpp),
> +						     limits,
> +						     conn_state, 16, true);
> 
>  	if (slots < 0)
>  		return slots;
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 10/11] drm/i916/dp_mst: Iterate over the DSC bpps as per DSC precision support

[Kandpal, Suraj]

> Subject: [PATCH 10/11] drm/i916/dp_mst: Iterate over the DSC bpps as per
> DSC precision support
> 
> Currently we iterate over the bpp_x16 in step of 16.
> Use DSC fractional bpp precision supported by the sink to compute the
> appropriate steps to iterate over the bpps.
> 

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index e7806fe11b9d..322046bb7d42 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -273,6 +273,8 @@ static int
> intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
>  	int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
>  	u8 dsc_max_bpc;
>  	int min_compressed_bpp, max_compressed_bpp;
> +	int bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector-
> >dp.dsc_dpcd);
> +	int bppx16_step;
> 
>  	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
>  	if (DISPLAY_VER(i915) >= 12)
> @@ -327,11 +329,16 @@ static int
> intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
>  	min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
> min_compressed_bpp,
>  							    crtc_state-
> >pipe_bpp);
> 
> +	if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
> +		bppx16_step = 16;
> +	else
> +		bppx16_step = 16 / bppx16_incr;
> +
>  	slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> 
> to_bpp_x16(max_compressed_bpp),
> 
> to_bpp_x16(min_compressed_bpp),
>  						     limits,
> -						     conn_state, 16, true);
> +						     conn_state, bppx16_step,
> true);
> 
>  	if (slots < 0)
>  		return slots;
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 11/11] drm/i915/dp_mst: Add support for forcing dsc fractional bpp via debugfs

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Friday, November 10, 2023 3:40 PM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sharma, Swati2 <swati2.sharma@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>;
> suijingfeng@loongson.cn
> Subject: [PATCH 11/11] drm/i915/dp_mst: Add support for forcing dsc
> fractional bpp via debugfs
> 
> If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
> compressed bpp is fractional. Continue if the computed compressed bpp
> turns out to be a integer.
> 

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 322046bb7d42..26b51ba6871d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -172,6 +172,10 @@ static int
> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
>  		struct intel_link_m_n remote_m_n;
>  		int link_bpp_x16;
> 
> +		if (dsc && intel_dp->force_dsc_fractional_bpp_en &&
> +		    !to_bpp_frac(bpp_x16))
> +			continue;
> +
>  		drm_dbg_kms(&i915->drm, "Trying bpp " BPP_X16_FMT "\n",
> BPP_X16_ARGS(bpp_x16));
> 
>  		ret = intel_dp_mst_check_constraints(i915, bpp_x16,
> adjusted_mode, crtc_state, dsc); @@ -225,12 +229,16 @@ static int
> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
>  		drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
>  			    slots);
>  	} else {
> -		if (!dsc)
> -			crtc_state->pipe_bpp = to_bpp_int(bpp_x16);
> -		else
> +		if (dsc) {
>  			crtc_state->dsc.compressed_bpp_x16 = bpp_x16;
> +			if (intel_dp->force_dsc_fractional_bpp_en &&
> to_bpp_frac(bpp_x16))
> +				drm_dbg_kms(&i915->drm, "Forcing DSC
> fractional bpp\n");
> +		} else {
> +			crtc_state->pipe_bpp = to_bpp_int(bpp_x16);
> +		}
>  		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp "
> BPP_X16_FMT " dsc %d\n",
>  			    slots, BPP_X16_ARGS(bpp_x16), dsc);
> +
>  	}
> 
>  	return slots;
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 02/11] drm/i915/display: Store compressed bpp in U6.4 format

[Kandpal, Suraj]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Friday, November 10, 2023 3:40 PM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sharma, Swati2 <swati2.sharma@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>;
> suijingfeng@loongson.cn
> Subject: [PATCH 02/11] drm/i915/display: Store compressed bpp in U6.4
> format
> 
> DSC parameter bits_per_pixel is stored in U6.4 format.
> The 4 bits represent the fractional part of the bpp.
> Currently we use compressed_bpp member of dsc structure to store only the
> integral part of the bits_per_pixel.
> To store the full bits_per_pixel along with the fractional part,
> compressed_bpp is changed to store bpp in U6.4 formats. Intergral part is
> retrieved by simply right shifting the member compressed_bpp by 4.
> 
> v2:
> -Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing  with
> compressed bpp. (Suraj) -Fix comment styling. (Suraj)
> 
> v3:
> -Add separate file for 6.4 fixed point helper(Jani, Nikula) -Add comment for
> magic values(Suraj)
> 
> v4:
> -Fix checkpatch warnings caused by renaming(Suraj)
> 
> v5:
> -Rebase.
> -Use existing helpers for conversion of bpp_int to bpp_x16  and vice versa.
> 

LGTM.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c        | 10 +++----
>  drivers/gpu/drm/i915/display/intel_audio.c    |  2 +-
>  drivers/gpu/drm/i915/display/intel_bios.c     |  4 +--
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |  5 ++--
>  drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
>  .../drm/i915/display/intel_display_types.h    |  3 ++-
>  drivers/gpu/drm/i915/display/intel_dp.c       | 27 ++++++++++---------
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |  2 +-
>  drivers/gpu/drm/i915/display/intel_link_bw.c  |  2 +-
>  drivers/gpu/drm/i915/display/intel_vdsc.c     |  4 +--
>  10 files changed, 33 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c4585e445198..481fcb650850 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
>  	int bpp;
> 
>  	if (crtc_state->dsc.compression_enable)
> -		bpp = crtc_state->dsc.compressed_bpp;
> +		bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
>  	else
>  		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> 
> @@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct
> intel_encoder *encoder,
>  	 * compressed and non-compressed bpp.
>  	 */
>  	if (crtc_state->dsc.compression_enable) {
> -		mul = crtc_state->dsc.compressed_bpp;
> +		mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
>  		div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>  	}
> 
> @@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct
> intel_encoder *encoder,
>  		int bpp, line_time_us, byte_clk_period_ns;
> 
>  		if (crtc_state->dsc.compression_enable)
> -			bpp = crtc_state->dsc.compressed_bpp;
> +			bpp = to_bpp_int(crtc_state-
> >dsc.compressed_bpp_x16);
>  		else
>  			bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> 
> @@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct
> intel_encoder *encoder,
>  	struct drm_display_mode *adjusted_mode =
>  					&pipe_config->hw.adjusted_mode;
> 
> -	if (pipe_config->dsc.compressed_bpp) {
> -		int div = pipe_config->dsc.compressed_bpp;
> +	if (pipe_config->dsc.compressed_bpp_x16) {
> +		int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
>  		int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> 
>  		adjusted_mode->crtc_htotal =
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 19605264a35c..aa93ccd6c2aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
>  	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
>  	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> -	vdsc_bpp = crtc_state->dsc.compressed_bpp;
> +	vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
>  	cdclk = i915->display.cdclk.hw.cdclk;
>  	/* fec= 0.972261, using rounding multiplier of 1000000 */
>  	fec_coeff = 972261;
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 719fb550342b..2fd72b2fd109 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -3414,8 +3414,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
> 
>  	crtc_state->pipe_bpp = bpc * 3;
> 
> -	crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
> -					     VBT_DSC_MAX_BPP(dsc-
> >max_bpp));
> +	crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state-
> >pipe_bpp,
> +
> VBT_DSC_MAX_BPP(dsc->max_bpp)));
> 
>  	/*
>  	 * FIXME: This is ugly, and slice count should take DSC engine diff --git
> a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c4839c67cb0f..b93d1ad7936d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2598,8 +2598,9 @@ static int intel_vdsc_min_cdclk(const struct
> intel_crtc_state *crtc_state)
>  		 * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner
> Interface bits
>  		 */
>  		int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 :
> 24;
> -		int min_cdclk_bj = (crtc_state->dsc.compressed_bpp *
> pixel_clock) /
> -				   (2 * bigjoiner_interface_bits);
> +		int min_cdclk_bj =
> +			(to_bpp_int_roundup(crtc_state-
> >dsc.compressed_bpp_x16) *
> +			 pixel_clock) / (2 * bigjoiner_interface_bits);
> 
>  		min_cdclk = max(min_cdclk, min_cdclk_bj);
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 3effafcbb411..b4a8e3087e50 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5434,7 +5434,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> 
>  	PIPE_CONF_CHECK_I(dsc.compression_enable);
>  	PIPE_CONF_CHECK_I(dsc.dsc_split);
> -	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
> +	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
> 
>  	PIPE_CONF_CHECK_BOOL(splitter.enable);
>  	PIPE_CONF_CHECK_I(splitter.link_count);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 926bf9c1a3ed..19e7e6e2e7a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1362,7 +1362,8 @@ struct intel_crtc_state {
>  	struct {
>  		bool compression_enable;
>  		bool dsc_split;
> -		u16 compressed_bpp;
> +		/* Compressed Bpp in U6.4 format (first 4 bits for fractional
> part) */
> +		u16 compressed_bpp_x16;
>  		u8 slice_count;
>  		struct drm_dsc_config config;
>  	} dsc;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 37d7c9c2d695..4ad3718c3c7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1885,7 +1885,8 @@ icl_dsc_compute_link_config(struct intel_dp
> *intel_dp,
>  					      valid_dsc_bpp[i],
>  					      timeslots);
>  		if (ret == 0) {
> -			pipe_config->dsc.compressed_bpp =
> valid_dsc_bpp[i];
> +			pipe_config->dsc.compressed_bpp_x16 =
> +				to_bpp_x16(valid_dsc_bpp[i]);
>  			return 0;
>  		}
>  	}
> @@ -1923,7 +1924,8 @@ xelpd_dsc_compute_link_config(struct intel_dp
> *intel_dp,
>  					      compressed_bpp,
>  					      timeslots);
>  		if (ret == 0) {
> -			pipe_config->dsc.compressed_bpp =
> compressed_bpp;
> +			pipe_config->dsc.compressed_bpp_x16 =
> +				to_bpp_x16(compressed_bpp);
>  			return 0;
>  		}
>  	}
> @@ -2120,7 +2122,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct
> intel_dp *intel_dp,
>  	/* Compressed BPP should be less than the Input DSC bpp */
>  	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
> 
> -	pipe_config->dsc.compressed_bpp = max(dsc_min_bpp,
> dsc_max_bpp);
> +	pipe_config->dsc.compressed_bpp_x16 =
> +		to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
> 
>  	pipe_config->pipe_bpp = pipe_bpp;
> 
> @@ -2209,18 +2212,18 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
>  	ret = intel_dp_dsc_compute_params(connector, pipe_config);
>  	if (ret < 0) {
>  		drm_dbg_kms(&dev_priv->drm,
> -			    "Cannot compute valid DSC parameters for Input
> Bpp = %d "
> -			    "Compressed BPP = %d\n",
> +			    "Cannot compute valid DSC parameters for Input
> Bpp = %d"
> +			    "Compressed BPP = " BPP_X16_FMT "\n",
>  			    pipe_config->pipe_bpp,
> -			    pipe_config->dsc.compressed_bpp);
> +			    BPP_X16_ARGS(pipe_config-
> >dsc.compressed_bpp_x16));
>  		return ret;
>  	}
> 
>  	pipe_config->dsc.compression_enable = true;
>  	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp =
> %d "
> -		    "Compressed Bpp = %d Slice Count = %d\n",
> +		    "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
>  		    pipe_config->pipe_bpp,
> -		    pipe_config->dsc.compressed_bpp,
> +		    BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
>  		    pipe_config->dsc.slice_count);
> 
>  	return 0;
> @@ -2393,15 +2396,15 @@ intel_dp_compute_link_config(struct
> intel_encoder *encoder,
> 
>  	if (pipe_config->dsc.compression_enable) {
>  		drm_dbg_kms(&i915->drm,
> -			    "DP lane count %d clock %d Input bpp %d
> Compressed bpp %d\n",
> +			    "DP lane count %d clock %d Input bpp %d
> Compressed bpp "
> +BPP_X16_FMT "\n",
>  			    pipe_config->lane_count, pipe_config->port_clock,
>  			    pipe_config->pipe_bpp,
> -			    pipe_config->dsc.compressed_bpp);
> +			    BPP_X16_ARGS(pipe_config-
> >dsc.compressed_bpp_x16));
> 
>  		drm_dbg_kms(&i915->drm,
>  			    "DP link rate required %i available %i\n",
>  			    intel_dp_link_required(adjusted_mode->crtc_clock,
> -						   pipe_config-
> >dsc.compressed_bpp),
> +
> to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),
>  			    intel_dp_max_data_rate(pipe_config->port_clock,
>  						   pipe_config->lane_count));
>  	} else {
> @@ -2838,7 +2841,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>  		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
> 
>  	if (pipe_config->dsc.compression_enable)
> -		link_bpp = pipe_config->dsc.compressed_bpp;
> +		link_bpp = to_bpp_int(pipe_config-
> >dsc.compressed_bpp_x16);
>  	else
>  		link_bpp = intel_dp_output_bpp(pipe_config-
> >output_format,
>  					       pipe_config->pipe_bpp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 107f7418ddc5..31461ea25f7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -227,7 +227,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
> intel_encoder *encoder,
>  		if (!dsc)
>  			crtc_state->pipe_bpp = bpp;
>  		else
> -			crtc_state->dsc.compressed_bpp = bpp;
> +			crtc_state->dsc.compressed_bpp_x16 =
> to_bpp_x16(bpp);
>  		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d
> dsc %d\n", slots, bpp, dsc);
>  	}
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c
> b/drivers/gpu/drm/i915/display/intel_link_bw.c
> index 390db5c0c24a..02a0af2aa5ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_link_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_link_bw.c
> @@ -70,7 +70,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state
> *state,
>  			return PTR_ERR(crtc_state);
> 
>  		if (crtc_state->dsc.compression_enable)
> -			link_bpp = crtc_state->dsc.compressed_bpp;
> +			link_bpp = crtc_state->dsc.compressed_bpp_x16;
>  		else
>  			/*
>  			 * TODO: for YUV420 the actual link bpp is only half
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 6757dbae9ee5..3a1ed574edbb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> -	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> +	u16 compressed_bpp = to_bpp_int(pipe_config-
> >dsc.compressed_bpp_x16);
>  	int err;
>  	int ret;
> 
> @@ -874,7 +874,7 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
>  	if (vdsc_cfg->native_420)
>  		vdsc_cfg->bits_per_pixel >>= 1;
> 
> -	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> +	crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
> 
>  	/* PPS 2 */
>  	pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 03/11] drm/i915/display: Consider fractional vdsc bpp while computing m_n values

[Kandpal, Suraj]

> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate this precision while computing m_n values.
> 
> v1:
> Replace the computation of 'data_clock' with 'data_clock =
> DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng).
> 
> v2:
> Rebase and pass bits_per_pixel in U6.4 format.
> 

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  4 ++--
>  drivers/gpu/drm/i915/display/intel_dp.c      | 16 ++++++++--------
>  drivers/gpu/drm/i915/display/intel_dp_mst.c  | 14 +++++++-------
>  drivers/gpu/drm/i915/display/intel_fdi.c     |  3 ++-
>  4 files changed, 19 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b4a8e3087e50..125903007a29 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2415,12 +2415,12 @@ add_bw_alloc_overhead(int link_clock, int
> bw_overhead,  }
> 
>  void
> -intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
> +intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
>  		       int pixel_clock, int link_clock,
>  		       int bw_overhead,
>  		       struct intel_link_m_n *m_n)
>  {
> -	u32 data_clock = bits_per_pixel * pixel_clock;
> +	u32 data_clock = DIV_ROUND_UP(bits_per_pixel_x16 * pixel_clock,
> 16);
>  	u32 data_m;
>  	u32 data_n;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4ad3718c3c7d..246f50d1f030 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2663,7 +2663,7 @@ static bool can_enable_drrs(struct intel_connector
> *connector,  static void  intel_dp_drrs_compute_config(struct intel_connector
> *connector,
>  			     struct intel_crtc_state *pipe_config,
> -			     int link_bpp)
> +			     int link_bpp_x16)
>  {
>  	struct drm_i915_private *i915 = to_i915(connector->base.dev);
>  	const struct drm_display_mode *downclock_mode = @@ -2688,7
> +2688,7 @@ intel_dp_drrs_compute_config(struct intel_connector
> *connector,
>  	if (pipe_config->splitter.enable)
>  		pixel_clock /= pipe_config->splitter.link_count;
> 
> -	intel_link_compute_m_n(link_bpp, pipe_config->lane_count,
> pixel_clock,
> +	intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count,
> +pixel_clock,
>  			       pipe_config->port_clock,
>  			       intel_dp_bw_fec_overhead(pipe_config-
> >fec_enable),
>  			       &pipe_config->dp_m2_n2);
> @@ -2792,7 +2792,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	const struct drm_display_mode *fixed_mode;
>  	struct intel_connector *connector = intel_dp->attached_connector;
> -	int ret = 0, link_bpp;
> +	int ret = 0, link_bpp_x16;
> 
>  	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder-
> >port != PORT_A)
>  		pipe_config->has_pch_encoder = true;
> @@ -2841,10 +2841,10 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
>  		drm_dp_enhanced_frame_cap(intel_dp->dpcd);
> 
>  	if (pipe_config->dsc.compression_enable)
> -		link_bpp = to_bpp_int(pipe_config-
> >dsc.compressed_bpp_x16);
> +		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
>  	else
> -		link_bpp = intel_dp_output_bpp(pipe_config-
> >output_format,
> -					       pipe_config->pipe_bpp);
> +		link_bpp_x16 =
> to_bpp_x16(intel_dp_output_bpp(pipe_config->output_format,
> +							      pipe_config-
> >pipe_bpp));
> 
>  	if (intel_dp->mso_link_count) {
>  		int n = intel_dp->mso_link_count;
> @@ -2868,7 +2868,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> 
>  	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
> 
> -	intel_link_compute_m_n(link_bpp,
> +	intel_link_compute_m_n(link_bpp_x16,
>  			       pipe_config->lane_count,
>  			       adjusted_mode->crtc_clock,
>  			       pipe_config->port_clock,
> @@ -2884,7 +2884,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> 
>  	intel_vrr_compute_config(pipe_config, conn_state);
>  	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> -	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
> +	intel_dp_drrs_compute_config(connector, pipe_config,
> link_bpp_x16);
>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
>  	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp,
> pipe_config, conn_state);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 31461ea25f7c..5c7e9d296483 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -70,7 +70,7 @@ static int intel_dp_mst_check_constraints(struct
> drm_i915_private *i915, int bpp
> 
>  static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
>  				    const struct intel_connector *connector,
> -				    bool ssc, bool dsc, int bpp)
> +				    bool ssc, bool dsc, int bpp_x16)
>  {
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> @@ -94,7 +94,7 @@ static int intel_dp_mst_bw_overhead(const struct
> intel_crtc_state *crtc_state,
>  	overhead = drm_dp_bw_overhead(crtc_state->lane_count,
>  				      adjusted_mode->hdisplay,
>  				      dsc_slice_count,
> -				      to_bpp_x16(bpp),
> +				      bpp_x16,
>  				      flags);
> 
>  	/*
> @@ -107,16 +107,16 @@ static int intel_dp_mst_bw_overhead(const struct
> intel_crtc_state *crtc_state,  static void intel_dp_mst_compute_m_n(const
> struct intel_crtc_state *crtc_state,
>  				     const struct intel_connector *connector,
>  				     bool ssc, bool dsc,
> -				     int bpp,
> +				     int bpp_x16,
>  				     struct intel_link_m_n *m_n)
>  {
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
>  	int overhead = intel_dp_mst_bw_overhead(crtc_state,
>  						connector,
> -						ssc, dsc, bpp);
> +						ssc, dsc, bpp_x16);
> 
> -	intel_link_compute_m_n(bpp, crtc_state->lane_count,
> +	intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,
>  			       adjusted_mode->crtc_clock,
>  			       crtc_state->port_clock,
>  			       overhead,
> @@ -180,9 +180,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
> intel_encoder *encoder,
>  		link_bpp = dsc ? bpp :
>  			intel_dp_output_bpp(crtc_state->output_format,
> bpp);
> 
> -		intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc,
> link_bpp,
> +		intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc,
> +to_bpp_x16(link_bpp),
>  					 &crtc_state->dp_m_n);
> -		intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc,
> link_bpp,
> +		intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc,
> +to_bpp_x16(link_bpp),
>  					 &remote_m_n);
> 
>  		/*
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
> b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 1d87fbc1e813..295a0f24ebbf 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -339,7 +339,8 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
> 
>  	pipe_config->fdi_lanes = lane;
> 
> -	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> +	intel_link_compute_m_n(to_bpp_x16(pipe_config->pipe_bpp),
> +			       lane, fdi_dotclock,
>  			       link_bw,
>  			       intel_dp_bw_fec_overhead(false),
>  			       &pipe_config->fdi_m_n);
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 04/11] drm/i915/audio: Consider fractional vdsc bpp while computing tu_data

[Kandpal, Suraj]

> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate the precision during calculation of transfer unit data for
> hblank_early calculation.
> 
> v2:
> -Fix tu_data calculation while dealing with U6.4 format. (Stan)
> 
> v3:
> -Use BPP_X16_FMT to print vdsc bpp.
> 

LGTM.

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
> ---
>  drivers/gpu/drm/i915/display/intel_audio.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index aa93ccd6c2aa..8796d90c46a6 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -521,25 +521,25 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
>  	unsigned int link_clks_available, link_clks_required;
>  	unsigned int tu_data, tu_line, link_clks_active;
>  	unsigned int h_active, h_total, hblank_delta, pixel_clk;
> -	unsigned int fec_coeff, cdclk, vdsc_bpp;
> +	unsigned int fec_coeff, cdclk, vdsc_bppx16;
>  	unsigned int link_clk, lanes;
>  	unsigned int hblank_rise;
> 
>  	h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
>  	h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
>  	pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> -	vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> +	vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
>  	cdclk = i915->display.cdclk.hw.cdclk;
>  	/* fec= 0.972261, using rounding multiplier of 1000000 */
>  	fec_coeff = 972261;
>  	link_clk = crtc_state->port_clock;
>  	lanes = crtc_state->lane_count;
> 
> -	drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
> -		    "lanes = %u vdsc_bpp = %u cdclk = %u\n",
> -		    h_active, link_clk, lanes, vdsc_bpp, cdclk);
> +	drm_dbg_kms(&i915->drm,
> +		    "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = "
> BPP_X16_FMT " cdclk = %u\n",
> +		    h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16),
> cdclk);
> 
> -	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
> +	if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 ||
> +!cdclk))
>  		return 0;
> 
>  	link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; @@
> -551,8 +551,8 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
>  		hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 *
> (link_clk + cdclk), pixel_clk),
>  						  mul_u32_u32(link_clk,
> cdclk));
> 
> -	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8,
> 1000000),
> -			    mul_u32_u32(link_clk * lanes, fec_coeff));
> +	tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8,
> 1000000),
> +			    mul_u32_u32(link_clk * lanes * 16, fec_coeff));
>  	tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
>  			    mul_u32_u32(64 * pixel_clk, 1000000));
>  	link_clks_active  = (tu_line - 1) * 64 + tu_data;
> --
> 2.40.1

Re: [Intel-gfx] [PATCH 00/11] Add DSC fractional bpp support

[Nautiyal, Ankit K]

On 11/10/2023 3:40 PM, Ankit Nautiyal wrote:
> This patch series adds support for DSC fractional compressed bpp
> for MTL+. The series starts with some fixes, followed by patches that
> lay groundwork to iterate over valid compressed bpps to select the
> 'best' compressed bpp with optimal link configuration (taken from
> upstream series: https://patchwork.freedesktop.org/series/105200/).
>
> The later patches, add changes to accommodate compressed bpp with
> fractional part, including changes to QP calculations.
> To get the 'best' compressed bpp, we iterate over the valid compressed
> bpp values, but with fractional step size 1/16, 1/8, 1/4 or 1/2 as per
> sink support.
>
> The last 2 patches add support to depict DSC sink's fractional support,
> and debugfs to enforce use of fractional bpp, while choosing an
> appropriate compressed bpp.
>
> Rev10: Rebased and added DSC Fractional support for DP MST.

Pushed patches 1-8 to drm-intel-next, thanks for the reviews, acks.

Regards,

Ankit


>
> Ankit Nautiyal (8):
>    drm/display/dp: Add helper function to get DSC bpp precision
>    drm/i915/display: Store compressed bpp in U6.4 format
>    drm/i915/display: Consider fractional vdsc bpp while computing m_n
>      values
>    drm/i915/audio: Consider fractional vdsc bpp while computing tu_data
>    drm/i915/dp: Iterate over output bpp with fractional step size
>    drm/i915/dp_mst: Use precision of 1/16 for computing bpp
>    drm/i916/dp_mst: Iterate over the DSC bpps as per DSC precision
>      support
>    drm/i915/dp_mst: Add support for forcing dsc fractional bpp via
>      debugfs
>
> Swati Sharma (2):
>    drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
>    drm/i915/dsc: Allow DSC only with fractional bpp when forced from
>      debugfs
>
> Vandita Kulkarni (1):
>    drm/i915/dsc/mtl: Add support for fractional bpp
>
>   drivers/gpu/drm/display/drm_dp_helper.c       | 27 ++++++
>   drivers/gpu/drm/i915/display/icl_dsi.c        | 10 +--
>   drivers/gpu/drm/i915/display/intel_audio.c    | 16 ++--
>   drivers/gpu/drm/i915/display/intel_bios.c     |  4 +-
>   drivers/gpu/drm/i915/display/intel_cdclk.c    |  5 +-
>   drivers/gpu/drm/i915/display/intel_display.c  |  6 +-
>   .../drm/i915/display/intel_display_debugfs.c  | 84 ++++++++++++++++++
>   .../drm/i915/display/intel_display_types.h    |  4 +-
>   drivers/gpu/drm/i915/display/intel_dp.c       | 87 +++++++++++--------
>   drivers/gpu/drm/i915/display/intel_dp_mst.c   | 85 +++++++++++-------
>   drivers/gpu/drm/i915/display/intel_fdi.c      |  3 +-
>   drivers/gpu/drm/i915/display/intel_link_bw.c  |  2 +-
>   .../gpu/drm/i915/display/intel_qp_tables.c    |  3 -
>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 29 +++++--
>   include/drm/display/drm_dp_helper.h           |  1 +
>   15 files changed, 266 insertions(+), 100 deletions(-)
>