diff for duplicates of <20231219085343.1211864-2-mitulkumar.ajitkumar.golani@intel.com> diff --git a/a/1.txt b/N1/1.txt index 7f67feb..7a98672 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -140,5 +140,400 @@ index 863b2e7add29..ab75b421fdf8 100644 void drm_dp_vsc_sdp_log(const char *level, struct device *dev, const struct drm_dp_vsc_sdp *vsc); --- -2.25.1 + +From patchwork Tue Dec 19 08:53:42 2023 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [2/3] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP +From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +X-Patchwork-Id: 572508 +Message-Id: <20231219085343.1211864-3-mitulkumar.ajitkumar.golani@intel.com> +To: intel-gfx@lists.freedesktop.org +Cc: jani.nikula@intel.com +Date: Tue, 19 Dec 2023 14:23:42 +0530 + +Add the necessary structures and functions to handle reading and +unpacking Adaptive Sync Secondary Data Packets. Also add support +to write and pack AS SDP. + +--v2: +- Correct use of REG_BIT and REG_GENMASK. [Jani] +- Use as_sdp instead of async. [Jani] +- Remove unrelated comments and changes. [Jani] +- Correct code indent. [Jani] + +Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +--- + drivers/gpu/drm/i915/display/intel_dp.c | 95 ++++++++++++++++++++++- + drivers/gpu/drm/i915/display/intel_hdmi.c | 12 ++- + drivers/gpu/drm/i915/i915_reg.h | 6 ++ + include/drm/display/drm_dp_helper.h | 3 + + 4 files changed, 112 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index 3b2482bf683f..5dee50f812c6 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -94,7 +94,6 @@ + #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) + #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) + +- + /* Constants for DP DSC configurations */ + static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; + +@@ -4110,6 +4109,34 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, + return false; + } + ++static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, ++ struct dp_sdp *sdp, size_t size) ++{ ++ size_t length = sizeof(struct dp_sdp); ++ ++ if (size < length) ++ return -ENOSPC; ++ ++ memset(sdp, 0, size); ++ ++ /* Prepare AS (Adaptive Sync) SDP Header */ ++ sdp->sdp_header.HB0 = 0; ++ sdp->sdp_header.HB1 = as_sdp->sdp_type; ++ sdp->sdp_header.HB2 = 0x02; ++ sdp->sdp_header.HB3 = as_sdp->length; ++ ++ /* Fill AS (Adaptive Sync) SDP Payload */ ++ sdp->db[1] = 0x0; ++ sdp->db[1] = as_sdp->vtotal & 0xFF; ++ sdp->db[2] = (as_sdp->vtotal >> 8) & 0xF; ++ sdp->db[3] = 0x0; ++ sdp->db[4] = 0x0; ++ sdp->db[7] = 0x0; ++ sdp->db[8] = 0x0; ++ ++ return length; ++} ++ + static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, + struct dp_sdp *sdp, size_t size) + { +@@ -4277,6 +4304,10 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, + &crtc_state->infoframes.drm.drm, + &sdp, sizeof(sdp)); + break; ++ case DP_SDP_ADAPTIVE_SYNC: ++ len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp, ++ sizeof(sdp)); ++ break; + default: + MISSING_CASE(type); + return; +@@ -4315,7 +4346,8 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, + i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); + u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | + VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | +- VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; ++ VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK | ++ VIDEO_DIP_ENABLE_AS_HSW; + u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; + + /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ +@@ -4339,6 +4371,40 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, + intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); + } + ++static ++int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, ++ const void *buffer, size_t size) ++{ ++ const struct dp_sdp *sdp = buffer; ++ ++ if (size < sizeof(struct dp_sdp)) ++ return -EINVAL; ++ ++ memset(as_sdp, 0, sizeof(*as_sdp)); ++ ++ if (sdp->sdp_header.HB0 != 0) ++ return -EINVAL; ++ ++ if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC) ++ return -EINVAL; ++ ++ if (sdp->sdp_header.HB2 != 0x02) ++ return -EINVAL; ++ ++ if ((sdp->sdp_header.HB3 & 0x3F) != 9) ++ return -EINVAL; ++ ++ if ((sdp->db[0] & AS_SDP_OP_MODE) != 0x0) ++ return -EINVAL; ++ ++ as_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1]; ++ as_sdp->target_rr = 0; ++ as_sdp->duration_incr_ms = 0; ++ as_sdp->duration_decr_ms = 0; ++ ++ return 0; ++} ++ + static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, + const void *buffer, size_t size) + { +@@ -4409,6 +4475,27 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, + return 0; + } + ++static int ++intel_read_dp_metadata_infoframe_as_sdp(struct intel_encoder *encoder, ++ struct intel_crtc_state *crtc_state, ++ struct drm_dp_as_sdp *as_sdp) ++{ ++ struct intel_digital_port *dig_port = enc_to_dig_port(encoder); ++ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); ++ unsigned int type = DP_SDP_ADAPTIVE_SYNC; ++ struct dp_sdp sdp = {}; ++ int ret; ++ ++ dig_port->read_infoframe(encoder, crtc_state, type, &sdp, ++ sizeof(sdp)); ++ ++ ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp)); ++ if (ret) ++ drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n"); ++ ++ return ret; ++} ++ + static int + intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, + const void *buffer, size_t size) +@@ -4519,6 +4606,10 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, + intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, + &crtc_state->infoframes.drm.drm); + break; ++ case DP_SDP_ADAPTIVE_SYNC: ++ intel_read_dp_metadata_infoframe_as_sdp(encoder, crtc_state, ++ &crtc_state->infoframes.as_sdp); ++ break; + default: + MISSING_CASE(type); + break; +diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c +index 39e4f5f7c817..ebc12ec102f0 100644 +--- a/drivers/gpu/drm/i915/display/intel_hdmi.c ++++ b/drivers/gpu/drm/i915/display/intel_hdmi.c +@@ -136,6 +136,8 @@ static u32 hsw_infoframe_enable(unsigned int type) + return VIDEO_DIP_ENABLE_GMP_HSW; + case DP_SDP_VSC: + return VIDEO_DIP_ENABLE_VSC_HSW; ++ case DP_SDP_ADAPTIVE_SYNC: ++ return VIDEO_DIP_ENABLE_AS_HSW; + case DP_SDP_PPS: + return VDIP_ENABLE_PPS; + case HDMI_INFOFRAME_TYPE_AVI: +@@ -163,6 +165,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, + return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); + case DP_SDP_VSC: + return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); ++ case DP_SDP_ADAPTIVE_SYNC: ++ return HSW_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i); + case DP_SDP_PPS: + return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); + case HDMI_INFOFRAME_TYPE_AVI: +@@ -185,6 +189,8 @@ static int hsw_dip_data_size(struct drm_i915_private *dev_priv, + switch (type) { + case DP_SDP_VSC: + return VIDEO_DIP_VSC_DATA_SIZE; ++ case DP_SDP_ADAPTIVE_SYNC: ++ return VIDEO_DIP_ASYNC_DATA_SIZE; + case DP_SDP_PPS: + return VIDEO_DIP_PPS_DATA_SIZE; + case HDMI_PACKET_TYPE_GAMUT_METADATA: +@@ -555,7 +561,8 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, + + mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | + VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | +- VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); ++ VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | ++ VIDEO_DIP_ENABLE_AS_HSW); + + if (DISPLAY_VER(dev_priv) >= 10) + mask |= VIDEO_DIP_ENABLE_DRM_GLK; +@@ -567,6 +574,7 @@ static const u8 infoframe_type_to_idx[] = { + HDMI_PACKET_TYPE_GENERAL_CONTROL, + HDMI_PACKET_TYPE_GAMUT_METADATA, + DP_SDP_VSC, ++ DP_SDP_ADAPTIVE_SYNC, + HDMI_INFOFRAME_TYPE_AVI, + HDMI_INFOFRAME_TYPE_SPD, + HDMI_INFOFRAME_TYPE_VENDOR, +@@ -1209,7 +1217,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, + val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | + VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | + VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | +- VIDEO_DIP_ENABLE_DRM_GLK); ++ VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_HSW); + + if (!enable) { + intel_de_write(dev_priv, reg, val); +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +index 27dc903f0553..b13cddc0f09d 100644 +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -2312,6 +2312,7 @@ + * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte + * of the infoframe structure specified by CEA-861. */ + #define VIDEO_DIP_DATA_SIZE 32 ++#define VIDEO_DIP_ASYNC_DATA_SIZE 36 + #define VIDEO_DIP_GMP_DATA_SIZE 36 + #define VIDEO_DIP_VSC_DATA_SIZE 36 + #define VIDEO_DIP_PPS_DATA_SIZE 132 +@@ -2344,6 +2345,7 @@ + #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) + #define VSC_DIP_SW_HEA_DATA (3 << 25) + #define VDIP_ENABLE_PPS (1 << 24) ++#define VIDEO_DIP_ENABLE_AS_HSW REG_BIT(23) + #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) + #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) + #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) +@@ -5038,6 +5040,7 @@ + #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 + #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 + #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 ++#define _HSW_VIDEO_DIP_ASYNC_DATA_A 0x60484 + #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 + #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 + #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 +@@ -5052,6 +5055,7 @@ + #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 + #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 + #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 ++#define _HSW_VIDEO_DIP_ASYNC_DATA_B 0x61484 + #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 + #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 + #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 +@@ -5078,6 +5082,8 @@ + #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) + #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) + #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) ++#define HSW_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(trans,\ ++ _HSW_VIDEO_DIP_ASYNC_DATA_A + (i) * 4) + #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) + #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) + #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) +diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h +index ab75b421fdf8..076c4aa6a5f3 100644 +--- a/include/drm/display/drm_dp_helper.h ++++ b/include/drm/display/drm_dp_helper.h +@@ -838,6 +838,9 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); + #define DRM_DP_BW_OVERHEAD_FEC BIT(3) + #define DRM_DP_BW_OVERHEAD_DSC BIT(4) + ++#define AS_SDP_ENABLE BIT(2) ++#define AS_SDP_OP_MODE GENMASK(1, 0) ++ + int drm_dp_bw_overhead(int lane_count, int hactive, + int dsc_slice_count, + int bpp_x16, unsigned long flags); + +From patchwork Tue Dec 19 08:53:43 2023 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [3/3] drm/i915/display: Compute and Enable AS SDP +From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +X-Patchwork-Id: 572509 +Message-Id: <20231219085343.1211864-4-mitulkumar.ajitkumar.golani@intel.com> +To: intel-gfx@lists.freedesktop.org +Cc: jani.nikula@intel.com +Date: Tue, 19 Dec 2023 14:23:43 +0530 + +Add necessary functions definitions to enable +and compute AS SDP data. The new `intel_dp_compute_as_sdp` +function computes AS SDP values based on the display +configuration, ensuring proper handling of Variable Refresh +Rate (VRR). + +--v2: +- Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit] +- separate patch for intel_read/write_dp_sdp [Ankit]. +- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward [Ankit] +- To fix indentation [Ankit] + +--v3: +- Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes. + +--v4: +- Add HAS_VRR check before write as sdp. + +--v5: +- Add missed HAS_VRR check before read as sdp. + +Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +--- + drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++ + drivers/gpu/drm/i915/display/intel_dp.c | 23 +++++++++++++++++++++++ + 2 files changed, 26 insertions(+) + +diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c +index 38f28c480b38..ed5afaa0ce5d 100644 +--- a/drivers/gpu/drm/i915/display/intel_ddi.c ++++ b/drivers/gpu/drm/i915/display/intel_ddi.c +@@ -3918,6 +3918,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, + intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); + intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); + ++ if ((DISPLAY_VER(dev_priv) >= 13) && HAS_VRR(dev_priv)) ++ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); ++ + intel_psr_get_config(encoder, pipe_config); + + intel_audio_codec_get_config(encoder, pipe_config); +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index 5dee50f812c6..0747b5bda5c8 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -2630,6 +2630,25 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, + &crtc_state->infoframes.vsc); + } + ++static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, ++ struct intel_crtc_state *crtc_state, ++ const struct drm_connector_state *conn_state) ++{ ++ struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; ++ struct intel_connector *connector = intel_dp->attached_connector; ++ const struct drm_display_mode *adjusted_mode = ++ &crtc_state->hw.adjusted_mode; ++ int vrefresh = drm_mode_vrefresh(adjusted_mode); ++ ++ if (!intel_vrr_is_in_range(connector, vrefresh)) ++ return; ++ ++ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); ++ as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; ++ as_sdp->length = 0x9; ++ as_sdp->vtotal = adjusted_mode->vtotal; ++} ++ + void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state, +@@ -2956,6 +2975,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, + g4x_dp_set_clock(encoder, pipe_config); + + intel_vrr_compute_config(pipe_config, conn_state); ++ intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state); + intel_psr_compute_config(intel_dp, pipe_config, conn_state); + intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); + intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); +@@ -4368,6 +4388,9 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, + if (!crtc_state->has_psr) + intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); + ++ if ((DISPLAY_VER(dev_priv) >= 13) && HAS_VRR(dev_priv)) ++ intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); ++ + intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); + } diff --git a/a/content_digest b/N1/content_digest index ae8d25d..a76d2ed 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,11 @@ - "ref\020231219085343.1211864-1-mitulkumar.ajitkumar.golani@intel.com\0" + "ref\020240212164316.1411230-1-mitulkumar.ajitkumar.golani@intel.com\0" "From\0Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\0" - "Subject\0[PATCH 1/3] drm: Add Adaptive Sync SDP logging\0" - "Date\0Tue, 19 Dec 2023 14:23:41 +0530\0" + "Subject\0[1/3] drm: Add Adaptive Sync SDP logging\0" + "Date\0Mon, 12 Feb 2024 22:13:16 +0530\0" "To\0intel-gfx@lists.freedesktop.org\0" - "Cc\0jani.nikula@intel.com\0" + "Cc\0ankit.k.nautiyal@intel.com" + Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> + " jani.nikula@intel.com\0" "\00:1\0" "b\0" "Add structure representing Adaptive Sync Secondary Data\n" @@ -148,7 +150,402 @@ " void drm_dp_vsc_sdp_log(const char *level, struct device *dev,\n" " \t\t\tconst struct drm_dp_vsc_sdp *vsc);\n" " \n" - "-- \n" - 2.25.1 + "\n" + "From patchwork Tue Dec 19 08:53:42 2023\n" + "Content-Type: text/plain; charset=\"utf-8\"\n" + "MIME-Version: 1.0\n" + "Content-Transfer-Encoding: 7bit\n" + "Subject: [2/3] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP\n" + "From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "X-Patchwork-Id: 572508\n" + "Message-Id: <20231219085343.1211864-3-mitulkumar.ajitkumar.golani@intel.com>\n" + "To: intel-gfx@lists.freedesktop.org\n" + "Cc: jani.nikula@intel.com\n" + "Date: Tue, 19 Dec 2023 14:23:42 +0530\n" + "\n" + "Add the necessary structures and functions to handle reading and\n" + "unpacking Adaptive Sync Secondary Data Packets. Also add support\n" + "to write and pack AS SDP.\n" + "\n" + "--v2:\n" + "- Correct use of REG_BIT and REG_GENMASK. [Jani]\n" + "- Use as_sdp instead of async. [Jani]\n" + "- Remove unrelated comments and changes. [Jani]\n" + "- Correct code indent. [Jani]\n" + "\n" + "Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "---\n" + " drivers/gpu/drm/i915/display/intel_dp.c | 95 ++++++++++++++++++++++-\n" + " drivers/gpu/drm/i915/display/intel_hdmi.c | 12 ++-\n" + " drivers/gpu/drm/i915/i915_reg.h | 6 ++\n" + " include/drm/display/drm_dp_helper.h | 3 +\n" + " 4 files changed, 112 insertions(+), 4 deletions(-)\n" + "\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "index 3b2482bf683f..5dee50f812c6 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_dp.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "@@ -94,7 +94,6 @@\n" + " #define INTEL_DP_RESOLUTION_STANDARD\t(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)\n" + " #define INTEL_DP_RESOLUTION_FAILSAFE\t(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)\n" + " \n" + "-\n" + " /* Constants for DP DSC configurations */\n" + " static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};\n" + " \n" + "@@ -4110,6 +4109,34 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,\n" + " \treturn false;\n" + " }\n" + " \n" + "+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,\n" + "+\t\t\t\t struct dp_sdp *sdp, size_t size)\n" + "+{\n" + "+\tsize_t length = sizeof(struct dp_sdp);\n" + "+\n" + "+\tif (size < length)\n" + "+\t\treturn -ENOSPC;\n" + "+\n" + "+\tmemset(sdp, 0, size);\n" + "+\n" + "+\t/* Prepare AS (Adaptive Sync) SDP Header */\n" + "+\tsdp->sdp_header.HB0 = 0;\n" + "+\tsdp->sdp_header.HB1 = as_sdp->sdp_type;\n" + "+\tsdp->sdp_header.HB2 = 0x02;\n" + "+\tsdp->sdp_header.HB3 = as_sdp->length;\n" + "+\n" + "+\t/* Fill AS (Adaptive Sync) SDP Payload */\n" + "+\tsdp->db[1] = 0x0;\n" + "+\tsdp->db[1] = as_sdp->vtotal & 0xFF;\n" + "+\tsdp->db[2] = (as_sdp->vtotal >> 8) & 0xF;\n" + "+\tsdp->db[3] = 0x0;\n" + "+\tsdp->db[4] = 0x0;\n" + "+\tsdp->db[7] = 0x0;\n" + "+\tsdp->db[8] = 0x0;\n" + "+\n" + "+\treturn length;\n" + "+}\n" + "+\n" + " static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,\n" + " \t\t\t\t struct dp_sdp *sdp, size_t size)\n" + " {\n" + "@@ -4277,6 +4304,10 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,\n" + " \t\t\t\t\t\t\t &crtc_state->infoframes.drm.drm,\n" + " \t\t\t\t\t\t\t &sdp, sizeof(sdp));\n" + " \t\tbreak;\n" + "+\tcase DP_SDP_ADAPTIVE_SYNC:\n" + "+\t\tlen = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,\n" + "+\t\t\t\t\t sizeof(sdp));\n" + "+\t\tbreak;\n" + " \tdefault:\n" + " \t\tMISSING_CASE(type);\n" + " \t\treturn;\n" + "@@ -4315,7 +4346,8 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,\n" + " \ti915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);\n" + " \tu32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |\n" + " \t\t\t VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |\n" + "-\t\t\t VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;\n" + "+\t\t\t VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |\n" + "+\t\t\t VIDEO_DIP_ENABLE_AS_HSW;\n" + " \tu32 val = intel_de_read(dev_priv, reg) & ~dip_enable;\n" + " \n" + " \t/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */\n" + "@@ -4339,6 +4371,40 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,\n" + " \tintel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);\n" + " }\n" + " \n" + "+static\n" + "+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,\n" + "+\t\t\t const void *buffer, size_t size)\n" + "+{\n" + "+\tconst struct dp_sdp *sdp = buffer;\n" + "+\n" + "+\tif (size < sizeof(struct dp_sdp))\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tmemset(as_sdp, 0, sizeof(*as_sdp));\n" + "+\n" + "+\tif (sdp->sdp_header.HB0 != 0)\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tif (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tif (sdp->sdp_header.HB2 != 0x02)\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tif ((sdp->sdp_header.HB3 & 0x3F) != 9)\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tif ((sdp->db[0] & AS_SDP_OP_MODE) != 0x0)\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tas_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1];\n" + "+\tas_sdp->target_rr = 0;\n" + "+\tas_sdp->duration_incr_ms = 0;\n" + "+\tas_sdp->duration_decr_ms = 0;\n" + "+\n" + "+\treturn 0;\n" + "+}\n" + "+\n" + " static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,\n" + " \t\t\t\t const void *buffer, size_t size)\n" + " {\n" + "@@ -4409,6 +4475,27 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,\n" + " \treturn 0;\n" + " }\n" + " \n" + "+static int\n" + "+intel_read_dp_metadata_infoframe_as_sdp(struct intel_encoder *encoder,\n" + "+\t\t\t\t\tstruct intel_crtc_state *crtc_state,\n" + "+\t\t\t\t\tstruct drm_dp_as_sdp *as_sdp)\n" + "+{\n" + "+\tstruct intel_digital_port *dig_port = enc_to_dig_port(encoder);\n" + "+\tstruct drm_i915_private *dev_priv = to_i915(encoder->base.dev);\n" + "+\tunsigned int type = DP_SDP_ADAPTIVE_SYNC;\n" + "+\tstruct dp_sdp sdp = {};\n" + "+\tint ret;\n" + "+\n" + "+\tdig_port->read_infoframe(encoder, crtc_state, type, &sdp,\n" + "+\t\t\t\t sizeof(sdp));\n" + "+\n" + "+\tret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));\n" + "+\tif (ret)\n" + "+\t\tdrm_dbg_kms(&dev_priv->drm, \"Failed to unpack DP AS SDP\\n\");\n" + "+\n" + "+\treturn ret;\n" + "+}\n" + "+\n" + " static int\n" + " intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,\n" + " \t\t\t\t\t const void *buffer, size_t size)\n" + "@@ -4519,6 +4606,10 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,\n" + " \t\tintel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,\n" + " \t\t\t\t\t\t\t &crtc_state->infoframes.drm.drm);\n" + " \t\tbreak;\n" + "+\tcase DP_SDP_ADAPTIVE_SYNC:\n" + "+\t\tintel_read_dp_metadata_infoframe_as_sdp(encoder, crtc_state,\n" + "+\t\t\t\t\t\t\t&crtc_state->infoframes.as_sdp);\n" + "+\t\tbreak;\n" + " \tdefault:\n" + " \t\tMISSING_CASE(type);\n" + " \t\tbreak;\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c\n" + "index 39e4f5f7c817..ebc12ec102f0 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_hdmi.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c\n" + "@@ -136,6 +136,8 @@ static u32 hsw_infoframe_enable(unsigned int type)\n" + " \t\treturn VIDEO_DIP_ENABLE_GMP_HSW;\n" + " \tcase DP_SDP_VSC:\n" + " \t\treturn VIDEO_DIP_ENABLE_VSC_HSW;\n" + "+\tcase DP_SDP_ADAPTIVE_SYNC:\n" + "+\t\treturn VIDEO_DIP_ENABLE_AS_HSW;\n" + " \tcase DP_SDP_PPS:\n" + " \t\treturn VDIP_ENABLE_PPS;\n" + " \tcase HDMI_INFOFRAME_TYPE_AVI:\n" + "@@ -163,6 +165,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,\n" + " \t\treturn HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);\n" + " \tcase DP_SDP_VSC:\n" + " \t\treturn HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);\n" + "+\tcase DP_SDP_ADAPTIVE_SYNC:\n" + "+\t\treturn HSW_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i);\n" + " \tcase DP_SDP_PPS:\n" + " \t\treturn ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);\n" + " \tcase HDMI_INFOFRAME_TYPE_AVI:\n" + "@@ -185,6 +189,8 @@ static int hsw_dip_data_size(struct drm_i915_private *dev_priv,\n" + " \tswitch (type) {\n" + " \tcase DP_SDP_VSC:\n" + " \t\treturn VIDEO_DIP_VSC_DATA_SIZE;\n" + "+\tcase DP_SDP_ADAPTIVE_SYNC:\n" + "+\t\treturn VIDEO_DIP_ASYNC_DATA_SIZE;\n" + " \tcase DP_SDP_PPS:\n" + " \t\treturn VIDEO_DIP_PPS_DATA_SIZE;\n" + " \tcase HDMI_PACKET_TYPE_GAMUT_METADATA:\n" + "@@ -555,7 +561,8 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,\n" + " \n" + " \tmask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |\n" + " \t\tVIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |\n" + "-\t\tVIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);\n" + "+\t\tVIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |\n" + "+\t\tVIDEO_DIP_ENABLE_AS_HSW);\n" + " \n" + " \tif (DISPLAY_VER(dev_priv) >= 10)\n" + " \t\tmask |= VIDEO_DIP_ENABLE_DRM_GLK;\n" + "@@ -567,6 +574,7 @@ static const u8 infoframe_type_to_idx[] = {\n" + " \tHDMI_PACKET_TYPE_GENERAL_CONTROL,\n" + " \tHDMI_PACKET_TYPE_GAMUT_METADATA,\n" + " \tDP_SDP_VSC,\n" + "+\tDP_SDP_ADAPTIVE_SYNC,\n" + " \tHDMI_INFOFRAME_TYPE_AVI,\n" + " \tHDMI_INFOFRAME_TYPE_SPD,\n" + " \tHDMI_INFOFRAME_TYPE_VENDOR,\n" + "@@ -1209,7 +1217,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,\n" + " \tval &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |\n" + " \t\t VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |\n" + " \t\t VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |\n" + "-\t\t VIDEO_DIP_ENABLE_DRM_GLK);\n" + "+\t\t VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_HSW);\n" + " \n" + " \tif (!enable) {\n" + " \t\tintel_de_write(dev_priv, reg, val);\n" + "diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h\n" + "index 27dc903f0553..b13cddc0f09d 100644\n" + "--- a/drivers/gpu/drm/i915/i915_reg.h\n" + "+++ b/drivers/gpu/drm/i915/i915_reg.h\n" + "@@ -2312,6 +2312,7 @@\n" + " * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte\n" + " * of the infoframe structure specified by CEA-861. */\n" + " #define VIDEO_DIP_DATA_SIZE\t32\n" + "+#define VIDEO_DIP_ASYNC_DATA_SIZE\t36\n" + " #define VIDEO_DIP_GMP_DATA_SIZE\t36\n" + " #define VIDEO_DIP_VSC_DATA_SIZE\t36\n" + " #define VIDEO_DIP_PPS_DATA_SIZE\t132\n" + "@@ -2344,6 +2345,7 @@\n" + " #define VSC_DIP_HW_DATA_SW_HEA\t(2 << 25)\n" + " #define VSC_DIP_SW_HEA_DATA\t\t(3 << 25)\n" + " #define VDIP_ENABLE_PPS\t\t(1 << 24)\n" + "+#define VIDEO_DIP_ENABLE_AS_HSW\tREG_BIT(23)\n" + " #define VIDEO_DIP_ENABLE_VSC_HSW\t(1 << 20)\n" + " #define VIDEO_DIP_ENABLE_GCP_HSW\t(1 << 16)\n" + " #define VIDEO_DIP_ENABLE_AVI_HSW\t(1 << 12)\n" + "@@ -5038,6 +5040,7 @@\n" + " #define _HSW_VIDEO_DIP_SPD_DATA_A\t0x602A0\n" + " #define _HSW_VIDEO_DIP_GMP_DATA_A\t0x602E0\n" + " #define _HSW_VIDEO_DIP_VSC_DATA_A\t0x60320\n" + "+#define\t_HSW_VIDEO_DIP_ASYNC_DATA_A\t0x60484\n" + " #define _GLK_VIDEO_DIP_DRM_DATA_A\t0x60440\n" + " #define _HSW_VIDEO_DIP_AVI_ECC_A\t0x60240\n" + " #define _HSW_VIDEO_DIP_VS_ECC_A\t\t0x60280\n" + "@@ -5052,6 +5055,7 @@\n" + " #define _HSW_VIDEO_DIP_SPD_DATA_B\t0x612A0\n" + " #define _HSW_VIDEO_DIP_GMP_DATA_B\t0x612E0\n" + " #define _HSW_VIDEO_DIP_VSC_DATA_B\t0x61320\n" + "+#define\t_HSW_VIDEO_DIP_ASYNC_DATA_B\t0x61484\n" + " #define _GLK_VIDEO_DIP_DRM_DATA_B\t0x61440\n" + " #define _HSW_VIDEO_DIP_BVI_ECC_B\t0x61240\n" + " #define _HSW_VIDEO_DIP_VS_ECC_B\t\t0x61280\n" + "@@ -5078,6 +5082,8 @@\n" + " #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)\t_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)\n" + " #define HSW_TVIDEO_DIP_GMP_DATA(trans, i)\t_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)\n" + " #define HSW_TVIDEO_DIP_VSC_DATA(trans, i)\t_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)\n" + "+#define HSW_TVIDEO_DIP_AS_SDP_DATA(trans, i)\t_MMIO_TRANS2(trans,\\\n" + "+\t\t\t\t\t\t\t _HSW_VIDEO_DIP_ASYNC_DATA_A + (i) * 4)\n" + " #define GLK_TVIDEO_DIP_DRM_DATA(trans, i)\t_MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)\n" + " #define ICL_VIDEO_DIP_PPS_DATA(trans, i)\t_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)\n" + " #define ICL_VIDEO_DIP_PPS_ECC(trans, i)\t\t_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)\n" + "diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h\n" + "index ab75b421fdf8..076c4aa6a5f3 100644\n" + "--- a/include/drm/display/drm_dp_helper.h\n" + "+++ b/include/drm/display/drm_dp_helper.h\n" + "@@ -838,6 +838,9 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);\n" + " #define DRM_DP_BW_OVERHEAD_FEC\t\tBIT(3)\n" + " #define DRM_DP_BW_OVERHEAD_DSC\t\tBIT(4)\n" + " \n" + "+#define AS_SDP_ENABLE\t\t\t\tBIT(2)\n" + "+#define AS_SDP_OP_MODE\t\t\t\tGENMASK(1, 0)\n" + "+\n" + " int drm_dp_bw_overhead(int lane_count, int hactive,\n" + " \t\t int dsc_slice_count,\n" + " \t\t int bpp_x16, unsigned long flags);\n" + "\n" + "From patchwork Tue Dec 19 08:53:43 2023\n" + "Content-Type: text/plain; charset=\"utf-8\"\n" + "MIME-Version: 1.0\n" + "Content-Transfer-Encoding: 7bit\n" + "Subject: [3/3] drm/i915/display: Compute and Enable AS SDP\n" + "From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "X-Patchwork-Id: 572509\n" + "Message-Id: <20231219085343.1211864-4-mitulkumar.ajitkumar.golani@intel.com>\n" + "To: intel-gfx@lists.freedesktop.org\n" + "Cc: jani.nikula@intel.com\n" + "Date: Tue, 19 Dec 2023 14:23:43 +0530\n" + "\n" + "Add necessary functions definitions to enable\n" + "and compute AS SDP data. The new `intel_dp_compute_as_sdp`\n" + "function computes AS SDP values based on the display\n" + "configuration, ensuring proper handling of Variable Refresh\n" + "Rate (VRR).\n" + "\n" + "--v2:\n" + "- Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit]\n" + "- separate patch for intel_read/write_dp_sdp [Ankit].\n" + "- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward [Ankit]\n" + "- To fix indentation [Ankit]\n" + "\n" + "--v3:\n" + "- Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.\n" + "\n" + "--v4:\n" + "- Add HAS_VRR check before write as sdp.\n" + "\n" + "--v5:\n" + "- Add missed HAS_VRR check before read as sdp.\n" + "\n" + "Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "---\n" + " drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++\n" + " drivers/gpu/drm/i915/display/intel_dp.c | 23 +++++++++++++++++++++++\n" + " 2 files changed, 26 insertions(+)\n" + "\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c\n" + "index 38f28c480b38..ed5afaa0ce5d 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_ddi.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_ddi.c\n" + "@@ -3918,6 +3918,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,\n" + " \tintel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);\n" + " \tintel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);\n" + " \n" + "+\tif ((DISPLAY_VER(dev_priv) >= 13) && HAS_VRR(dev_priv))\n" + "+\t\tintel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);\n" + "+\n" + " \tintel_psr_get_config(encoder, pipe_config);\n" + " \n" + " \tintel_audio_codec_get_config(encoder, pipe_config);\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "index 5dee50f812c6..0747b5bda5c8 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_dp.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "@@ -2630,6 +2630,25 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,\n" + " \t\t\t\t\t &crtc_state->infoframes.vsc);\n" + " }\n" + " \n" + "+static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,\n" + "+\t\t\t\t struct intel_crtc_state *crtc_state,\n" + "+\t\t\t\t const struct drm_connector_state *conn_state)\n" + "+{\n" + "+\tstruct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;\n" + "+\tstruct intel_connector *connector = intel_dp->attached_connector;\n" + "+\tconst struct drm_display_mode *adjusted_mode =\n" + "+\t\t&crtc_state->hw.adjusted_mode;\n" + "+\tint vrefresh = drm_mode_vrefresh(adjusted_mode);\n" + "+\n" + "+\tif (!intel_vrr_is_in_range(connector, vrefresh))\n" + "+\t\treturn;\n" + "+\n" + "+\tcrtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);\n" + "+\tas_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;\n" + "+\tas_sdp->length = 0x9;\n" + "+\tas_sdp->vtotal = adjusted_mode->vtotal;\n" + "+}\n" + "+\n" + " void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,\n" + " \t\t\t\t const struct intel_crtc_state *crtc_state,\n" + " \t\t\t\t const struct drm_connector_state *conn_state,\n" + "@@ -2956,6 +2975,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,\n" + " \t\tg4x_dp_set_clock(encoder, pipe_config);\n" + " \n" + " \tintel_vrr_compute_config(pipe_config, conn_state);\n" + "+\tintel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);\n" + " \tintel_psr_compute_config(intel_dp, pipe_config, conn_state);\n" + " \tintel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);\n" + " \tintel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);\n" + "@@ -4368,6 +4388,9 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,\n" + " \tif (!crtc_state->has_psr)\n" + " \t\tintel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);\n" + " \n" + "+\tif ((DISPLAY_VER(dev_priv) >= 13) && HAS_VRR(dev_priv))\n" + "+\t\tintel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);\n" + "+\n" + " \tintel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);\n" + } -7098a335c5d42cbc78cbca3225aa35811b89f0699b31939b75c7d5655ad011a6 +080075ead9c95ab8f3740453d3498a7801c70913eb5b1ba4c265d44d74bc0afa
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