diff for duplicates of <20240229163957.2948182-2-mitulkumar.ajitkumar.golani@intel.com> diff --git a/a/1.txt b/N1/1.txt index 9a19506..17dceec 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -58,5 +58,1001 @@ index 0c1a4021e098..7c1aa3a703c8 100644 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); --- -2.25.1 + +From patchwork Thu Feb 29 16:39:50 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v14,2/9] drm: Add Adaptive Sync SDP logging +From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +X-Patchwork-Id: 580636 +Message-Id: <20240229163957.2948182-3-mitulkumar.ajitkumar.golani@intel.com> +To: intel-gfx@lists.freedesktop.org +Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, + ankit.k.nautiyal@intel.com, + Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +Date: Thu, 29 Feb 2024 22:09:50 +0530 + +Add structure representing Adaptive Sync Secondary Data Packet (AS SDP). +Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate +debugging. + +--v2: +- Update logging. [Jani, Ankit] +- Use 'as_sdp' instead of 'async' [Ankit] +- Correct define placeholders to where they are actually used. [Jani] +- Update members in 'as_sdp' structure to make it uniform. [Jani] + +--v3: +- Added changes to dri-devel mailing list. No code changes. + +--v4: +- Instead of directly using operation mode, use an enum to accommodate +all operation modes (Ankit). + +--v5: +Nit-pick changes to commit message. + +--v6: +- Add correct place holder and name change for AS_SDP_OP_MODE. +- Separate i915 changes from drm changes. +- Remove extra lines. + +Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +--- + drivers/gpu/drm/display/drm_dp_helper.c | 12 ++++++++++ + include/drm/display/drm_dp.h | 10 +++++++++ + include/drm/display/drm_dp_helper.h | 29 +++++++++++++++++++++++++ + 3 files changed, 51 insertions(+) + +diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c +index f94c04db7187..b1459ac92aea 100644 +--- a/drivers/gpu/drm/display/drm_dp_helper.c ++++ b/drivers/gpu/drm/display/drm_dp_helper.c +@@ -2913,6 +2913,18 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc) + } + EXPORT_SYMBOL(drm_dp_vsc_sdp_log); + ++void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp) ++{ ++ drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n", ++ as_sdp->revision, as_sdp->length); ++ drm_printf(p, " vtotal: %d\n", as_sdp->vtotal); ++ drm_printf(p, " target_rr: %d\n", as_sdp->target_rr); ++ drm_printf(p, " duration_incr_ms: %d\n", as_sdp->duration_incr_ms); ++ drm_printf(p, " duration_decr_ms: %d\n", as_sdp->duration_decr_ms); ++ drm_printf(p, " operation_mode: %d\n", as_sdp->mode); ++} ++EXPORT_SYMBOL(drm_dp_as_sdp_log); ++ + /** + * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported + * @aux: DisplayPort AUX channel +diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h +index 281afff6ee4e..ba388ad48ade 100644 +--- a/include/drm/display/drm_dp.h ++++ b/include/drm/display/drm_dp.h +@@ -1149,6 +1149,7 @@ + + #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ + # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0) ++# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE GENMASK(1, 0) + # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1) + # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (1 << 4) + +@@ -1578,10 +1579,12 @@ enum drm_dp_phy { + #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ + #define DP_SDP_ISRC 0x06 /* DP 1.2 */ + #define DP_SDP_VSC 0x07 /* DP 1.2 */ ++#define DP_SDP_ADAPTIVE_SYNC 0x22 /* DP 1.4 */ + #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ + #define DP_SDP_PPS 0x10 /* DP 1.4 */ + #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ + #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ ++ + /* 0x80+ CEA-861 infoframe types */ + + #define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b +@@ -1737,4 +1740,11 @@ enum dp_content_type { + DP_CONTENT_TYPE_GAME = 0x04, + }; + ++enum operation_mode { ++ DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00, ++ DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01, ++ DP_AS_SDP_FAVT_TRR_NOT_REACHED = 0x02, ++ DP_AS_SDP_FAVT_TRR_REACHED = 0x03 ++}; ++ + #endif /* _DRM_DP_H_ */ +diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h +index 7c1aa3a703c8..94eb0d92abae 100644 +--- a/include/drm/display/drm_dp_helper.h ++++ b/include/drm/display/drm_dp_helper.h +@@ -98,6 +98,35 @@ struct drm_dp_vsc_sdp { + enum dp_content_type content_type; + }; + ++/** ++ * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP ++ * ++ * This structure represents a DP AS SDP of drm ++ * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and ++ * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8] ++ * ++ * @sdp_type: Secondary-data packet type ++ * @revision: Revision Number ++ * @length: Number of valid data bytes ++ * @vtotal: Minimum Vertical Vtotal ++ * @target_rr: Target Refresh ++ * @duration_incr_ms: Successive frame duration increase ++ * @duration_decr_ms: Successive frame duration decrease ++ * @operation_mode: Adaptive Sync Operation Mode ++ */ ++struct drm_dp_as_sdp { ++ unsigned char sdp_type; ++ unsigned char revision; ++ unsigned char length; ++ int vtotal; ++ int target_rr; ++ int duration_incr_ms; ++ int duration_decr_ms; ++ enum operation_mode mode; ++}; ++ ++void drm_dp_as_sdp_log(struct drm_printer *p, ++ const struct drm_dp_as_sdp *as_sdp); + void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); + + bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); + +From patchwork Thu Feb 29 16:39:51 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v14,3/9] drm: Add crtc state dump for Adaptive Sync SDP +From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +X-Patchwork-Id: 580634 +Message-Id: <20240229163957.2948182-4-mitulkumar.ajitkumar.golani@intel.com> +To: intel-gfx@lists.freedesktop.org +Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, + ankit.k.nautiyal@intel.com, + Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +Date: Thu, 29 Feb 2024 22:09:51 +0530 + +Add crtc state dump for Adaptive Sync SDP to know which +crtc specifically caused the failure. + +Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +--- + .../gpu/drm/i915/display/intel_crtc_state_dump.c | 13 +++++++++++++ + drivers/gpu/drm/i915/display/intel_display_types.h | 1 + + 2 files changed, 14 insertions(+) + +diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +index 4bcf446c75f4..1e4618271156 100644 +--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c ++++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +@@ -51,6 +51,15 @@ intel_dump_infoframe(struct drm_i915_private *i915, + hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame); + } + ++static void ++intel_dump_dp_as_sdp(struct drm_i915_private *i915, ++ const struct drm_dp_as_sdp *as_sdp) ++{ ++ struct drm_printer p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, "AS_SDP"); ++ ++ drm_dp_as_sdp_log(&p, as_sdp); ++} ++ + static void + intel_dump_dp_vsc_sdp(struct drm_i915_private *i915, + const struct drm_dp_vsc_sdp *vsc) +@@ -302,6 +311,10 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, + if (pipe_config->infoframes.enable & + intel_hdmi_infoframe_enable(DP_SDP_VSC)) + intel_dump_dp_vsc_sdp(i915, &pipe_config->infoframes.vsc); ++ if (pipe_config->infoframes.enable & ++ intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) ++ intel_dump_dp_as_sdp(i915, &pipe_config->infoframes.as_sdp); ++ + + if (pipe_config->has_audio) + intel_dump_buffer(i915, "ELD: ", pipe_config->eld, +diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h +index 8ce986fadd9a..1256730ea276 100644 +--- a/drivers/gpu/drm/i915/display/intel_display_types.h ++++ b/drivers/gpu/drm/i915/display/intel_display_types.h +@@ -1335,6 +1335,7 @@ struct intel_crtc_state { + union hdmi_infoframe hdmi; + union hdmi_infoframe drm; + struct drm_dp_vsc_sdp vsc; ++ struct drm_dp_as_sdp as_sdp; + } infoframes; + + u8 eld[MAX_ELD_BYTES]; + +From patchwork Thu Feb 29 16:39:52 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v14,4/9] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP +From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +X-Patchwork-Id: 580637 +Message-Id: <20240229163957.2948182-5-mitulkumar.ajitkumar.golani@intel.com> +To: intel-gfx@lists.freedesktop.org +Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, + ankit.k.nautiyal@intel.com, + Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +Date: Thu, 29 Feb 2024 22:09:52 +0530 + +Add the necessary structures and functions to handle reading and +unpacking Adaptive Sync Secondary Data Packets. Also add support +to write and pack AS SDP. + +--v2: +- Correct use of REG_BIT and REG_GENMASK. [Jani] +- Use as_sdp instead of async. [Jani] +- Remove unrelated comments and changes. [Jani] +- Correct code indent. [Jani] + +--v3: +- Update definition names for AS SDP which are starting from +HSW, as these defines are applicable for ADLP+.(Ankit) + +--v4: +- Remove as_sdp_mode from crtc_state. +- Drop metadata keyword. +- For consistency, update ADL_ prefix or post fix as required. + +--v5: +- Check if AS_SDP bit is set in crtc_state->infoframes.enable. If not + return. +- Check for HAS_AS_SDP() before setting VIDEO_DIP_ENABLE_AS_ADL mask. +Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +--- + .../drm/i915/display/intel_display_device.h | 1 + + drivers/gpu/drm/i915/display/intel_dp.c | 91 +++++++++++++++++++ + drivers/gpu/drm/i915/display/intel_hdmi.c | 12 ++- + drivers/gpu/drm/i915/i915_reg.h | 8 ++ + include/drm/display/drm_dp_helper.h | 2 +- + 5 files changed, 112 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h +index fe4268813786..6399fbc6c738 100644 +--- a/drivers/gpu/drm/i915/display/intel_display_device.h ++++ b/drivers/gpu/drm/i915/display/intel_display_device.h +@@ -68,6 +68,7 @@ struct drm_printer; + #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ + BIT(trans)) != 0) + #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) ++#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13) + #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) + #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) + #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index e13121dc3a03..7cf849015797 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -4089,6 +4089,32 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, + return false; + } + ++static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, ++ struct dp_sdp *sdp, size_t size) ++{ ++ size_t length = sizeof(struct dp_sdp); ++ ++ if (size < length) ++ return -ENOSPC; ++ ++ memset(sdp, 0, size); ++ ++ /* Prepare AS (Adaptive Sync) SDP Header */ ++ sdp->sdp_header.HB0 = 0; ++ sdp->sdp_header.HB1 = as_sdp->sdp_type; ++ sdp->sdp_header.HB2 = 0x02; ++ sdp->sdp_header.HB3 = as_sdp->length; ++ ++ /* Fill AS (Adaptive Sync) SDP Payload */ ++ sdp->db[0] = as_sdp->mode; ++ sdp->db[1] = as_sdp->vtotal & 0xFF; ++ sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; ++ sdp->db[3] = as_sdp->target_rr; ++ sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; ++ ++ return length; ++} ++ + static ssize_t + intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915, + const struct hdmi_drm_infoframe *drm_infoframe, +@@ -4188,6 +4214,10 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, + &crtc_state->infoframes.drm.drm, + &sdp, sizeof(sdp)); + break; ++ case DP_SDP_ADAPTIVE_SYNC: ++ len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp, ++ sizeof(sdp)); ++ break; + default: + MISSING_CASE(type); + return; +@@ -4209,6 +4239,10 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, + u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | + VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | + VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; ++ ++ if (HAS_AS_SDP(dev_priv)) ++ dip_enable |= VIDEO_DIP_ENABLE_AS_ADL; ++ + u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; + + /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ +@@ -4230,6 +4264,36 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, + intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); + } + ++static ++int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, ++ const void *buffer, size_t size) ++{ ++ const struct dp_sdp *sdp = buffer; ++ ++ if (size < sizeof(struct dp_sdp)) ++ return -EINVAL; ++ ++ memset(as_sdp, 0, sizeof(*as_sdp)); ++ ++ if (sdp->sdp_header.HB0 != 0) ++ return -EINVAL; ++ ++ if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC) ++ return -EINVAL; ++ ++ if (sdp->sdp_header.HB2 != 0x02) ++ return -EINVAL; ++ ++ if ((sdp->sdp_header.HB3 & 0x3F) != 9) ++ return -EINVAL; ++ ++ as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; ++ as_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1]; ++ as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); ++ ++ return 0; ++} ++ + static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, + const void *buffer, size_t size) + { +@@ -4300,6 +4364,29 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, + return 0; + } + ++static void ++intel_read_dp_infoframe_as_sdp(struct intel_encoder *encoder, ++ struct intel_crtc_state *crtc_state, ++ struct drm_dp_as_sdp *as_sdp) ++{ ++ struct intel_digital_port *dig_port = enc_to_dig_port(encoder); ++ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); ++ unsigned int type = DP_SDP_ADAPTIVE_SYNC; ++ struct dp_sdp sdp = {}; ++ int ret; ++ ++ if ((crtc_state->infoframes.enable & ++ intel_hdmi_infoframe_enable(type)) == 0) ++ return; ++ ++ dig_port->read_infoframe(encoder, crtc_state, type, &sdp, ++ sizeof(sdp)); ++ ++ ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp)); ++ if (ret) ++ drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n"); ++} ++ + static int + intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, + const void *buffer, size_t size) +@@ -4406,6 +4493,10 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, + intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, + &crtc_state->infoframes.drm.drm); + break; ++ case DP_SDP_ADAPTIVE_SYNC: ++ intel_read_dp_infoframe_as_sdp(encoder, crtc_state, ++ &crtc_state->infoframes.as_sdp); ++ break; + default: + MISSING_CASE(type); + break; +diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c +index 90d2236fede3..fb134bf64dae 100644 +--- a/drivers/gpu/drm/i915/display/intel_hdmi.c ++++ b/drivers/gpu/drm/i915/display/intel_hdmi.c +@@ -137,6 +137,8 @@ static u32 hsw_infoframe_enable(unsigned int type) + return VIDEO_DIP_ENABLE_GMP_HSW; + case DP_SDP_VSC: + return VIDEO_DIP_ENABLE_VSC_HSW; ++ case DP_SDP_ADAPTIVE_SYNC: ++ return VIDEO_DIP_ENABLE_AS_ADL; + case DP_SDP_PPS: + return VDIP_ENABLE_PPS; + case HDMI_INFOFRAME_TYPE_AVI: +@@ -164,6 +166,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, + return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); + case DP_SDP_VSC: + return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); ++ case DP_SDP_ADAPTIVE_SYNC: ++ return ADL_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i); + case DP_SDP_PPS: + return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); + case HDMI_INFOFRAME_TYPE_AVI: +@@ -186,6 +190,8 @@ static int hsw_dip_data_size(struct drm_i915_private *dev_priv, + switch (type) { + case DP_SDP_VSC: + return VIDEO_DIP_VSC_DATA_SIZE; ++ case DP_SDP_ADAPTIVE_SYNC: ++ return VIDEO_DIP_ASYNC_DATA_SIZE; + case DP_SDP_PPS: + return VIDEO_DIP_PPS_DATA_SIZE; + case HDMI_PACKET_TYPE_GAMUT_METADATA: +@@ -563,6 +569,9 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, + if (DISPLAY_VER(dev_priv) >= 10) + mask |= VIDEO_DIP_ENABLE_DRM_GLK; + ++ if (HAS_AS_SDP(dev_priv)) ++ mask |= VIDEO_DIP_ENABLE_AS_ADL; ++ + return val & mask; + } + +@@ -570,6 +579,7 @@ static const u8 infoframe_type_to_idx[] = { + HDMI_PACKET_TYPE_GENERAL_CONTROL, + HDMI_PACKET_TYPE_GAMUT_METADATA, + DP_SDP_VSC, ++ DP_SDP_ADAPTIVE_SYNC, + HDMI_INFOFRAME_TYPE_AVI, + HDMI_INFOFRAME_TYPE_SPD, + HDMI_INFOFRAME_TYPE_VENDOR, +@@ -1212,7 +1222,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, + val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | + VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | + VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | +- VIDEO_DIP_ENABLE_DRM_GLK); ++ VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); + + if (!enable) { + intel_de_write(dev_priv, reg, val); +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +index e00557e1a57f..dce276236707 100644 +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -2312,6 +2312,7 @@ + * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte + * of the infoframe structure specified by CEA-861. */ + #define VIDEO_DIP_DATA_SIZE 32 ++#define VIDEO_DIP_ASYNC_DATA_SIZE 36 + #define VIDEO_DIP_GMP_DATA_SIZE 36 + #define VIDEO_DIP_VSC_DATA_SIZE 36 + #define VIDEO_DIP_PPS_DATA_SIZE 132 +@@ -2350,6 +2351,8 @@ + #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) + #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) + #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) ++/* ADL and later: */ ++#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23) + + /* Panel fitting */ + #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) +@@ -5040,6 +5043,7 @@ + #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 + #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 + #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 ++#define _ADL_VIDEO_DIP_AS_DATA_A 0x60484 + #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 + #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 + #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 +@@ -5054,6 +5058,7 @@ + #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 + #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 + #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 ++#define _ADL_VIDEO_DIP_AS_DATA_B 0x61484 + #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 + #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 + #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 +@@ -5083,6 +5088,9 @@ + #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) + #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) + #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) ++/*ADLP and later: */ ++#define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(trans,\ ++ _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) + + #define _HSW_STEREO_3D_CTL_A 0x70020 + #define S3D_ENABLE (1 << 31) +diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h +index 94eb0d92abae..3f6003656e3d 100644 +--- a/include/drm/display/drm_dp_helper.h ++++ b/include/drm/display/drm_dp_helper.h +@@ -130,8 +130,8 @@ void drm_dp_as_sdp_log(struct drm_printer *p, + void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); + + bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); +-bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); + ++bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); + int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); + + static inline int + +From patchwork Thu Feb 29 16:39:53 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v14,5/9] drm/i915/dp: Add wrapper function to check AS SDP +From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +X-Patchwork-Id: 580643 +Message-Id: <20240229163957.2948182-6-mitulkumar.ajitkumar.golani@intel.com> +To: intel-gfx@lists.freedesktop.org +Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, + ankit.k.nautiyal@intel.com, + Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +Date: Thu, 29 Feb 2024 22:09:53 +0530 + +Add a wrapper function to check if both the source and +sink support Adaptive Sync SDP. + +--v1: +Just use drm/i915/dp in subject line. + +Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +--- + drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++ + drivers/gpu/drm/i915/display/intel_dp.h | 1 + + 2 files changed, 9 insertions(+) + +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index 7cf849015797..b26efce4a041 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -120,6 +120,14 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) + return dig_port->base.type == INTEL_OUTPUT_EDP; + } + ++bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp) ++{ ++ struct drm_i915_private *i915 = dp_to_i915(intel_dp); ++ ++ return HAS_AS_SDP(i915) && ++ drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd); ++} ++ + static void intel_dp_unset_edid(struct intel_dp *intel_dp); + + /* Is link rate UHBR and thus 128b/132b? */ +diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h +index 530cc97bc42f..cc5e069091ff 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.h ++++ b/drivers/gpu/drm/i915/display/intel_dp.h +@@ -80,6 +80,7 @@ void intel_dp_audio_compute_config(struct intel_encoder *encoder, + struct drm_connector_state *conn_state); + bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); + bool intel_dp_is_edp(struct intel_dp *intel_dp); ++bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp); + bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); + int intel_dp_link_symbol_size(int rate); + int intel_dp_link_symbol_clock(int rate); + +From patchwork Thu Feb 29 16:39:54 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v14,6/9] drm/i915/display: Compute AS SDP parameters +From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +X-Patchwork-Id: 580646 +Message-Id: <20240229163957.2948182-7-mitulkumar.ajitkumar.golani@intel.com> +To: intel-gfx@lists.freedesktop.org +Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, + ankit.k.nautiyal@intel.com, + Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +Date: Thu, 29 Feb 2024 22:09:54 +0530 + +Add necessary function definitions to compute AS SDP data. +The new intel_dp_compute_as_sdp function computes AS SDP +values based on the display configuration, ensuring proper +handling of Variable Refresh Rate (VRR). + +--v2: +- Added DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx(). [Ankit] +- Separated patch for intel_read/write_dp_sdp. [Ankit] +- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward. [Ankit] +- Fixed indentation issues. [Ankit] + +--v3: +- Added VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes. + +--v4: +- Added HAS_VRR check before writing AS SDP. + +--v5: +Added missed HAS_VRR check before reading AS SDP. + +--v6: +- Used Adaptive Sync sink status as a check for read/write SDP. (Ankit) + +--v7: +- Remove as_sdp_enable from crtc_state. +- Add a comment mentioning current support of + DP_AS_SDP_AVT_FIXED_VTOTAL. +- Add state checker for AS_SDP infoframe enable. + +--v8: +- Drop conn_state from intel_dp_compute_as_sdp, as not used. +- Remove fullstop in subject line. +Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> +--- + drivers/gpu/drm/i915/display/intel_dp.c | 26 +++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index b26efce4a041..86de854516ef 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -2626,6 +2626,31 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc + vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; + } + ++static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, ++ struct intel_crtc_state *crtc_state) ++{ ++ struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; ++ struct intel_connector *connector = intel_dp->attached_connector; ++ const struct drm_display_mode *adjusted_mode = ++ &crtc_state->hw.adjusted_mode; ++ int vrefresh = drm_mode_vrefresh(adjusted_mode); ++ ++ if (!intel_vrr_is_in_range(connector, vrefresh) || ++ !intel_dp_as_sdp_supported(intel_dp)) ++ return; ++ ++ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); ++ ++ /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */ ++ as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; ++ as_sdp->length = 0x9; ++ as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; ++ as_sdp->vtotal = adjusted_mode->vtotal; ++ as_sdp->target_rr = 0; ++ as_sdp->duration_incr_ms = 0; ++ as_sdp->duration_incr_ms = 0; ++} ++ + static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +@@ -2951,6 +2976,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, + g4x_dp_set_clock(encoder, pipe_config); + + intel_vrr_compute_config(pipe_config, conn_state); ++ intel_dp_compute_as_sdp(intel_dp, pipe_config); + intel_psr_compute_config(intel_dp, pipe_config, conn_state); + intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); + intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); + +From patchwork Thu Feb 29 16:39:55 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v14,7/9] drm/i915/display: Add state checker for Adaptive Sync SDP +From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +X-Patchwork-Id: 580645 +Message-Id: <20240229163957.2948182-8-mitulkumar.ajitkumar.golani@intel.com> +To: intel-gfx@lists.freedesktop.org +Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, + ankit.k.nautiyal@intel.com, + Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +Date: Thu, 29 Feb 2024 22:09:55 +0530 + +Enable infoframe and add state checker for Adaptive Sync +SDP enablement. + +--v1: +- crtc_state->infoframes.enable, to add on correct place holder. + +Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +--- + drivers/gpu/drm/i915/display/intel_display.c | 46 ++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c +index 00ac65a14029..be0a5fae4e58 100644 +--- a/drivers/gpu/drm/i915/display/intel_display.c ++++ b/drivers/gpu/drm/i915/display/intel_display.c +@@ -4781,6 +4781,17 @@ intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, + a->content_type == b->content_type; + } + ++static bool ++intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a, ++ const struct drm_dp_as_sdp *b) ++{ ++ return a->vtotal == b->vtotal && ++ a->target_rr == b->target_rr && ++ a->duration_incr_ms == b->duration_incr_ms && ++ a->duration_decr_ms == b->duration_decr_ms && ++ a->mode == b->mode; ++} ++ + static bool + intel_compare_buffer(const u8 *a, const u8 *b, size_t len) + { +@@ -4836,6 +4847,30 @@ pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *i915, + drm_dp_vsc_sdp_log(&p, b); + } + ++static void ++pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915, ++ bool fastset, const char *name, ++ const struct drm_dp_as_sdp *a, ++ const struct drm_dp_as_sdp *b) ++{ ++ struct drm_printer p; ++ ++ if (fastset) { ++ p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL); ++ ++ drm_printf(&p, "fastset requirement not met in %s dp sdp\n", name); ++ } else { ++ p = drm_err_printer(&i915->drm, NULL); ++ ++ drm_printf(&p, "mismatch in %s dp sdp\n", name); ++ } ++ ++ drm_printf(&p, "expected:\n"); ++ drm_dp_as_sdp_log(&p, a); ++ drm_printf(&p, "found:\n"); ++ drm_dp_as_sdp_log(&p, b); ++} ++ + /* Returns the length up to and including the last differing byte */ + static size_t + memcmp_diff_len(const u8 *a, const u8 *b, size_t len) +@@ -5089,6 +5124,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, + } \ + } while (0) + ++#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \ ++ if (!intel_compare_dp_as_sdp(¤t_config->infoframes.name, \ ++ &pipe_config->infoframes.name)) { \ ++ pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, __stringify(name), \ ++ ¤t_config->infoframes.name, \ ++ &pipe_config->infoframes.name); \ ++ ret = false; \ ++ } \ ++} while (0) ++ + #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ + BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ + BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ +@@ -5270,6 +5315,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, + PIPE_CONF_CHECK_INFOFRAME(hdmi); + PIPE_CONF_CHECK_INFOFRAME(drm); + PIPE_CONF_CHECK_DP_VSC_SDP(vsc); ++ PIPE_CONF_CHECK_DP_AS_SDP(as_sdp); + + PIPE_CONF_CHECK_X(sync_mode_slaves_mask); + PIPE_CONF_CHECK_I(master_transcoder); + +From patchwork Thu Feb 29 16:39:56 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v14,8/9] drm/i915/display: Compute vrr_vsync params +From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +X-Patchwork-Id: 580642 +Message-Id: <20240229163957.2948182-9-mitulkumar.ajitkumar.golani@intel.com> +To: intel-gfx@lists.freedesktop.org +Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, + ankit.k.nautiyal@intel.com, + Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +Date: Thu, 29 Feb 2024 22:09:56 +0530 + +Compute vrr_vsync_start/end, which sets the position +for hardware to send the Vsync at a fixed position +relative to the end of the Vblank. + +--v2: +- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit) +- Updated bit fields of VRR_VSYNC_START/END. (Ankit) + +--v3: +- Add PIPE_CONF_CHECK_I(vrr.vsync_start/end). +- Read/write vrr_vsync params only when we intend to send +adaptive_sync sdp. + +Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +--- + drivers/gpu/drm/i915/display/intel_display.c | 2 ++ + .../drm/i915/display/intel_display_types.h | 1 + + drivers/gpu/drm/i915/display/intel_vrr.c | 29 +++++++++++++++++-- + drivers/gpu/drm/i915/i915_reg.h | 7 +++++ + 4 files changed, 37 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c +index be0a5fae4e58..c523eec4d626 100644 +--- a/drivers/gpu/drm/i915/display/intel_display.c ++++ b/drivers/gpu/drm/i915/display/intel_display.c +@@ -5367,6 +5367,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, + PIPE_CONF_CHECK_I(vrr.flipline); + PIPE_CONF_CHECK_I(vrr.pipeline_full); + PIPE_CONF_CHECK_I(vrr.guardband); ++ PIPE_CONF_CHECK_I(vrr.vsync_start); ++ PIPE_CONF_CHECK_I(vrr.vsync_end); + } + + #undef PIPE_CONF_CHECK_X +diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h +index 1256730ea276..45b30d3ceb06 100644 +--- a/drivers/gpu/drm/i915/display/intel_display_types.h ++++ b/drivers/gpu/drm/i915/display/intel_display_types.h +@@ -1417,6 +1417,7 @@ struct intel_crtc_state { + bool enable, in_range; + u8 pipeline_full; + u16 flipline, vmin, vmax, guardband; ++ u32 vsync_end, vsync_start; + } vrr; + + /* Stream Splitter for eDP MSO */ +diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c +index 5d905f932cb4..d24a42902e69 100644 +--- a/drivers/gpu/drm/i915/display/intel_vrr.c ++++ b/drivers/gpu/drm/i915/display/intel_vrr.c +@@ -9,6 +9,7 @@ + #include "intel_de.h" + #include "intel_display_types.h" + #include "intel_vrr.h" ++#include "intel_dp.h" + + bool intel_vrr_is_capable(struct intel_connector *connector) + { +@@ -113,6 +114,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_connector *connector = + to_intel_connector(conn_state->connector); ++ struct intel_dp *intel_dp = intel_attached_dp(connector); + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + const struct drm_display_info *info = &connector->base.display_info; + int vmin, vmax; +@@ -165,6 +167,15 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, + if (crtc_state->uapi.vrr_enabled) { + crtc_state->vrr.enable = true; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; ++ ++ if (intel_dp_as_sdp_supported(intel_dp)) { ++ crtc_state->vrr.vsync_start = ++ (crtc_state->hw.adjusted_mode.crtc_vtotal - ++ VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start)); ++ crtc_state->vrr.vsync_end = ++ (crtc_state->hw.adjusted_mode.crtc_vtotal - ++ (VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16)); ++ } + } + } + +@@ -203,6 +214,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) + intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state)); + intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); ++ ++ if (crtc_state->vrr.vsync_end && crtc_state->vrr.vsync_start) ++ intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), ++ crtc_state->vrr.vsync_end << 16 | crtc_state->vrr.vsync_start); + } + + void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) +@@ -263,7 +278,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) + { + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; +- u32 trans_vrr_ctl; ++ u32 trans_vrr_ctl, trans_vrr_vsync; + + trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); + +@@ -283,6 +298,16 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) + crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; + } + +- if (crtc_state->vrr.enable) ++ if (crtc_state->vrr.enable) { + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; ++ ++ if (HAS_AS_SDP(dev_priv)) { ++ trans_vrr_vsync = ++ intel_de_read(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder)); ++ crtc_state->vrr.vsync_start = ++ trans_vrr_vsync & VRR_VSYNC_START_MASK; ++ crtc_state->vrr.vsync_end = ++ trans_vrr_vsync & VRR_VSYNC_START_MASK; ++ } ++ } + } +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +index dce276236707..53d8eb7ea1ea 100644 +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -2007,7 +2007,9 @@ + #define _TRANS_VRR_CTL_B 0x61420 + #define _TRANS_VRR_CTL_C 0x62420 + #define _TRANS_VRR_CTL_D 0x63420 ++#define _TRANS_VRR_VSYNC_A 0x60078 + #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) ++#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A) + #define VRR_CTL_VRR_ENABLE REG_BIT(31) + #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) + #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +@@ -2087,6 +2089,11 @@ + #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) + #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) + ++#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) ++#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) ++#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) ++#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) ++ + #define _TRANS_PUSH_A 0x60A70 + #define _TRANS_PUSH_B 0x61A70 + #define _TRANS_PUSH_C 0x62A70 + +From patchwork Thu Feb 29 16:39:57 2024 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v14,9/9] drm/i915/display: Read/Write AS sdp only when sink/source + has enabled +From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +X-Patchwork-Id: 580649 +Message-Id: <20240229163957.2948182-10-mitulkumar.ajitkumar.golani@intel.com> +To: intel-gfx@lists.freedesktop.org +Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, + ankit.k.nautiyal@intel.com, + Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +Date: Thu, 29 Feb 2024 22:09:57 +0530 + +Write/Read Adaptive sync SDP only when Sink and Source is enabled +for the same. Also along with write TRANS_VRR_VSYNC values. + +Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> +--- + drivers/gpu/drm/i915/display/intel_ddi.c | 1 + + drivers/gpu/drm/i915/display/intel_dp.c | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c +index bea441590204..6b8088321582 100644 +--- a/drivers/gpu/drm/i915/display/intel_ddi.c ++++ b/drivers/gpu/drm/i915/display/intel_ddi.c +@@ -3971,6 +3971,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, + + intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); + intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); ++ intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); + + intel_audio_codec_get_config(encoder, pipe_config); + } +diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c +index 86de854516ef..9309abeda241 100644 +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -4294,6 +4294,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, + return; + + intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); ++ intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); + + intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); + } diff --git a/a/content_digest b/N1/content_digest index 40bcd2a..7315710 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,7 +1,6 @@ - "ref\020240229163957.2948182-1-mitulkumar.ajitkumar.golani@intel.com\0" "From\0Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\0" - "Subject\0[PATCH v14 1/9] drm/dp: Add support to indicate if sink supports AS SDP\0" - "Date\0Thu, 29 Feb 2024 22:09:49 +0530\0" + "Subject\0[v14,1/9] drm/dp: Add support to indicate if sink supports AS SDP\0" + "Date\0Fri, 1 Mar 2024 14:13:45 +0530\0" "To\0intel-gfx@lists.freedesktop.org\0" "Cc\0dri-devel@lists.freedesktop.org" jani.nikula@intel.com @@ -69,7 +68,1003 @@ " \n" " int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);\n" " \n" - "-- \n" - 2.25.1 + "\n" + "From patchwork Thu Feb 29 16:39:50 2024\n" + "Content-Type: text/plain; charset=\"utf-8\"\n" + "MIME-Version: 1.0\n" + "Content-Transfer-Encoding: 7bit\n" + "Subject: [v14,2/9] drm: Add Adaptive Sync SDP logging\n" + "From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "X-Patchwork-Id: 580636\n" + "Message-Id: <20240229163957.2948182-3-mitulkumar.ajitkumar.golani@intel.com>\n" + "To: intel-gfx@lists.freedesktop.org\n" + "Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com,\n" + " ankit.k.nautiyal@intel.com,\n" + " Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "Date: Thu, 29 Feb 2024 22:09:50 +0530\n" + "\n" + "Add structure representing Adaptive Sync Secondary Data Packet (AS SDP).\n" + "Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate\n" + "debugging.\n" + "\n" + "--v2:\n" + "- Update logging. [Jani, Ankit]\n" + "- Use 'as_sdp' instead of 'async' [Ankit]\n" + "- Correct define placeholders to where they are actually used. [Jani]\n" + "- Update members in 'as_sdp' structure to make it uniform. [Jani]\n" + "\n" + "--v3:\n" + "- Added changes to dri-devel mailing list. No code changes.\n" + "\n" + "--v4:\n" + "- Instead of directly using operation mode, use an enum to accommodate\n" + "all operation modes (Ankit).\n" + "\n" + "--v5:\n" + "Nit-pick changes to commit message.\n" + "\n" + "--v6:\n" + "- Add correct place holder and name change for AS_SDP_OP_MODE.\n" + "- Separate i915 changes from drm changes.\n" + "- Remove extra lines.\n" + "\n" + "Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "---\n" + " drivers/gpu/drm/display/drm_dp_helper.c | 12 ++++++++++\n" + " include/drm/display/drm_dp.h | 10 +++++++++\n" + " include/drm/display/drm_dp_helper.h | 29 +++++++++++++++++++++++++\n" + " 3 files changed, 51 insertions(+)\n" + "\n" + "diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c\n" + "index f94c04db7187..b1459ac92aea 100644\n" + "--- a/drivers/gpu/drm/display/drm_dp_helper.c\n" + "+++ b/drivers/gpu/drm/display/drm_dp_helper.c\n" + "@@ -2913,6 +2913,18 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc)\n" + " }\n" + " EXPORT_SYMBOL(drm_dp_vsc_sdp_log);\n" + " \n" + "+void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp)\n" + "+{\n" + "+\tdrm_printf(p, \"DP SDP: AS_SDP, revision %u, length %u\\n\",\n" + "+\t\t as_sdp->revision, as_sdp->length);\n" + "+\tdrm_printf(p, \" vtotal: %d\\n\", as_sdp->vtotal);\n" + "+\tdrm_printf(p, \" target_rr: %d\\n\", as_sdp->target_rr);\n" + "+\tdrm_printf(p, \" duration_incr_ms: %d\\n\", as_sdp->duration_incr_ms);\n" + "+\tdrm_printf(p, \" duration_decr_ms: %d\\n\", as_sdp->duration_decr_ms);\n" + "+\tdrm_printf(p, \" operation_mode: %d\\n\", as_sdp->mode);\n" + "+}\n" + "+EXPORT_SYMBOL(drm_dp_as_sdp_log);\n" + "+\n" + " /**\n" + " * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported\n" + " * @aux: DisplayPort AUX channel\n" + "diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h\n" + "index 281afff6ee4e..ba388ad48ade 100644\n" + "--- a/include/drm/display/drm_dp.h\n" + "+++ b/include/drm/display/drm_dp.h\n" + "@@ -1149,6 +1149,7 @@\n" + " \n" + " #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */\n" + " # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0)\n" + "+# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE\t\tGENMASK(1, 0)\n" + " # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)\n" + " # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (1 << 4)\n" + " \n" + "@@ -1578,10 +1579,12 @@ enum drm_dp_phy {\n" + " #define DP_SDP_AUDIO_COPYMANAGEMENT\t0x05 /* DP 1.2 */\n" + " #define DP_SDP_ISRC\t\t\t0x06 /* DP 1.2 */\n" + " #define DP_SDP_VSC\t\t\t0x07 /* DP 1.2 */\n" + "+#define DP_SDP_ADAPTIVE_SYNC\t\t0x22 /* DP 1.4 */\n" + " #define DP_SDP_CAMERA_GENERIC(i)\t(0x08 + (i)) /* 0-7, DP 1.3 */\n" + " #define DP_SDP_PPS\t\t\t0x10 /* DP 1.4 */\n" + " #define DP_SDP_VSC_EXT_VESA\t\t0x20 /* DP 1.4 */\n" + " #define DP_SDP_VSC_EXT_CEA\t\t0x21 /* DP 1.4 */\n" + "+\n" + " /* 0x80+ CEA-861 infoframe types */\n" + " \n" + " #define DP_SDP_AUDIO_INFOFRAME_HB2\t0x1b\n" + "@@ -1737,4 +1740,11 @@ enum dp_content_type {\n" + " \tDP_CONTENT_TYPE_GAME = 0x04,\n" + " };\n" + " \n" + "+enum operation_mode {\n" + "+\tDP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,\n" + "+\tDP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,\n" + "+\tDP_AS_SDP_FAVT_TRR_NOT_REACHED = 0x02,\n" + "+\tDP_AS_SDP_FAVT_TRR_REACHED = 0x03\n" + "+};\n" + "+\n" + " #endif /* _DRM_DP_H_ */\n" + "diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h\n" + "index 7c1aa3a703c8..94eb0d92abae 100644\n" + "--- a/include/drm/display/drm_dp_helper.h\n" + "+++ b/include/drm/display/drm_dp_helper.h\n" + "@@ -98,6 +98,35 @@ struct drm_dp_vsc_sdp {\n" + " \tenum dp_content_type content_type;\n" + " };\n" + " \n" + "+/**\n" + "+ * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP\n" + "+ *\n" + "+ * This structure represents a DP AS SDP of drm\n" + "+ * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and\n" + "+ * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8]\n" + "+ *\n" + "+ * @sdp_type: Secondary-data packet type\n" + "+ * @revision: Revision Number\n" + "+ * @length: Number of valid data bytes\n" + "+ * @vtotal: Minimum Vertical Vtotal\n" + "+ * @target_rr: Target Refresh\n" + "+ * @duration_incr_ms: Successive frame duration increase\n" + "+ * @duration_decr_ms: Successive frame duration decrease\n" + "+ * @operation_mode: Adaptive Sync Operation Mode\n" + "+ */\n" + "+struct drm_dp_as_sdp {\n" + "+\tunsigned char sdp_type;\n" + "+\tunsigned char revision;\n" + "+\tunsigned char length;\n" + "+\tint vtotal;\n" + "+\tint target_rr;\n" + "+\tint duration_incr_ms;\n" + "+\tint duration_decr_ms;\n" + "+\tenum operation_mode mode;\n" + "+};\n" + "+\n" + "+void drm_dp_as_sdp_log(struct drm_printer *p,\n" + "+\t\t const struct drm_dp_as_sdp *as_sdp);\n" + " void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);\n" + " \n" + " bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);\n" + "\n" + "From patchwork Thu Feb 29 16:39:51 2024\n" + "Content-Type: text/plain; charset=\"utf-8\"\n" + "MIME-Version: 1.0\n" + "Content-Transfer-Encoding: 7bit\n" + "Subject: [v14,3/9] drm: Add crtc state dump for Adaptive Sync SDP\n" + "From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "X-Patchwork-Id: 580634\n" + "Message-Id: <20240229163957.2948182-4-mitulkumar.ajitkumar.golani@intel.com>\n" + "To: intel-gfx@lists.freedesktop.org\n" + "Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com,\n" + " ankit.k.nautiyal@intel.com,\n" + " Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "Date: Thu, 29 Feb 2024 22:09:51 +0530\n" + "\n" + "Add crtc state dump for Adaptive Sync SDP to know which\n" + "crtc specifically caused the failure.\n" + "\n" + "Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "---\n" + " .../gpu/drm/i915/display/intel_crtc_state_dump.c | 13 +++++++++++++\n" + " drivers/gpu/drm/i915/display/intel_display_types.h | 1 +\n" + " 2 files changed, 14 insertions(+)\n" + "\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c\n" + "index 4bcf446c75f4..1e4618271156 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c\n" + "@@ -51,6 +51,15 @@ intel_dump_infoframe(struct drm_i915_private *i915,\n" + " \thdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame);\n" + " }\n" + " \n" + "+static void\n" + "+intel_dump_dp_as_sdp(struct drm_i915_private *i915,\n" + "+\t\t const struct drm_dp_as_sdp *as_sdp)\n" + "+{\n" + "+\tstruct drm_printer p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, \"AS_SDP\");\n" + "+\n" + "+\tdrm_dp_as_sdp_log(&p, as_sdp);\n" + "+}\n" + "+\n" + " static void\n" + " intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,\n" + " \t\t const struct drm_dp_vsc_sdp *vsc)\n" + "@@ -302,6 +311,10 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,\n" + " \tif (pipe_config->infoframes.enable &\n" + " \t intel_hdmi_infoframe_enable(DP_SDP_VSC))\n" + " \t\tintel_dump_dp_vsc_sdp(i915, &pipe_config->infoframes.vsc);\n" + "+\tif (pipe_config->infoframes.enable &\n" + "+\t intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))\n" + "+\t\tintel_dump_dp_as_sdp(i915, &pipe_config->infoframes.as_sdp);\n" + "+\n" + " \n" + " \tif (pipe_config->has_audio)\n" + " \t\tintel_dump_buffer(i915, \"ELD: \", pipe_config->eld,\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h\n" + "index 8ce986fadd9a..1256730ea276 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_display_types.h\n" + "+++ b/drivers/gpu/drm/i915/display/intel_display_types.h\n" + "@@ -1335,6 +1335,7 @@ struct intel_crtc_state {\n" + " \t\tunion hdmi_infoframe hdmi;\n" + " \t\tunion hdmi_infoframe drm;\n" + " \t\tstruct drm_dp_vsc_sdp vsc;\n" + "+\t\tstruct drm_dp_as_sdp as_sdp;\n" + " \t} infoframes;\n" + " \n" + " \tu8 eld[MAX_ELD_BYTES];\n" + "\n" + "From patchwork Thu Feb 29 16:39:52 2024\n" + "Content-Type: text/plain; charset=\"utf-8\"\n" + "MIME-Version: 1.0\n" + "Content-Transfer-Encoding: 7bit\n" + "Subject: [v14,4/9] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP\n" + "From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "X-Patchwork-Id: 580637\n" + "Message-Id: <20240229163957.2948182-5-mitulkumar.ajitkumar.golani@intel.com>\n" + "To: intel-gfx@lists.freedesktop.org\n" + "Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com,\n" + " ankit.k.nautiyal@intel.com,\n" + " Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "Date: Thu, 29 Feb 2024 22:09:52 +0530\n" + "\n" + "Add the necessary structures and functions to handle reading and\n" + "unpacking Adaptive Sync Secondary Data Packets. Also add support\n" + "to write and pack AS SDP.\n" + "\n" + "--v2:\n" + "- Correct use of REG_BIT and REG_GENMASK. [Jani]\n" + "- Use as_sdp instead of async. [Jani]\n" + "- Remove unrelated comments and changes. [Jani]\n" + "- Correct code indent. [Jani]\n" + "\n" + "--v3:\n" + "- Update definition names for AS SDP which are starting from\n" + "HSW, as these defines are applicable for ADLP+.(Ankit)\n" + "\n" + "--v4:\n" + "- Remove as_sdp_mode from crtc_state.\n" + "- Drop metadata keyword.\n" + "- For consistency, update ADL_ prefix or post fix as required.\n" + "\n" + "--v5:\n" + "- Check if AS_SDP bit is set in crtc_state->infoframes.enable. If not\n" + " return.\n" + "- Check for HAS_AS_SDP() before setting VIDEO_DIP_ENABLE_AS_ADL mask.\n" + "Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "---\n" + " .../drm/i915/display/intel_display_device.h | 1 +\n" + " drivers/gpu/drm/i915/display/intel_dp.c | 91 +++++++++++++++++++\n" + " drivers/gpu/drm/i915/display/intel_hdmi.c | 12 ++-\n" + " drivers/gpu/drm/i915/i915_reg.h | 8 ++\n" + " include/drm/display/drm_dp_helper.h | 2 +-\n" + " 5 files changed, 112 insertions(+), 2 deletions(-)\n" + "\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h\n" + "index fe4268813786..6399fbc6c738 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_display_device.h\n" + "+++ b/drivers/gpu/drm/i915/display/intel_display_device.h\n" + "@@ -68,6 +68,7 @@ struct drm_printer;\n" + " #define HAS_TRANSCODER(i915, trans)\t((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \\\n" + " \t\t\t\t\t BIT(trans)) != 0)\n" + " #define HAS_VRR(i915)\t\t\t(DISPLAY_VER(i915) >= 11)\n" + "+#define HAS_AS_SDP(i915)\t\t(DISPLAY_VER(i915) >= 13)\n" + " #define INTEL_NUM_PIPES(i915)\t\t(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))\n" + " #define I915_HAS_HOTPLUG(i915)\t\t(DISPLAY_INFO(i915)->has_hotplug)\n" + " #define OVERLAY_NEEDS_PHYSICAL(i915)\t(DISPLAY_INFO(i915)->overlay_needs_physical)\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "index e13121dc3a03..7cf849015797 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_dp.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "@@ -4089,6 +4089,32 @@ intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,\n" + " \treturn false;\n" + " }\n" + " \n" + "+static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,\n" + "+\t\t\t\t struct dp_sdp *sdp, size_t size)\n" + "+{\n" + "+\tsize_t length = sizeof(struct dp_sdp);\n" + "+\n" + "+\tif (size < length)\n" + "+\t\treturn -ENOSPC;\n" + "+\n" + "+\tmemset(sdp, 0, size);\n" + "+\n" + "+\t/* Prepare AS (Adaptive Sync) SDP Header */\n" + "+\tsdp->sdp_header.HB0 = 0;\n" + "+\tsdp->sdp_header.HB1 = as_sdp->sdp_type;\n" + "+\tsdp->sdp_header.HB2 = 0x02;\n" + "+\tsdp->sdp_header.HB3 = as_sdp->length;\n" + "+\n" + "+\t/* Fill AS (Adaptive Sync) SDP Payload */\n" + "+\tsdp->db[0] = as_sdp->mode;\n" + "+\tsdp->db[1] = as_sdp->vtotal & 0xFF;\n" + "+\tsdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;\n" + "+\tsdp->db[3] = as_sdp->target_rr;\n" + "+\tsdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;\n" + "+\n" + "+\treturn length;\n" + "+}\n" + "+\n" + " static ssize_t\n" + " intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,\n" + " \t\t\t\t\t const struct hdmi_drm_infoframe *drm_infoframe,\n" + "@@ -4188,6 +4214,10 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder,\n" + " \t\t\t\t\t\t\t &crtc_state->infoframes.drm.drm,\n" + " \t\t\t\t\t\t\t &sdp, sizeof(sdp));\n" + " \t\tbreak;\n" + "+\tcase DP_SDP_ADAPTIVE_SYNC:\n" + "+\t\tlen = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,\n" + "+\t\t\t\t\t sizeof(sdp));\n" + "+\t\tbreak;\n" + " \tdefault:\n" + " \t\tMISSING_CASE(type);\n" + " \t\treturn;\n" + "@@ -4209,6 +4239,10 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,\n" + " \tu32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |\n" + " \t\t\t VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |\n" + " \t\t\t VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;\n" + "+\n" + "+\tif (HAS_AS_SDP(dev_priv))\n" + "+\t\tdip_enable |= VIDEO_DIP_ENABLE_AS_ADL;\n" + "+\n" + " \tu32 val = intel_de_read(dev_priv, reg) & ~dip_enable;\n" + " \n" + " \t/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */\n" + "@@ -4230,6 +4264,36 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,\n" + " \tintel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);\n" + " }\n" + " \n" + "+static\n" + "+int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,\n" + "+\t\t\t const void *buffer, size_t size)\n" + "+{\n" + "+\tconst struct dp_sdp *sdp = buffer;\n" + "+\n" + "+\tif (size < sizeof(struct dp_sdp))\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tmemset(as_sdp, 0, sizeof(*as_sdp));\n" + "+\n" + "+\tif (sdp->sdp_header.HB0 != 0)\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tif (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tif (sdp->sdp_header.HB2 != 0x02)\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tif ((sdp->sdp_header.HB3 & 0x3F) != 9)\n" + "+\t\treturn -EINVAL;\n" + "+\n" + "+\tas_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;\n" + "+\tas_sdp->vtotal = ((u64)sdp->db[2] << 32) | (u64)sdp->db[1];\n" + "+\tas_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);\n" + "+\n" + "+\treturn 0;\n" + "+}\n" + "+\n" + " static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,\n" + " \t\t\t\t const void *buffer, size_t size)\n" + " {\n" + "@@ -4300,6 +4364,29 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,\n" + " \treturn 0;\n" + " }\n" + " \n" + "+static void\n" + "+intel_read_dp_infoframe_as_sdp(struct intel_encoder *encoder,\n" + "+\t\t\t struct intel_crtc_state *crtc_state,\n" + "+\t\t\t struct drm_dp_as_sdp *as_sdp)\n" + "+{\n" + "+\tstruct intel_digital_port *dig_port = enc_to_dig_port(encoder);\n" + "+\tstruct drm_i915_private *dev_priv = to_i915(encoder->base.dev);\n" + "+\tunsigned int type = DP_SDP_ADAPTIVE_SYNC;\n" + "+\tstruct dp_sdp sdp = {};\n" + "+\tint ret;\n" + "+\n" + "+\tif ((crtc_state->infoframes.enable &\n" + "+\t intel_hdmi_infoframe_enable(type)) == 0)\n" + "+\t\treturn;\n" + "+\n" + "+\tdig_port->read_infoframe(encoder, crtc_state, type, &sdp,\n" + "+\t\t\t\t sizeof(sdp));\n" + "+\n" + "+\tret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));\n" + "+\tif (ret)\n" + "+\t\tdrm_dbg_kms(&dev_priv->drm, \"Failed to unpack DP AS SDP\\n\");\n" + "+}\n" + "+\n" + " static int\n" + " intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,\n" + " \t\t\t\t\t const void *buffer, size_t size)\n" + "@@ -4406,6 +4493,10 @@ void intel_read_dp_sdp(struct intel_encoder *encoder,\n" + " \t\tintel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,\n" + " \t\t\t\t\t\t\t &crtc_state->infoframes.drm.drm);\n" + " \t\tbreak;\n" + "+\tcase DP_SDP_ADAPTIVE_SYNC:\n" + "+\t\tintel_read_dp_infoframe_as_sdp(encoder, crtc_state,\n" + "+\t\t\t\t\t &crtc_state->infoframes.as_sdp);\n" + "+\t\tbreak;\n" + " \tdefault:\n" + " \t\tMISSING_CASE(type);\n" + " \t\tbreak;\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c\n" + "index 90d2236fede3..fb134bf64dae 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_hdmi.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c\n" + "@@ -137,6 +137,8 @@ static u32 hsw_infoframe_enable(unsigned int type)\n" + " \t\treturn VIDEO_DIP_ENABLE_GMP_HSW;\n" + " \tcase DP_SDP_VSC:\n" + " \t\treturn VIDEO_DIP_ENABLE_VSC_HSW;\n" + "+\tcase DP_SDP_ADAPTIVE_SYNC:\n" + "+\t\treturn VIDEO_DIP_ENABLE_AS_ADL;\n" + " \tcase DP_SDP_PPS:\n" + " \t\treturn VDIP_ENABLE_PPS;\n" + " \tcase HDMI_INFOFRAME_TYPE_AVI:\n" + "@@ -164,6 +166,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,\n" + " \t\treturn HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);\n" + " \tcase DP_SDP_VSC:\n" + " \t\treturn HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);\n" + "+\tcase DP_SDP_ADAPTIVE_SYNC:\n" + "+\t\treturn ADL_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i);\n" + " \tcase DP_SDP_PPS:\n" + " \t\treturn ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);\n" + " \tcase HDMI_INFOFRAME_TYPE_AVI:\n" + "@@ -186,6 +190,8 @@ static int hsw_dip_data_size(struct drm_i915_private *dev_priv,\n" + " \tswitch (type) {\n" + " \tcase DP_SDP_VSC:\n" + " \t\treturn VIDEO_DIP_VSC_DATA_SIZE;\n" + "+\tcase DP_SDP_ADAPTIVE_SYNC:\n" + "+\t\treturn VIDEO_DIP_ASYNC_DATA_SIZE;\n" + " \tcase DP_SDP_PPS:\n" + " \t\treturn VIDEO_DIP_PPS_DATA_SIZE;\n" + " \tcase HDMI_PACKET_TYPE_GAMUT_METADATA:\n" + "@@ -563,6 +569,9 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,\n" + " \tif (DISPLAY_VER(dev_priv) >= 10)\n" + " \t\tmask |= VIDEO_DIP_ENABLE_DRM_GLK;\n" + " \n" + "+\tif (HAS_AS_SDP(dev_priv))\n" + "+\t\tmask |= VIDEO_DIP_ENABLE_AS_ADL;\n" + "+\n" + " \treturn val & mask;\n" + " }\n" + " \n" + "@@ -570,6 +579,7 @@ static const u8 infoframe_type_to_idx[] = {\n" + " \tHDMI_PACKET_TYPE_GENERAL_CONTROL,\n" + " \tHDMI_PACKET_TYPE_GAMUT_METADATA,\n" + " \tDP_SDP_VSC,\n" + "+\tDP_SDP_ADAPTIVE_SYNC,\n" + " \tHDMI_INFOFRAME_TYPE_AVI,\n" + " \tHDMI_INFOFRAME_TYPE_SPD,\n" + " \tHDMI_INFOFRAME_TYPE_VENDOR,\n" + "@@ -1212,7 +1222,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder,\n" + " \tval &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |\n" + " \t\t VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |\n" + " \t\t VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |\n" + "-\t\t VIDEO_DIP_ENABLE_DRM_GLK);\n" + "+\t\t VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL);\n" + " \n" + " \tif (!enable) {\n" + " \t\tintel_de_write(dev_priv, reg, val);\n" + "diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h\n" + "index e00557e1a57f..dce276236707 100644\n" + "--- a/drivers/gpu/drm/i915/i915_reg.h\n" + "+++ b/drivers/gpu/drm/i915/i915_reg.h\n" + "@@ -2312,6 +2312,7 @@\n" + " * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte\n" + " * of the infoframe structure specified by CEA-861. */\n" + " #define VIDEO_DIP_DATA_SIZE\t32\n" + "+#define VIDEO_DIP_ASYNC_DATA_SIZE\t36\n" + " #define VIDEO_DIP_GMP_DATA_SIZE\t36\n" + " #define VIDEO_DIP_VSC_DATA_SIZE\t36\n" + " #define VIDEO_DIP_PPS_DATA_SIZE\t132\n" + "@@ -2350,6 +2351,8 @@\n" + " #define VIDEO_DIP_ENABLE_VS_HSW\t(1 << 8)\n" + " #define VIDEO_DIP_ENABLE_GMP_HSW\t(1 << 4)\n" + " #define VIDEO_DIP_ENABLE_SPD_HSW\t(1 << 0)\n" + "+/* ADL and later: */\n" + "+#define VIDEO_DIP_ENABLE_AS_ADL\tREG_BIT(23)\n" + " \n" + " /* Panel fitting */\n" + " #define PFIT_CONTROL\t_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)\n" + "@@ -5040,6 +5043,7 @@\n" + " #define _HSW_VIDEO_DIP_SPD_DATA_A\t0x602A0\n" + " #define _HSW_VIDEO_DIP_GMP_DATA_A\t0x602E0\n" + " #define _HSW_VIDEO_DIP_VSC_DATA_A\t0x60320\n" + "+#define\t_ADL_VIDEO_DIP_AS_DATA_A\t0x60484\n" + " #define _GLK_VIDEO_DIP_DRM_DATA_A\t0x60440\n" + " #define _HSW_VIDEO_DIP_AVI_ECC_A\t0x60240\n" + " #define _HSW_VIDEO_DIP_VS_ECC_A\t\t0x60280\n" + "@@ -5054,6 +5058,7 @@\n" + " #define _HSW_VIDEO_DIP_SPD_DATA_B\t0x612A0\n" + " #define _HSW_VIDEO_DIP_GMP_DATA_B\t0x612E0\n" + " #define _HSW_VIDEO_DIP_VSC_DATA_B\t0x61320\n" + "+#define _ADL_VIDEO_DIP_AS_DATA_B\t0x61484\n" + " #define _GLK_VIDEO_DIP_DRM_DATA_B\t0x61440\n" + " #define _HSW_VIDEO_DIP_BVI_ECC_B\t0x61240\n" + " #define _HSW_VIDEO_DIP_VS_ECC_B\t\t0x61280\n" + "@@ -5083,6 +5088,9 @@\n" + " #define GLK_TVIDEO_DIP_DRM_DATA(trans, i)\t_MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)\n" + " #define ICL_VIDEO_DIP_PPS_DATA(trans, i)\t_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)\n" + " #define ICL_VIDEO_DIP_PPS_ECC(trans, i)\t\t_MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)\n" + "+/*ADLP and later: */\n" + "+#define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i)\t_MMIO_TRANS2(trans,\\\n" + "+\t\t\t\t\t\t\t _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)\n" + " \n" + " #define _HSW_STEREO_3D_CTL_A\t\t0x70020\n" + " #define S3D_ENABLE\t\t\t(1 << 31)\n" + "diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h\n" + "index 94eb0d92abae..3f6003656e3d 100644\n" + "--- a/include/drm/display/drm_dp_helper.h\n" + "+++ b/include/drm/display/drm_dp_helper.h\n" + "@@ -130,8 +130,8 @@ void drm_dp_as_sdp_log(struct drm_printer *p,\n" + " void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);\n" + " \n" + " bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);\n" + "-bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);\n" + " \n" + "+bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);\n" + " int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);\n" + " \n" + " static inline int\n" + "\n" + "From patchwork Thu Feb 29 16:39:53 2024\n" + "Content-Type: text/plain; charset=\"utf-8\"\n" + "MIME-Version: 1.0\n" + "Content-Transfer-Encoding: 7bit\n" + "Subject: [v14,5/9] drm/i915/dp: Add wrapper function to check AS SDP\n" + "From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "X-Patchwork-Id: 580643\n" + "Message-Id: <20240229163957.2948182-6-mitulkumar.ajitkumar.golani@intel.com>\n" + "To: intel-gfx@lists.freedesktop.org\n" + "Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com,\n" + " ankit.k.nautiyal@intel.com,\n" + " Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "Date: Thu, 29 Feb 2024 22:09:53 +0530\n" + "\n" + "Add a wrapper function to check if both the source and\n" + "sink support Adaptive Sync SDP.\n" + "\n" + "--v1:\n" + "Just use drm/i915/dp in subject line.\n" + "\n" + "Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "---\n" + " drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++\n" + " drivers/gpu/drm/i915/display/intel_dp.h | 1 +\n" + " 2 files changed, 9 insertions(+)\n" + "\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "index 7cf849015797..b26efce4a041 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_dp.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "@@ -120,6 +120,14 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)\n" + " \treturn dig_port->base.type == INTEL_OUTPUT_EDP;\n" + " }\n" + " \n" + "+bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp)\n" + "+{\n" + "+\tstruct drm_i915_private *i915 = dp_to_i915(intel_dp);\n" + "+\n" + "+\treturn HAS_AS_SDP(i915) &&\n" + "+\t\tdrm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);\n" + "+}\n" + "+\n" + " static void intel_dp_unset_edid(struct intel_dp *intel_dp);\n" + " \n" + " /* Is link rate UHBR and thus 128b/132b? */\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h\n" + "index 530cc97bc42f..cc5e069091ff 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_dp.h\n" + "+++ b/drivers/gpu/drm/i915/display/intel_dp.h\n" + "@@ -80,6 +80,7 @@ void intel_dp_audio_compute_config(struct intel_encoder *encoder,\n" + " \t\t\t\t struct drm_connector_state *conn_state);\n" + " bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);\n" + " bool intel_dp_is_edp(struct intel_dp *intel_dp);\n" + "+bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp);\n" + " bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);\n" + " int intel_dp_link_symbol_size(int rate);\n" + " int intel_dp_link_symbol_clock(int rate);\n" + "\n" + "From patchwork Thu Feb 29 16:39:54 2024\n" + "Content-Type: text/plain; charset=\"utf-8\"\n" + "MIME-Version: 1.0\n" + "Content-Transfer-Encoding: 7bit\n" + "Subject: [v14,6/9] drm/i915/display: Compute AS SDP parameters\n" + "From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "X-Patchwork-Id: 580646\n" + "Message-Id: <20240229163957.2948182-7-mitulkumar.ajitkumar.golani@intel.com>\n" + "To: intel-gfx@lists.freedesktop.org\n" + "Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com,\n" + " ankit.k.nautiyal@intel.com,\n" + " Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "Date: Thu, 29 Feb 2024 22:09:54 +0530\n" + "\n" + "Add necessary function definitions to compute AS SDP data.\n" + "The new intel_dp_compute_as_sdp function computes AS SDP\n" + "values based on the display configuration, ensuring proper\n" + "handling of Variable Refresh Rate (VRR).\n" + "\n" + "--v2:\n" + "- Added DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx(). [Ankit]\n" + "- Separated patch for intel_read/write_dp_sdp. [Ankit]\n" + "- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward. [Ankit]\n" + "- Fixed indentation issues. [Ankit]\n" + "\n" + "--v3:\n" + "- Added VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.\n" + "\n" + "--v4:\n" + "- Added HAS_VRR check before writing AS SDP.\n" + "\n" + "--v5:\n" + "Added missed HAS_VRR check before reading AS SDP.\n" + "\n" + "--v6:\n" + "- Used Adaptive Sync sink status as a check for read/write SDP. (Ankit)\n" + "\n" + "--v7:\n" + "- Remove as_sdp_enable from crtc_state.\n" + "- Add a comment mentioning current support of\n" + " DP_AS_SDP_AVT_FIXED_VTOTAL.\n" + "- Add state checker for AS_SDP infoframe enable.\n" + "\n" + "--v8:\n" + "- Drop conn_state from intel_dp_compute_as_sdp, as not used.\n" + "- Remove fullstop in subject line.\n" + "Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>\n" + "---\n" + " drivers/gpu/drm/i915/display/intel_dp.c | 26 +++++++++++++++++++++++++\n" + " 1 file changed, 26 insertions(+)\n" + "\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "index b26efce4a041..86de854516ef 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_dp.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "@@ -2626,6 +2626,31 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc\n" + " \tvsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;\n" + " }\n" + " \n" + "+static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,\n" + "+\t\t\t\t struct intel_crtc_state *crtc_state)\n" + "+{\n" + "+\tstruct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;\n" + "+\tstruct intel_connector *connector = intel_dp->attached_connector;\n" + "+\tconst struct drm_display_mode *adjusted_mode =\n" + "+\t\t&crtc_state->hw.adjusted_mode;\n" + "+\tint vrefresh = drm_mode_vrefresh(adjusted_mode);\n" + "+\n" + "+\tif (!intel_vrr_is_in_range(connector, vrefresh) ||\n" + "+\t !intel_dp_as_sdp_supported(intel_dp))\n" + "+\t\treturn;\n" + "+\n" + "+\tcrtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);\n" + "+\n" + "+\t/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */\n" + "+\tas_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;\n" + "+\tas_sdp->length = 0x9;\n" + "+\tas_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;\n" + "+\tas_sdp->vtotal = adjusted_mode->vtotal;\n" + "+\tas_sdp->target_rr = 0;\n" + "+\tas_sdp->duration_incr_ms = 0;\n" + "+\tas_sdp->duration_incr_ms = 0;\n" + "+}\n" + "+\n" + " static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,\n" + " \t\t\t\t struct intel_crtc_state *crtc_state,\n" + " \t\t\t\t const struct drm_connector_state *conn_state)\n" + "@@ -2951,6 +2976,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,\n" + " \t\tg4x_dp_set_clock(encoder, pipe_config);\n" + " \n" + " \tintel_vrr_compute_config(pipe_config, conn_state);\n" + "+\tintel_dp_compute_as_sdp(intel_dp, pipe_config);\n" + " \tintel_psr_compute_config(intel_dp, pipe_config, conn_state);\n" + " \tintel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);\n" + " \tintel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);\n" + "\n" + "From patchwork Thu Feb 29 16:39:55 2024\n" + "Content-Type: text/plain; charset=\"utf-8\"\n" + "MIME-Version: 1.0\n" + "Content-Transfer-Encoding: 7bit\n" + "Subject: [v14,7/9] drm/i915/display: Add state checker for Adaptive Sync SDP\n" + "From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "X-Patchwork-Id: 580645\n" + "Message-Id: <20240229163957.2948182-8-mitulkumar.ajitkumar.golani@intel.com>\n" + "To: intel-gfx@lists.freedesktop.org\n" + "Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com,\n" + " ankit.k.nautiyal@intel.com,\n" + " Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "Date: Thu, 29 Feb 2024 22:09:55 +0530\n" + "\n" + "Enable infoframe and add state checker for Adaptive Sync\n" + "SDP enablement.\n" + "\n" + "--v1:\n" + "- crtc_state->infoframes.enable, to add on correct place holder.\n" + "\n" + "Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "---\n" + " drivers/gpu/drm/i915/display/intel_display.c | 46 ++++++++++++++++++++\n" + " 1 file changed, 46 insertions(+)\n" + "\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c\n" + "index 00ac65a14029..be0a5fae4e58 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_display.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_display.c\n" + "@@ -4781,6 +4781,17 @@ intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,\n" + " \t\ta->content_type == b->content_type;\n" + " }\n" + " \n" + "+static bool\n" + "+intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,\n" + "+\t\t\tconst struct drm_dp_as_sdp *b)\n" + "+{\n" + "+\treturn a->vtotal == b->vtotal &&\n" + "+\t\ta->target_rr == b->target_rr &&\n" + "+\t\ta->duration_incr_ms == b->duration_incr_ms &&\n" + "+\t\ta->duration_decr_ms == b->duration_decr_ms &&\n" + "+\t\ta->mode == b->mode;\n" + "+}\n" + "+\n" + " static bool\n" + " intel_compare_buffer(const u8 *a, const u8 *b, size_t len)\n" + " {\n" + "@@ -4836,6 +4847,30 @@ pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *i915,\n" + " \tdrm_dp_vsc_sdp_log(&p, b);\n" + " }\n" + " \n" + "+static void\n" + "+pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915,\n" + "+\t\t\t bool fastset, const char *name,\n" + "+\t\t\t const struct drm_dp_as_sdp *a,\n" + "+\t\t\t const struct drm_dp_as_sdp *b)\n" + "+{\n" + "+\tstruct drm_printer p;\n" + "+\n" + "+\tif (fastset) {\n" + "+\t\tp = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL);\n" + "+\n" + "+\t\tdrm_printf(&p, \"fastset requirement not met in %s dp sdp\\n\", name);\n" + "+\t} else {\n" + "+\t\tp = drm_err_printer(&i915->drm, NULL);\n" + "+\n" + "+\t\tdrm_printf(&p, \"mismatch in %s dp sdp\\n\", name);\n" + "+\t}\n" + "+\n" + "+\tdrm_printf(&p, \"expected:\\n\");\n" + "+\tdrm_dp_as_sdp_log(&p, a);\n" + "+\tdrm_printf(&p, \"found:\\n\");\n" + "+\tdrm_dp_as_sdp_log(&p, b);\n" + "+}\n" + "+\n" + " /* Returns the length up to and including the last differing byte */\n" + " static size_t\n" + " memcmp_diff_len(const u8 *a, const u8 *b, size_t len)\n" + "@@ -5089,6 +5124,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,\n" + " \t} \\\n" + " } while (0)\n" + " \n" + "+#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \\\n" + "+\tif (!intel_compare_dp_as_sdp(¤t_config->infoframes.name, \\\n" + "+\t\t\t\t &pipe_config->infoframes.name)) { \\\n" + "+\t\tpipe_config_dp_as_sdp_mismatch(dev_priv, fastset, __stringify(name), \\\n" + "+\t\t\t\t\t\t¤t_config->infoframes.name, \\\n" + "+\t\t\t\t\t\t&pipe_config->infoframes.name); \\\n" + "+\t\tret = false; \\\n" + "+\t} \\\n" + "+} while (0)\n" + "+\n" + " #define PIPE_CONF_CHECK_BUFFER(name, len) do { \\\n" + " \tBUILD_BUG_ON(sizeof(current_config->name) != (len)); \\\n" + " \tBUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \\\n" + "@@ -5270,6 +5315,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,\n" + " \tPIPE_CONF_CHECK_INFOFRAME(hdmi);\n" + " \tPIPE_CONF_CHECK_INFOFRAME(drm);\n" + " \tPIPE_CONF_CHECK_DP_VSC_SDP(vsc);\n" + "+\tPIPE_CONF_CHECK_DP_AS_SDP(as_sdp);\n" + " \n" + " \tPIPE_CONF_CHECK_X(sync_mode_slaves_mask);\n" + " \tPIPE_CONF_CHECK_I(master_transcoder);\n" + "\n" + "From patchwork Thu Feb 29 16:39:56 2024\n" + "Content-Type: text/plain; charset=\"utf-8\"\n" + "MIME-Version: 1.0\n" + "Content-Transfer-Encoding: 7bit\n" + "Subject: [v14,8/9] drm/i915/display: Compute vrr_vsync params\n" + "From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "X-Patchwork-Id: 580642\n" + "Message-Id: <20240229163957.2948182-9-mitulkumar.ajitkumar.golani@intel.com>\n" + "To: intel-gfx@lists.freedesktop.org\n" + "Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com,\n" + " ankit.k.nautiyal@intel.com,\n" + " Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "Date: Thu, 29 Feb 2024 22:09:56 +0530\n" + "\n" + "Compute vrr_vsync_start/end, which sets the position\n" + "for hardware to send the Vsync at a fixed position\n" + "relative to the end of the Vblank.\n" + "\n" + "--v2:\n" + "- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)\n" + "- Updated bit fields of VRR_VSYNC_START/END. (Ankit)\n" + "\n" + "--v3:\n" + "- Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).\n" + "- Read/write vrr_vsync params only when we intend to send\n" + "adaptive_sync sdp.\n" + "\n" + "Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "---\n" + " drivers/gpu/drm/i915/display/intel_display.c | 2 ++\n" + " .../drm/i915/display/intel_display_types.h | 1 +\n" + " drivers/gpu/drm/i915/display/intel_vrr.c | 29 +++++++++++++++++--\n" + " drivers/gpu/drm/i915/i915_reg.h | 7 +++++\n" + " 4 files changed, 37 insertions(+), 2 deletions(-)\n" + "\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c\n" + "index be0a5fae4e58..c523eec4d626 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_display.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_display.c\n" + "@@ -5367,6 +5367,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,\n" + " \t\tPIPE_CONF_CHECK_I(vrr.flipline);\n" + " \t\tPIPE_CONF_CHECK_I(vrr.pipeline_full);\n" + " \t\tPIPE_CONF_CHECK_I(vrr.guardband);\n" + "+\t\tPIPE_CONF_CHECK_I(vrr.vsync_start);\n" + "+\t\tPIPE_CONF_CHECK_I(vrr.vsync_end);\n" + " \t}\n" + " \n" + " #undef PIPE_CONF_CHECK_X\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h\n" + "index 1256730ea276..45b30d3ceb06 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_display_types.h\n" + "+++ b/drivers/gpu/drm/i915/display/intel_display_types.h\n" + "@@ -1417,6 +1417,7 @@ struct intel_crtc_state {\n" + " \t\tbool enable, in_range;\n" + " \t\tu8 pipeline_full;\n" + " \t\tu16 flipline, vmin, vmax, guardband;\n" + "+\t\tu32 vsync_end, vsync_start;\n" + " \t} vrr;\n" + " \n" + " \t/* Stream Splitter for eDP MSO */\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c\n" + "index 5d905f932cb4..d24a42902e69 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_vrr.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_vrr.c\n" + "@@ -9,6 +9,7 @@\n" + " #include \"intel_de.h\"\n" + " #include \"intel_display_types.h\"\n" + " #include \"intel_vrr.h\"\n" + "+#include \"intel_dp.h\"\n" + " \n" + " bool intel_vrr_is_capable(struct intel_connector *connector)\n" + " {\n" + "@@ -113,6 +114,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,\n" + " \tstruct drm_i915_private *i915 = to_i915(crtc->base.dev);\n" + " \tstruct intel_connector *connector =\n" + " \t\tto_intel_connector(conn_state->connector);\n" + "+\tstruct intel_dp *intel_dp = intel_attached_dp(connector);\n" + " \tstruct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;\n" + " \tconst struct drm_display_info *info = &connector->base.display_info;\n" + " \tint vmin, vmax;\n" + "@@ -165,6 +167,15 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,\n" + " \tif (crtc_state->uapi.vrr_enabled) {\n" + " \t\tcrtc_state->vrr.enable = true;\n" + " \t\tcrtc_state->mode_flags |= I915_MODE_FLAG_VRR;\n" + "+\n" + "+\t\tif (intel_dp_as_sdp_supported(intel_dp)) {\n" + "+\t\t\tcrtc_state->vrr.vsync_start =\n" + "+\t\t\t\t(crtc_state->hw.adjusted_mode.crtc_vtotal -\n" + "+\t\t\t\tVRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start));\n" + "+\t\t\tcrtc_state->vrr.vsync_end =\n" + "+\t\t\t\t(crtc_state->hw.adjusted_mode.crtc_vtotal -\n" + "+\t\t\t\t(VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16));\n" + "+\t\t}\n" + " \t}\n" + " }\n" + " \n" + "@@ -203,6 +214,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)\n" + " \tintel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);\n" + " \tintel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));\n" + " \tintel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);\n" + "+\n" + "+\tif (crtc_state->vrr.vsync_end && crtc_state->vrr.vsync_start)\n" + "+\t\tintel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),\n" + "+\t\t\t crtc_state->vrr.vsync_end << 16 | crtc_state->vrr.vsync_start);\n" + " }\n" + " \n" + " void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)\n" + "@@ -263,7 +278,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)\n" + " {\n" + " \tstruct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);\n" + " \tenum transcoder cpu_transcoder = crtc_state->cpu_transcoder;\n" + "-\tu32 trans_vrr_ctl;\n" + "+\tu32 trans_vrr_ctl, trans_vrr_vsync;\n" + " \n" + " \ttrans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));\n" + " \n" + "@@ -283,6 +298,16 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)\n" + " \t\tcrtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;\n" + " \t}\n" + " \n" + "-\tif (crtc_state->vrr.enable)\n" + "+\tif (crtc_state->vrr.enable) {\n" + " \t\tcrtc_state->mode_flags |= I915_MODE_FLAG_VRR;\n" + "+\n" + "+\t\tif (HAS_AS_SDP(dev_priv)) {\n" + "+\t\t\ttrans_vrr_vsync =\n" + "+\t\t\t\tintel_de_read(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder));\n" + "+\t\t\tcrtc_state->vrr.vsync_start =\n" + "+\t\t\t\ttrans_vrr_vsync & VRR_VSYNC_START_MASK;\n" + "+\t\t\tcrtc_state->vrr.vsync_end =\n" + "+\t\t\t\ttrans_vrr_vsync & VRR_VSYNC_START_MASK;\n" + "+\t\t}\n" + "+\t}\n" + " }\n" + "diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h\n" + "index dce276236707..53d8eb7ea1ea 100644\n" + "--- a/drivers/gpu/drm/i915/i915_reg.h\n" + "+++ b/drivers/gpu/drm/i915/i915_reg.h\n" + "@@ -2007,7 +2007,9 @@\n" + " #define _TRANS_VRR_CTL_B\t\t0x61420\n" + " #define _TRANS_VRR_CTL_C\t\t0x62420\n" + " #define _TRANS_VRR_CTL_D\t\t0x63420\n" + "+#define _TRANS_VRR_VSYNC_A\t\t0x60078\n" + " #define TRANS_VRR_CTL(trans)\t\t\t_MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)\n" + "+#define TRANS_VRR_VSYNC(trans)\t\t\t_MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A)\n" + " #define VRR_CTL_VRR_ENABLE\t\t\tREG_BIT(31)\n" + " #define VRR_CTL_IGN_MAX_SHIFT\t\t\tREG_BIT(30)\n" + " #define VRR_CTL_FLIP_LINE_EN\t\t\tREG_BIT(29)\n" + "@@ -2087,6 +2089,11 @@\n" + " #define TRANS_VRR_STATUS2(trans)\t_MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)\n" + " #define VRR_STATUS2_VERT_LN_CNT_MASK\tREG_GENMASK(19, 0)\n" + " \n" + "+#define VRR_VSYNC_END_MASK\t\tREG_GENMASK(28, 16)\n" + "+#define VRR_VSYNC_END(vsync_end)\tREG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))\n" + "+#define VRR_VSYNC_START_MASK\t\tREG_GENMASK(12, 0)\n" + "+#define VRR_VSYNC_START(vsync_start)\tREG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))\n" + "+\n" + " #define _TRANS_PUSH_A\t\t\t0x60A70\n" + " #define _TRANS_PUSH_B\t\t\t0x61A70\n" + " #define _TRANS_PUSH_C\t\t\t0x62A70\n" + "\n" + "From patchwork Thu Feb 29 16:39:57 2024\n" + "Content-Type: text/plain; charset=\"utf-8\"\n" + "MIME-Version: 1.0\n" + "Content-Transfer-Encoding: 7bit\n" + "Subject: [v14,9/9] drm/i915/display: Read/Write AS sdp only when sink/source\n" + " has enabled\n" + "From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "X-Patchwork-Id: 580649\n" + "Message-Id: <20240229163957.2948182-10-mitulkumar.ajitkumar.golani@intel.com>\n" + "To: intel-gfx@lists.freedesktop.org\n" + "Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com,\n" + " ankit.k.nautiyal@intel.com,\n" + " Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "Date: Thu, 29 Feb 2024 22:09:57 +0530\n" + "\n" + "Write/Read Adaptive sync SDP only when Sink and Source is enabled\n" + "for the same. Also along with write TRANS_VRR_VSYNC values.\n" + "\n" + "Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>\n" + "---\n" + " drivers/gpu/drm/i915/display/intel_ddi.c | 1 +\n" + " drivers/gpu/drm/i915/display/intel_dp.c | 1 +\n" + " 2 files changed, 2 insertions(+)\n" + "\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c\n" + "index bea441590204..6b8088321582 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_ddi.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_ddi.c\n" + "@@ -3971,6 +3971,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,\n" + " \n" + " \tintel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);\n" + " \tintel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);\n" + "+\tintel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);\n" + " \n" + " \tintel_audio_codec_get_config(encoder, pipe_config);\n" + " }\n" + "diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "index 86de854516ef..9309abeda241 100644\n" + "--- a/drivers/gpu/drm/i915/display/intel_dp.c\n" + "+++ b/drivers/gpu/drm/i915/display/intel_dp.c\n" + "@@ -4294,6 +4294,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,\n" + " \t\treturn;\n" + " \n" + " \tintel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);\n" + "+\tintel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);\n" + " \n" + " \tintel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);\n" + } -a02cec60cf324aee429089d3a3e1bb9c9f52077d7290c8c2053b1b8fbfd2973d +675bed12a6f5a64f82c575f64024faaf303c81cd90716338976bf63275fc329e
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