Re: [PATCH v3 4/4] drm/i915/dg2: Implement Wa_14022698537

Raag Jadav
2024-12-10T11:33:39Z

On Tue, Dec 10, 2024 at 01:33:29PM +0530, Riana Tauro wrote:
> On 10/30/2024 8:04 PM, Raag Jadav wrote:
> > G8 power state entry is disabled due to a limitation on DG2, so we
> > enable it from driver with Wa_14022698537. For now we enable it for
> > all DG2 devices with the exception of a few, for which, we enable
> > only when paired with whitelisted CPU models. This works with Native
> > ASMP and reduces idle power consumption.
> %s/ASMP/ASPM

Turns out I already have it locally but I don't remember fixing it.
Bit of a supernatural moment.

> With that
> Reviewed-by: Riana Tauro <riana.tauro@intel.com>

Awesome :)

...

> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 89e4381f8baa..d400c77423a5 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3617,6 +3617,7 @@
> > #define POWER_SETUP_I1_WATTS REG_BIT(31)
> > #define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
> > #define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
> > +#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
> Is the alignment correct?

Yeah, we all fell for the same trick.
https://lore.kernel.org/intel-gfx/ZyJgYML0jLuHxG7G@black.fi.intel.com/

Raag

> > #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> > #define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
> > /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
>