From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21138C3ABAC for ; Tue, 6 May 2025 14:57:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA3BA10E6E4; Tue, 6 May 2025 14:57:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="IaX9th0S"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B4EA10E6D9; Tue, 6 May 2025 14:57:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1746543463; x=1778079463; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Az45UzVHRn4d3iZF95bbZBRTpl+kEY15Bf988eDxFSE=; b=IaX9th0SJHp69q2qBJVZb9agWgTxWhE2VhJKxAiovN4ihEZ5ZHJcOzP1 gu0OA1xJGgRk4SHtS/JVuXt5IChZJY4NL+JS84DxkBhCQJN/iv5h5D/kp eJPMUaMLiBNKrYtAcLXaHqi0JaD0W0HEe5cIMtqhbCFY1bbtq2peNPZXu Y31/bDjYMULMkqfmqAli6/JapNsCGEpz4/7KyPOpWInSR1VG2qREoY6sw ONX0kAYbem9W8CTSVtdIa+EJVTq9/1D+24AYxNNR1E6KTrfXg340FFrm3 3LZYcMh9QUPF03uu/1yfXAJOhdzCMfkkeaPYIR1WrWKUln4quXncN/4B9 g==; X-CSE-ConnectionGUID: 0GPqe101Rn2+6zCsD5BMCg== X-CSE-MsgGUID: aIrKU9abQx28q/agVox55g== X-IronPort-AV: E=McAfee;i="6700,10204,11425"; a="59206160" X-IronPort-AV: E=Sophos;i="6.15,266,1739865600"; d="scan'208";a="59206160" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2025 07:57:43 -0700 X-CSE-ConnectionGUID: VzkRMMe6Tp+gAEegwR4law== X-CSE-MsgGUID: 2c2pFMnoTrWefFxtGg5uVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,266,1739865600"; d="scan'208";a="166572253" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa002.jf.intel.com with ESMTP; 06 May 2025 07:57:41 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, ville.syrjala@intel.com Subject: [PATCH v4 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits Date: Tue, 6 May 2025 20:25:15 +0530 Message-ID: <20250506145517.4129419-16-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250506145517.4129419-1-mitulkumar.ajitkumar.golani@intel.com> References: <20250506145517.4129419-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Pause the DMC DC Balancing for the remainder of the commit so that vmin/vmax won't change after we've baked them into the DSB vblank evasion commands. --v2: - Remove typo. (Ankit) - Separate vrr enable structuring. (Ankit) --v3: - Add gaurd before accessing DC balance bits. - Remove redundancy checks. Signed-off-by: Ville Syrjälä Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 20c7c6eb485d..3111fd54968a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7215,6 +7215,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, } if (new_crtc_state->use_dsb) { + if (new_crtc_state->vrr.dc_balance.enable) { + /* + * Pause the DMC DC balancing for the remainder of + * the commit so that vmin/vmax won't change after + * we've baked them into the DSB vblank evasion + * commands. + * + * FIXME maybe need a small delay here to make sure + * DMC has finished updating the values? Or we need + * a better DMC<->driver protocol that gives is real + * guarantees about that... + */ + intel_pipedmc_dcb_disable(NULL, crtc); + } + if (intel_crtc_needs_color_update(new_crtc_state)) intel_color_commit_noarm(new_crtc_state->dsb_commit, new_crtc_state); @@ -7251,6 +7266,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state); + if (new_crtc_state->vrr.dc_balance.enable) + intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc); intel_dsb_interrupt(new_crtc_state->dsb_commit); } } diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 92a1bd18fa7a..1275be16e749 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -9,6 +9,7 @@ #include "i915_reg.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dmc.h" #include "intel_dp.h" #include "intel_dmc_regs.h" #include "intel_vrr.h" @@ -622,6 +623,7 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display) void intel_vrr_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 ctl; @@ -643,17 +645,24 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) ctl |= VRR_CTL_CMRR_ENABLE; intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl); + + if (crtc_state->vrr.dc_balance.enable) + intel_pipedmc_dcb_enable(NULL, crtc); } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) { struct intel_display *display = to_intel_display(old_crtc_state); + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; u32 ctl; if (!old_crtc_state->vrr.enable) return; + if (old_crtc_state->vrr.dc_balance.enable) + intel_pipedmc_dcb_disable(NULL, crtc); + ctl = trans_vrr_ctl(old_crtc_state); if (intel_vrr_always_use_vrr_tg(display)) ctl |= VRR_CTL_VRR_ENABLE; -- 2.48.1