From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 44508C87FCA for ; Thu, 7 Aug 2025 11:32:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DCE0B10E821; Thu, 7 Aug 2025 11:32:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MgoNTEzI"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id A9C3A10E7C9; Thu, 7 Aug 2025 11:32:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1754566350; x=1786102350; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1HYUD5SQug+sAUt7OUow3ogAXtmmkzW8FAdtkKw7SEA=; b=MgoNTEzIbWdryAjwGUp9/CGnwb1tla3Cv+/8ykwE0Sfc48Ola9FqKGsq NVmpmn9HzHhVEIPS6pgG9EdUke318EN3FVDih3rLryHYN2xzghTPD/bbW b5LHq2OEZKdAY7JCgWDYtRP3sOTGwpj9htR2nyE0CwrBH8wtBWIu/hYc3 cmMq+AYEopdEXPN/OjuFyg+xhZwj70hyY6xM2zyOOaIjWp6HcRahRvJFq Xve9oaW9U6Ed8dQKqobtVTcDVzs4CUzsohyR0Es17Bd4lCHgGnCdbFFAG usud8dl8+RJy4yrP9Agz0iATFXWGffsTjPjp2ZTlUAAbAt6WtDMD1UUni g==; X-CSE-ConnectionGUID: PGq7W/hjThyJdZgreT7gQw== X-CSE-MsgGUID: 6m83aRZzSxmCzmHr7s3jqg== X-IronPort-AV: E=McAfee;i="6800,10657,11514"; a="67166830" X-IronPort-AV: E=Sophos;i="6.17,271,1747724400"; d="scan'208";a="67166830" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2025 04:29:54 -0700 X-CSE-ConnectionGUID: KKDc2JdaQomIflNFUHYhUw== X-CSE-MsgGUID: BU9YqH1tTG62KWvHZ7kmtQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,271,1747724400"; d="scan'208";a="188716543" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2025 04:29:52 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, jani.nikula@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com, Ankit Nautiyal Subject: [PATCH 04/12] drm/i915/display: Extract helpers to set dsc/scaler prefill latencies Date: Thu, 7 Aug 2025 16:45:40 +0530 Message-ID: <20250807111548.1490624-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250807111548.1490624-1-ankit.k.nautiyal@intel.com> References: <20250807111548.1490624-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently dsc/scaler prefill latencies are handled during watermark calculations. With the optimized guardband, we need to compute the latencies to find the minimum guardband that works for most cases. Extract the helpers to compute these latencies, so that they can be used while computing vrr guardband. While at it, put declarations in reverse xmas tree order for better redability. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display.c | 34 +++++++++++++++ drivers/gpu/drm/i915/display/intel_display.h | 8 ++++ drivers/gpu/drm/i915/display/skl_watermark.c | 46 +++++++++----------- 3 files changed, 63 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c1a3a95c65f0..af4d54672d0d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8328,3 +8328,37 @@ bool intel_scanout_needs_vtd_wa(struct intel_display *display) return IS_DISPLAY_VER(display, 6, 11) && i915_vtd_active(i915); } + +int intel_display_scaler_prefill_latency(int num_scaler_users, u64 hscale, u64 vscale, + int chroma_downscaling_factor, + int cdclk_prefill_adjustment, + int linetime) +{ + int scaler_prefill_latency; + + scaler_prefill_latency = 4 * linetime; + if (num_scaler_users > 1) + scaler_prefill_latency += DIV_ROUND_UP_ULL((4 * linetime * hscale * vscale * + chroma_downscaling_factor), 1000000); + + scaler_prefill_latency *= cdclk_prefill_adjustment; + + return scaler_prefill_latency; +} + +int intel_display_dsc_prefill_latency(int num_scaler_users, u64 *hscale, u64 *vscale, + int chroma_downscaling_factor, + int cdclk_prefill_adjustment, + int linetime) +{ + int dsc_prefill_latency; + + dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10); + + for (int i = 0; i < num_scaler_users; i++) + dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale[i] * vscale[i], + 1000000); + dsc_prefill_latency *= cdclk_prefill_adjustment; + + return dsc_prefill_latency; +} diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 37e2ab301a80..8d094b0a8c6b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -559,5 +559,13 @@ bool assert_port_valid(struct intel_display *display, enum port port); bool intel_scanout_needs_vtd_wa(struct intel_display *display); int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state); +int intel_display_scaler_prefill_latency(int num_scaler_users, u64 hscale, u64 vscale, + int chroma_downscaling_factor, + int cdclk_prefill_adjustment, + int linetime); +int intel_display_dsc_prefill_latency(int num_scaler_users, u64 *hscale, u64 *vscale, + int chroma_downscaling_factor, + int cdclk_prefill_adjustment, + int linetime); #endif diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 97b42bbf5642..4474f987de06 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2179,11 +2179,12 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) static int dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime) { + const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; + int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - const struct intel_crtc_scaler_state *scaler_state = - &crtc_state->scaler_state; int num_scaler_users = hweight32(scaler_state->scaler_users); - int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state); + u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)]; + u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)]; u32 dsc_prefill_latency = 0; if (!crtc_state->dsc.compression_enable || @@ -2191,18 +2192,16 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime) num_scaler_users > crtc->num_scalers) return dsc_prefill_latency; - dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10); - for (int i = 0; i < num_scaler_users; i++) { - u64 hscale_k, vscale_k; - - hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16); - vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16); - dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k, - 1000000); + hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16); + vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16); } - dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state); + dsc_prefill_latency = + intel_display_dsc_prefill_latency(num_scaler_users, hscale_k, vscale_k, + chroma_downscaling_factor, + cdclk_prefill_adjustment(crtc_state), + linetime); return dsc_prefill_latency; } @@ -2210,28 +2209,25 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime) static int scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime) { - const struct intel_crtc_scaler_state *scaler_state = - &crtc_state->scaler_state; + const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; + int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state); int num_scaler_users = hweight32(scaler_state->scaler_users); + u64 hscale_k = 1000, vscale_k = 1000; int scaler_prefill_latency = 0; if (!num_scaler_users) return scaler_prefill_latency; - scaler_prefill_latency = 4 * linetime; - if (num_scaler_users > 1) { - u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16); - u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16); - int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state); - int latency; - - latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k * - chroma_downscaling_factor), 1000000); - scaler_prefill_latency += latency; + hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16); + vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16); } - scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state); + scaler_prefill_latency = + intel_display_scaler_prefill_latency(num_scaler_users, hscale_k, vscale_k, + chroma_downscaling_factor, + cdclk_prefill_adjustment(crtc_state), + linetime); return scaler_prefill_latency; } -- 2.45.2