From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E39DCA0FE9 for ; Mon, 25 Aug 2025 12:49:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2283910E45C; Mon, 25 Aug 2025 12:49:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="R0A1jEMl"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 74DED10E45C; Mon, 25 Aug 2025 12:49:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756126191; x=1787662191; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MFOb4FHtCPujkm0NuxhSsUZfQs3nbcyLtZooj+BrD/s=; b=R0A1jEMlD/xcmGh0wyCwCVKIFzFJlVeB8p+2SyWp86TI82AM5W6T2fL8 0FmJnkmAGI/XYJX0sU30qX62WLpDHzsnCmckM+q9+CicJAOwphacGA0tW 356HoZygTzPFk/ZUs+hNX/i1AxfOyI+268blXHyOWV7na31BchwnKLFHX ASKskSah1vn+dNIys3Mw7+uHz8E4p+iDs5Sxw4lnKFvGncSUjKKGR1IUF GUbFOr5w1j9r/uxkeD6MsmTW79JLaCOBBTgQAETU0Feb8uQgXXzdo/V/v e60pYg9MmrS3ijVTcaY3D84l/0QNOSRCBJFChC7uMy4vwuXIgd+bqVXWg w==; X-CSE-ConnectionGUID: C5VI6boyTludowVCkwe2vw== X-CSE-MsgGUID: N1zuoFa6RaqBywQeLY2/xg== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="62164125" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="62164125" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2025 05:49:51 -0700 X-CSE-ConnectionGUID: 7fVrL69sQReFDa/7ju5i0Q== X-CSE-MsgGUID: fpeZ1k7tSdiAGpHGqLtRpw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,213,1751266800"; d="scan'208";a="200230003" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2025 05:49:48 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, Ankit Nautiyal , Mitul Golani Subject: [PATCH 09/12] drm/i915/skl_watermark: Remove redundant latency checks from vblank validation Date: Mon, 25 Aug 2025 18:05:45 +0530 Message-ID: <20250825123548.3022474-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250825123548.3022474-1-ankit.k.nautiyal@intel.com> References: <20250825123548.3022474-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Drop DSC and scaler prefill latency checks from skl_is_vblank_too_short(). These are now covered by the guardband validation added during the atomic CRTC check phase. This cleanup prepares for future changes where the guardband will be optimized independently of vblank length, making vblank-based checks obsolete. Signed-off-by: Ankit Nautiyal Reviewed-by: Mitul Golani --- drivers/gpu/drm/i915/display/skl_watermark.c | 79 -------------------- 1 file changed, 79 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 9ce526e6c285..b2dfab0cd48b 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -28,7 +28,6 @@ #include "intel_flipq.h" #include "intel_pcode.h" #include "intel_plane.h" -#include "intel_vrr.h" #include "intel_wm.h" #include "skl_universal_plane_regs.h" #include "skl_scaler.h" @@ -2159,93 +2158,15 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, return 0; } -static int -cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) -{ - struct intel_display *display = to_intel_display(crtc_state); - struct intel_atomic_state *state = - to_intel_atomic_state(crtc_state->uapi.state); - const struct intel_cdclk_state *cdclk_state; - - cdclk_state = intel_atomic_get_cdclk_state(state); - if (IS_ERR(cdclk_state)) { - drm_WARN_ON(display->drm, PTR_ERR(cdclk_state)); - return 1; - } - - return min(1, DIV_ROUND_UP(crtc_state->pixel_rate, - 2 * intel_cdclk_logical(cdclk_state))); -} - -static int -dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime) -{ - const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; - int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - int num_scaler_users = hweight32(scaler_state->scaler_users); - u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)]; - u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)]; - u32 dsc_prefill_latency = 0; - - if (!crtc_state->dsc.compression_enable || - !num_scaler_users || - num_scaler_users > crtc->num_scalers) - return dsc_prefill_latency; - - for (int i = 0; i < num_scaler_users; i++) { - hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16); - vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16); - } - - dsc_prefill_latency = - intel_vrr_guardband_dsc_latency(num_scaler_users, hscale_k, vscale_k, - chroma_downscaling_factor, - cdclk_prefill_adjustment(crtc_state), - linetime); - - return dsc_prefill_latency; -} - -static int -scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime) -{ - const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; - int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state); - int num_scaler_users = hweight32(scaler_state->scaler_users); - u64 hscale_k = 0, vscale_k = 0; - int scaler_prefill_latency = 0; - - if (!num_scaler_users) - return scaler_prefill_latency; - - if (num_scaler_users > 1) { - hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16); - vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16); - } - - scaler_prefill_latency = - intel_vrr_guardband_scaler_latency(num_scaler_users, hscale_k, vscale_k, - chroma_downscaling_factor, - cdclk_prefill_adjustment(crtc_state), - linetime); - - return scaler_prefill_latency; -} - static bool skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, int wm0_lines, int latency) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - int linetime = DIV_ROUND_UP(1000 * adjusted_mode->htotal, - adjusted_mode->clock); return crtc_state->framestart_delay + intel_usecs_to_scanlines(adjusted_mode, latency) + - DIV_ROUND_UP(scaler_prefill_latency(crtc_state, linetime), linetime) + - DIV_ROUND_UP(dsc_prefill_latency(crtc_state, linetime), linetime) + wm0_lines > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; } -- 2.45.2