From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F9D1CCD1A5 for ; Wed, 22 Oct 2025 00:31:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B2DB10E678; Wed, 22 Oct 2025 00:31:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nAO1ehzx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5056E10E678; Wed, 22 Oct 2025 00:31:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761093095; x=1792629095; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=423sBug4V6mCs/I1WoSxjQ6Favdv0WDqbDD06DENX+k=; b=nAO1ehzxJfdj8L177Y0ixT8Xi87YuZ3yr9JeWDcR7Crgh5ltE/a+kNCF HzZ+DZoZd/WqB1DnQmhxyb6Kx9Zach0NkS2Nz2r7dUDw/LJYXvjeSMhRw D8H6lCMIHDc1zaQVwh/BiwsMw1iFO5uhrrmgYhYPYapHNGH8brebQBkdd +OvLDcf89BOyb3ROEQX9iK6C5iDllLnz6rcxl3mE8XXrehvTbbuHySi0o QP2N6+Y/KG0ua5gV/7FRqBdznLr41G8G8I3xIYNVXJu5e3OvtFy3uQDo+ sR+KzFyEP+SRpYyJGgd5hW2TYWgGnUO9hdQZFf3GjDnrW9cS63ZMks4ib A==; X-CSE-ConnectionGUID: QLRq6qnnTkeQcDPnzXJhrA== X-CSE-MsgGUID: FFKWJB7HTYWqDzBC+3T2Ow== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="85855728" X-IronPort-AV: E=Sophos;i="6.19,246,1754982000"; d="scan'208";a="85855728" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2025 17:31:35 -0700 X-CSE-ConnectionGUID: 6xP770ZCTNq9CnP07qdV1g== X-CSE-MsgGUID: kG/6Do3HR8iGgUqM09qecg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,246,1754982000"; d="scan'208";a="188132377" Received: from gpacheco-mobl.amr.corp.intel.com (HELO [192.168.1.16]) ([10.124.221.26]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2025 17:31:31 -0700 From: Gustavo Sousa Date: Tue, 21 Oct 2025 21:28:35 -0300 Subject: [PATCH v2 10/32] drm/i915/xe3p_lpd: Wait for AUX channel power status MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251021-xe3p_lpd-basic-enabling-v2-10-10eae6d655b8@intel.com> References: <20251021-xe3p_lpd-basic-enabling-v2-0-10eae6d655b8@intel.com> In-Reply-To: <20251021-xe3p_lpd-basic-enabling-v2-0-10eae6d655b8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal , Dnyaneshwar Bhadane , Gustavo Sousa , =?utf-8?q?Jouni_H=C3=B6gander?= , Juha-pekka Heikkila , Luca Coelho , Lucas De Marchi , Matt Atwood , Matt Roper , Ravi Kumar Vodapalli , Shekhar Chauhan , Vinod Govindapillai X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The LT PHY in Xe3p_LPD allows polling for the AUX channel power status to verify completion of power up and down. As such, let's use that field to have a more precise waiting time instead of a fixed one. Bspec: 68967 Signed-off-by: Gustavo Sousa --- .../drm/i915/display/intel_display_power_well.c | 32 +++++++++++++++++----- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 5e88b930f5aa..ba2552adb58b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1858,23 +1858,41 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display, XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); - /* - * The power status flag cannot be used to determine whether aux - * power wells have finished powering up. Instead we're - * expected to just wait a fixed 600us after raising the request - * bit. - */ - usleep_range(600, 1200); + if (DISPLAY_VER(display) >= 35) { + if (intel_de_wait_for_set(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), + XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1)) + drm_warn(display->drm, + "Timeout waiting for PHY %c AUX channel power to be up\n", + phy_name(phy)); + } else { + /* + * The power status flag cannot be used to determine whether aux + * power wells have finished powering up. Instead we're + * expected to just wait a fixed 600us after raising the request + * bit. + */ + usleep_range(600, 1200); + } } static void xelpdp_aux_power_well_disable(struct intel_display *display, struct i915_power_well *power_well) { enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; + enum phy phy = icl_aux_pw_to_phy(display, power_well); intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 0); + + if (DISPLAY_VER(display) >= 35) { + if (intel_de_wait_for_clear(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), + XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1)) + drm_warn(display->drm, + "Timeout waiting for PHY %c AUX channel power to be down\n", + phy_name(phy)); + } + usleep_range(10, 30); } -- 2.51.0