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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: "Ankit Nautiyal" <ankit.k.nautiyal@intel.com>,
	"Dnyaneshwar Bhadane" <dnyaneshwar.bhadane@intel.com>,
	"Gustavo Sousa" <gustavo.sousa@intel.com>,
	"Jouni Högander" <jouni.hogander@intel.com>,
	"Juha-pekka Heikkila" <juha-pekka.heikkila@intel.com>,
	"Luca Coelho" <luciano.coelho@intel.com>,
	"Lucas De Marchi" <lucas.demarchi@intel.com>,
	"Matt Atwood" <matthew.s.atwood@intel.com>,
	"Matt Roper" <matthew.d.roper@intel.com>,
	"Ravi Kumar Vodapalli" <ravi.kumar.vodapalli@intel.com>,
	"Shekhar Chauhan" <shekhar.chauhan@intel.com>,
	"Vinod Govindapillai" <vinod.govindapillai@intel.com>,
	"Suraj Kandpal" <suraj.kandpal@intel.com>
Subject: [PATCH v2 18/32] drm/i915/xe3p_lpd: Drop support for interlace mode
Date: Tue, 21 Oct 2025 21:28:43 -0300	[thread overview]
Message-ID: <20251021-xe3p_lpd-basic-enabling-v2-18-10eae6d655b8@intel.com> (raw)
In-Reply-To: <20251021-xe3p_lpd-basic-enabling-v2-0-10eae6d655b8@intel.com>

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Interlace mode is officially removed from HW from Xe3p_LPD.  The
register TRANS_VSYNCSHIFT and the bits in TRANS_CONF are now removed, so
make sure we do not set/get these anymore.

Bspec: 69961, 70000
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a8b4619de347..5ae02bfc2148 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2633,7 +2633,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		crtc_vblank_start = 1;
 	}
 
-	if (DISPLAY_VER(display) >= 4)
+	if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
 		intel_de_write(display,
 			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
 			       vsyncshift);
@@ -2771,7 +2771,7 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if (DISPLAY_VER(display) == 2)
+	if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35)
 		return false;
 
 	if (DISPLAY_VER(display) >= 9 ||
@@ -3162,10 +3162,12 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
 	if (display->platform.haswell && crtc_state->dither)
 		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
 
-	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
-		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
-	else
-		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
+	if (DISPLAY_VER(display) < 35) {
+		if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+			val |= TRANSCONF_INTERLACE_IF_ID_ILK;
+		else
+			val |= TRANSCONF_INTERLACE_PF_PD_ILK;
+	}
 
 	if (display->platform.haswell &&
 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)

-- 
2.51.0


  parent reply	other threads:[~2025-10-22  0:32 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-22  0:28 [PATCH v2 00/32] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 01/32] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 02/32] drm/i915/xe3p_lpd: Drop north display reset option programming Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 03/32] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw() Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 04/32] drm/i915/dram: Add field ecc_impacting_de_bw Gustavo Sousa
2025-10-22 11:37   ` Gustavo Sousa
2025-10-22 11:53     ` Jani Nikula
2025-10-22 12:12       ` Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 05/32] drm/i915/xe3p_lpd: Update bandwidth parameters Gustavo Sousa
2025-10-22 14:56   ` Matt Roper
2025-10-27 22:26     ` Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 06/32] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 07/32] drm/i915/xe3p_lpd: Support UINT16 formats Gustavo Sousa
2025-10-22 12:28   ` Ville Syrjälä
2025-10-22 17:58     ` Matt Roper
2025-10-27 19:41       ` Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 08/32] drm/i915/xe3p_lpd: Extend FBC support to " Gustavo Sousa
2025-10-22 12:39   ` Ville Syrjälä
2025-10-22  0:28 ` [PATCH v2 09/32] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 10/32] drm/i915/xe3p_lpd: Wait for AUX channel power status Gustavo Sousa
2025-10-29 20:06   ` Matt Roper
2025-10-29 20:50     ` Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 11/32] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints Gustavo Sousa
2025-10-29 20:54   ` Matt Roper
2025-10-30 21:56     ` Gustavo Sousa
2025-10-31 22:17       ` Matt Roper
2025-10-31 22:41         ` Gustavo Sousa
2025-11-11  0:44         ` Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 12/32] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 13/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers Gustavo Sousa
2025-10-29 21:22   ` Matt Roper
2025-10-31  2:48     ` Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 14/32] drm/i915/wm: Reorder adjust_wm_latency() for Xe3_LPD Gustavo Sousa
2025-10-29 21:53   ` Matt Roper
2025-10-29 22:22   ` Ville Syrjälä
2025-10-29 22:36     ` Ville Syrjälä
2025-10-30 13:45       ` Gustavo Sousa
2025-10-30 15:38         ` Ville Syrjälä
2025-10-30 13:48     ` Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 15/32] drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment Gustavo Sousa
2025-10-29 22:08   ` Matt Roper
2025-10-29 22:39     ` Ville Syrjälä
2025-10-30 13:53       ` Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 16/32] drm/i915/xe3p_lpd: Add CDCLK table Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 17/32] drm/i915/xe3p_lpd: Load DMC firmware Gustavo Sousa
2025-10-22  0:28 ` Gustavo Sousa [this message]
2025-10-22  0:28 ` [PATCH v2 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4 Gustavo Sousa
2025-10-29 22:14   ` Matt Roper
2025-10-31 17:36     ` Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 20/32] drm/i915/xe3p_lpd: Enable system caching for FBC Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 21/32] drm/i915/xe3p_lpd: Extend Wa_16025573575 Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 22/32] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 23/32] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 24/32] drm/i915/xe3p_lpd: Introduce pixel normalizer config support Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 25/32] drm/i915/xe3p_lpd: Add FBC support for FP16 formats Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 26/32] drm/i915/xe3p_lpd: Enable pixel normalizer for fp16 formats for FBC Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 28/32] drm/i915/power: Use intel_encoder_is_tc() Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 29/32] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc() Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 30/32] drm/i915/wm: don't use method1 in Xe3p_LPD onwards Gustavo Sousa
2025-10-22 15:08   ` Shekhar Chauhan
2025-10-22  0:28 ` [PATCH v2 31/32] drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation Gustavo Sousa
2025-10-22  0:28 ` [PATCH v2 32/32] drm/i915/nvls: Add NVL-S display support Gustavo Sousa
2025-10-22 15:12   ` Shekhar Chauhan
2025-10-22  1:46 ` ✗ i915.CI.BAT: failure for drm/i915/display: Add initial support for Xe3p_LPD (rev2) Patchwork

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