From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBBEBCCD1A5 for ; Wed, 22 Oct 2025 00:31:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7076A10E65F; Wed, 22 Oct 2025 00:31:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bNn5Hwlk"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 69AC910E65F; Wed, 22 Oct 2025 00:31:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761093067; x=1792629067; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=LgPv1UTrE0bk9nJZtVjRzDOaVZsFjzFVTet9Pl2CKNk=; b=bNn5HwlkidxPXx8f8E2DwIePWBYi1ToykOjZyk4oy7jvf6EaLGlqjEUf VBZ41WnYxtpryrFG0c/RewB4Xri8yWxrTu88BnX3mmcCwPB448fiLkycw 2MWqsINfmq5GTJd+TQToZH63aBFPyGCXdXupyUe7B48E1c6/bqilHiQqs jEZRNnyzrJZWmTkefKWb8/v/hygJyB1uSUNQvu8xZk/0iTgb0hP/hDacG GGDo2xw5hZsCKKoIfgPtreieL5XySQlp5z6BBvbHcGJN31CRNF8YECqgz Lh6ZnSBGk/SRxD7EFufSmwUboqiGjaPCq43B3U8SOX78WxsQc7LkEQEVr A==; X-CSE-ConnectionGUID: BFO+FEwvSAmxZJwOhitPjg== X-CSE-MsgGUID: TW8boDQKSv2qaZETIX143w== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="85855694" X-IronPort-AV: E=Sophos;i="6.19,246,1754982000"; d="scan'208";a="85855694" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2025 17:31:07 -0700 X-CSE-ConnectionGUID: PVAXaJ9sQeOi0M+9apaBgg== X-CSE-MsgGUID: YH2E2qDxS0+XoGedPxE4Ag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,246,1754982000"; d="scan'208";a="188132258" Received: from gpacheco-mobl.amr.corp.intel.com (HELO [192.168.1.16]) ([10.124.221.26]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2025 17:31:03 -0700 From: Gustavo Sousa Date: Tue, 21 Oct 2025 21:28:27 -0300 Subject: [PATCH v2 02/32] drm/i915/xe3p_lpd: Drop north display reset option programming MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251021-xe3p_lpd-basic-enabling-v2-2-10eae6d655b8@intel.com> References: <20251021-xe3p_lpd-basic-enabling-v2-0-10eae6d655b8@intel.com> In-Reply-To: <20251021-xe3p_lpd-basic-enabling-v2-0-10eae6d655b8@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal , Dnyaneshwar Bhadane , Gustavo Sousa , =?utf-8?q?Jouni_H=C3=B6gander?= , Juha-pekka Heikkila , Luca Coelho , Lucas De Marchi , Matt Atwood , Matt Roper , Ravi Kumar Vodapalli , Shekhar Chauhan , Vinod Govindapillai X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper The NDE_RSTWRN_OPT has been removed on Xe3p platforms and reset option programming is no longer necessary during display init. Bspec: 68846, 69137 Signed-off-by: Matt Roper Reviewed-by: Matt Atwood Signed-off-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index da4babfd6bcb..821f5097e9c0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1436,6 +1436,9 @@ static void intel_pch_reset_handshake(struct intel_display *display, i915_reg_t reg; u32 reset_bits; + if (DISPLAY_VER(display) >= 35) + return; + if (display->platform.ivybridge) { reg = GEN7_MSG_CTL; reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK; -- 2.51.0