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([10.245.244.2]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2025 05:26:06 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , Ankit Nautiyal Subject: [PATCH] drm/i915/display: Take into account AS SDP in intel_dp_sdp_min_guardband Date: Wed, 22 Oct 2025 15:25:52 +0300 Message-ID: <20251022122552.890090-1-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We started seeing "[drm] *ERROR* Timed out waiting PSR idle state" after taking optimized guardband into use. These are seen because VSC SDPs are sent on same line as AS SDPs when AS SDP is enabled. AS SDP is sent on line configured in EMP_AS_SDP_TL register. We are configuring crtc_state->vrr.vsync_start into that register. Fix this by ensuring AS SDP is sent on line which is within guardband. From the bspec: EMP_AS_SDP_TL < SCL + Guardband Bspec: 71197 Fixes: 52ecd48b8d3f ("drm/i915/dp: Add helper to get min sdp guardband") Cc: Ankit Nautiyal Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b0aeb6c2de86c..54b5e060be82a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -7026,7 +7026,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder, } static -int intel_dp_get_lines_for_sdp(u32 type) +int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 type) { switch (type) { case DP_SDP_VSC_EXT_VESA: @@ -7036,6 +7036,8 @@ int intel_dp_get_lines_for_sdp(u32 type) return 8; case DP_SDP_PPS: return 7; + case DP_SDP_ADAPTIVE_SYNC: + return crtc_state->vrr.vsync_start + 1; default: break; } @@ -7052,11 +7054,18 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state, crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) sdp_guardband = max(sdp_guardband, - intel_dp_get_lines_for_sdp(HDMI_PACKET_TYPE_GAMUT_METADATA)); + intel_dp_get_lines_for_sdp(crtc_state, + HDMI_PACKET_TYPE_GAMUT_METADATA)); if (assume_all_enabled || crtc_state->dsc.compression_enable) - sdp_guardband = max(sdp_guardband, intel_dp_get_lines_for_sdp(DP_SDP_PPS)); + sdp_guardband = max(sdp_guardband, + intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS)); + + if (assume_all_enabled || + crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) + sdp_guardband = max(sdp_guardband, + intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC)); return sdp_guardband; } -- 2.43.0