[PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD

[PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD

[Gustavo Sousa]

This series adds initial support for Xe3p_LPD, Intel's display
architecture with IP version 35.

This series contains basic enabling patches and does not provide
complete support for the display IP yet. More involved features, like
the new PHY implementation and ALPM are implemented as separate patch
series.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Changes in v3:
- Reshuffled patches so that most of the ones already containing a r-b
  are placed at the start.
- Dropped "drm/i915/xe3p_lpd: Wait for AUX channel power status", as a
  similar patch was already applied from a patch series dedicated to LT
  PHY
  (https://lore.kernel.org/all/20251101032513.4171255-25-suraj.kandpal@intel.com/).
- Dropped patches related to UINT16 plane formats, as they were
  incomplete and were not specific to Xe3p_LPD.
- Dropped FBC related patches, as Vinod is handling them as a separated
  series
  (https://lore.kernel.org/intel-gfx/20251027134001.325064-1-vinod.govindapillai@intel.com/)
- Dropped "drm/i915/xe3p_lpd: PSR SU minimum lines is 4", since that
  change is not valid according to Bspec.
- Incorporated review feedback on the other patches. Please check the
  changelog in the individual patches for details.
- Link to v2: https://lore.kernel.org/r/20251021-xe3p_lpd-basic-enabling-v2-0-10eae6d655b8@intel.com

Changes in v2:
- Incorporated review feedback. Please check the changelog in the
  patches for details.
- Link to v1: https://lore.kernel.org/r/20251015-xe3p_lpd-basic-enabling-v1-0-d2d1e26520aa@intel.com

---
Ankit Nautiyal (1):
      drm/i915/xe3p_lpd: Drop support for interlace mode

Gustavo Sousa (16):
      drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()
      drm/i915/xe3p_lpd: Add CDCLK table
      drm/i915/xe3p_lpd: Load DMC firmware
      drm/i915/xe3p_lpd: Extend Wa_16025573575
      drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D
      drm/i915/dram: Add field ecc_impacting_de_bw
      drm/i915/xe3p_lpd: Log FBC-related debug info for PIPE underrun
      drm/i915/wm: Do not make latency values monotonic on Xe3 onward
      drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency
      drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc
      drm/i915/power: Use intel_encoder_is_tc()
      drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()
      drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation
      drm/i915/display: Use platform check in HAS_LT_PHY()
      drm/i915/display: Move HAS_LT_PHY() to intel_display_device.h
      drm/i915/display: Use HAS_LT_PHY() for LT PHY AUX power

Juha-pekka Heikkila (1):
      drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format

Luca Coelho (1):
      drm/i915/wm: don't use method1 in Xe3p_LPD onwards

Matt Atwood (1):
      drm/i915/xe3p_lpd: Update bandwidth parameters

Matt Roper (1):
      drm/i915/xe3p_lpd: Drop north display reset option programming

Ravi Kumar Vodapalli (1):
      drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers

Sai Teja Pottumuttu (6):
      drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features
      drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields
      drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces
      drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks
      drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints
      drm/i915/nvls: Add NVL-S display support

Vinod Govindapillai (1):
      drm/i915/xe3p_lpd: Enable system caching for FBC

 drivers/gpu/drm/i915/display/intel_bios.c          |  54 +++++++-
 drivers/gpu/drm/i915/display/intel_bios.h          |   2 +
 drivers/gpu/drm/i915/display/intel_bw.c            |  43 +++---
 drivers/gpu/drm/i915/display/intel_cdclk.c         |  44 +++++-
 drivers/gpu/drm/i915/display/intel_color.c         |  13 +-
 drivers/gpu/drm/i915/display/intel_ddi.c           |  11 ++
 drivers/gpu/drm/i915/display/intel_display.c       |  33 ++++-
 .../gpu/drm/i915/display/intel_display_device.c    |   6 +
 .../gpu/drm/i915/display/intel_display_device.h    |   5 +-
 drivers/gpu/drm/i915/display/intel_display_power.c |   3 +
 .../drm/i915/display/intel_display_power_well.c    |  42 +++---
 drivers/gpu/drm/i915/display/intel_display_regs.h  |  40 +++++-
 drivers/gpu/drm/i915/display/intel_display_types.h |   1 +
 drivers/gpu/drm/i915/display/intel_display_wa.c    |   3 +-
 drivers/gpu/drm/i915/display/intel_dmc.c           |  13 +-
 drivers/gpu/drm/i915/display/intel_fbc.c           |  92 +++++++++++++
 drivers/gpu/drm/i915/display/intel_fbc.h           |   2 +
 drivers/gpu/drm/i915/display/intel_fbc_regs.h      |  11 ++
 drivers/gpu/drm/i915/display/intel_fifo_underrun.c |  73 ++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h        |   2 -
 drivers/gpu/drm/i915/display/intel_plane.c         |   3 +
 drivers/gpu/drm/i915/display/intel_tc.c            | 151 ++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h      |   3 +-
 drivers/gpu/drm/i915/display/skl_universal_plane.c |   3 +-
 .../drm/i915/display/skl_universal_plane_regs.h    |  12 +-
 drivers/gpu/drm/i915/display/skl_watermark.c       |  42 +++++-
 drivers/gpu/drm/i915/display/skl_watermark_regs.h  |  52 +++----
 drivers/gpu/drm/i915/i915_reg.h                    |   1 +
 drivers/gpu/drm/i915/soc/intel_dram.c              |   4 +
 drivers/gpu/drm/i915/soc/intel_dram.h              |   1 +
 30 files changed, 670 insertions(+), 95 deletions(-)
---
base-commit: c6cd36e5d63bd95a7b68e934d874921a67aecfd2
change-id: 20251014-xe3p_lpd-basic-enabling-eb4424698b44

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>

[PATCH v3 01/29] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Xe3p_LPD (display version 35) is similar to Xe2_LPD with respect to the
features described by struct intel_display_device_info, so reuse its
device descriptor.

v2:
  - Add reference to Bspec 74201. (Shekhar)

Bspec: 74201, 74304
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 328447a5e5e8..1170afaa8680 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1507,6 +1507,7 @@ static const struct {
 	{ 20,  0, &xe2_lpd_display },
 	{ 30,  0, &xe2_lpd_display },
 	{ 30,  2, &wcl_display },
+	{ 35,  0, &xe2_lpd_display },
 };
 
 static const struct intel_display_device_info *

-- 
2.51.0

[PATCH v3 02/29] drm/i915/xe3p_lpd: Drop north display reset option programming

[Gustavo Sousa]

From: Matt Roper <matthew.d.roper@intel.com>

The NDE_RSTWRN_OPT has been removed on Xe3p platforms and reset option
programming is no longer necessary during display init.

Bspec: 68846, 69137
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fbfa823b6dce..74fcd9cfe911 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1438,6 +1438,9 @@ static void intel_pch_reset_handshake(struct intel_display *display,
 	i915_reg_t reg;
 	u32 reset_bits;
 
+	if (DISPLAY_VER(display) >= 35)
+		return;
+
 	if (display->platform.ivybridge) {
 		reg = GEN7_MSG_CTL;
 		reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;

-- 
2.51.0

[PATCH v3 03/29] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()

[Gustavo Sousa]

Looking at the current if-ladder in intel_bw_init_hw(), we see that
Xe2_HPD contains two entries, differing only for ECC memories.  Let's
improve readability by using braces and allowing adding extra conditions
for each case.

v2:
  - Tweaked commit message, since we are not going to add the ECC case
    for Xe3p_LPD anymore.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index f97ccc1a96a7..bf37d7a9732e 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -805,29 +805,30 @@ void intel_bw_init_hw(struct intel_display *display)
 	if (!HAS_DISPLAY(display))
 		return;
 
-	if (DISPLAY_VERx100(display) >= 3002)
+	if (DISPLAY_VERx100(display) >= 3002) {
 		tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
-	else if (DISPLAY_VER(display) >= 30)
+	} else if (DISPLAY_VER(display) >= 30) {
 		tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
-	else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&
-		 dram_info->type == INTEL_DRAM_GDDR_ECC)
-		xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
-	else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
-		xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
-	else if (DISPLAY_VER(display) >= 14)
+	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
+		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
+			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
+		else
+			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
+	} else if (DISPLAY_VER(display) >= 14) {
 		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
-	else if (display->platform.dg2)
+	} else if (display->platform.dg2) {
 		dg2_get_bw_info(display);
-	else if (display->platform.alderlake_p)
+	} else if (display->platform.alderlake_p) {
 		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
-	else if (display->platform.alderlake_s)
+	} else if (display->platform.alderlake_s) {
 		tgl_get_bw_info(display, dram_info, &adls_sa_info);
-	else if (display->platform.rocketlake)
+	} else if (display->platform.rocketlake) {
 		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
-	else if (DISPLAY_VER(display) == 12)
+	} else if (DISPLAY_VER(display) == 12) {
 		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
-	else if (DISPLAY_VER(display) == 11)
+	} else if (DISPLAY_VER(display) == 11) {
 		icl_get_bw_info(display, dram_info, &icl_sa_info);
+	}
 }
 
 static unsigned int intel_bw_num_active_planes(struct intel_display *display,

-- 
2.51.0

[PATCH v3 04/29] drm/i915/xe3p_lpd: Update bandwidth parameters

[Gustavo Sousa]

From: Matt Atwood <matthew.s.atwood@intel.com>

Bandwidth parameters for Xe3p_LPD are the same as for Xe3_LPD. Re-use
them.

Since handling for Xe3_LPD version 30.02 is more like a special case,
let's use a "== 3002" check for it inside the ">= 30" branch instead of
adding a new branch for version 35.  That allows us to re-use the ">=
30" branch for Xe3p_LPD.

v2:
  - Do not have a special case for ecc_impacting_de_bw, since there are
    no specific instructions in Bspec for this scenario. (Matt Roper)
v3:
  - Re-use the ">= 30" branch in the if-ladder. (Matt Roper)

Bspec: 68859
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bf37d7a9732e..919b25a5fbac 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -805,10 +805,11 @@ void intel_bw_init_hw(struct intel_display *display)
 	if (!HAS_DISPLAY(display))
 		return;
 
-	if (DISPLAY_VERx100(display) >= 3002) {
-		tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
-	} else if (DISPLAY_VER(display) >= 30) {
-		tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
+	if (DISPLAY_VER(display) >= 30) {
+		if (DISPLAY_VERx100(display) == 3002)
+			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
+		else
+			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
 	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
 		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
 			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);

-- 
2.51.0

[PATCH v3 05/29] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

On Xe3p_LPD, the dbuf blocks fields of different registers are now
documented as 13-bit fields. The dbuf isn't really large enough to need
the 13th bit, but let's go ahead and update the definition now just in
case some new display IP in future ends up needing the larger size. The
extra bit is an unused bit in previous display versions, so we can
safely just extend the existing definition.

Bspec: 69847, 69880, 72053
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 7c944d3ca855..6f815b231340 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -324,7 +324,7 @@
 #define   PLANE_WM_IGNORE_LINES			REG_BIT(30)
 #define   PLANE_WM_AUTO_MIN_ALLOC_EN		REG_BIT(29)
 #define   PLANE_WM_LINES_MASK			REG_GENMASK(26, 14)
-#define   PLANE_WM_BLOCKS_MASK			REG_GENMASK(11, 0)
+#define   PLANE_WM_BLOCKS_MASK			REG_GENMASK(12, 0)
 
 #define _PLANE_WM_SAGV_1_A			0x70258
 #define _PLANE_WM_SAGV_1_B			0x71258
@@ -375,10 +375,10 @@
 							_PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \
 							_PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
 
-/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define   PLANE_BUF_END_MASK			REG_GENMASK(27, 16)
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits, xe3p_lpd 13 bits */
+#define   PLANE_BUF_END_MASK			REG_GENMASK(28, 16)
 #define   PLANE_BUF_END(end)			REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
-#define   PLANE_BUF_START_MASK			REG_GENMASK(11, 0)
+#define   PLANE_BUF_START_MASK			REG_GENMASK(12, 0)
 #define   PLANE_BUF_START(start)		REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
 
 #define _PLANE_MIN_BUF_CFG_1_A			0x70274
@@ -389,9 +389,9 @@
 							_PLANE_MIN_BUF_CFG_1_A, _PLANE_MIN_BUF_CFG_1_B, \
 							_PLANE_MIN_BUF_CFG_2_A, _PLANE_MIN_BUF_CFG_2_B)
 #define	  PLANE_AUTO_MIN_DBUF_EN		REG_BIT(31)
-#define	  PLANE_MIN_DBUF_BLOCKS_MASK		REG_GENMASK(27, 16)
+#define	  PLANE_MIN_DBUF_BLOCKS_MASK		REG_GENMASK(28, 16)
 #define	  PLANE_MIN_DBUF_BLOCKS(val)		REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val))
-#define	  PLANE_INTERIM_DBUF_BLOCKS_MASK	REG_GENMASK(11, 0)
+#define	  PLANE_INTERIM_DBUF_BLOCKS_MASK	REG_GENMASK(12, 0)
 #define	  PLANE_INTERIM_DBUF_BLOCKS(val)	REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val))
 
 /* tgl+ */

-- 
2.51.0

[PATCH v3 06/29] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Starting from Xe3p_LPD, linear surfaces also support horizontal flip.

Bspec: 68904
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ba1bf0bd4c55..bc55fafe9ce3 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1748,7 +1748,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	}
 
 	if (rotation & DRM_MODE_REFLECT_X &&
-	    fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+	    fb->modifier == DRM_FORMAT_MOD_LINEAR &&
+	    DISPLAY_VER(display) < 35) {
 		drm_dbg_kms(display->drm,
 			    "[PLANE:%d:%s] horizontal flip is not supported with linear surface formats\n",
 			    plane->base.base.id, plane->base.name);

-- 
2.51.0

[PATCH v3 07/29] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

With Xe3p_LPD, the SKL_BOTTOM_COLOR_GAMMA_ENABLE and
SKL_BOTTOM_COLOR_CSC_ENABLE bits are being removed. Thus, we need not
set gamma_enable nor csc_enable in crtc_state.

Note that GAMMA_MODE.POST_CSC_GAMMA_ENABLE and CSC_MODE.ICL_CSC_ENABLE
are the documented alternatives for the bottom color bits being removed.
But as these suggested bits are being checked in state checker as part
of gamma_mode, csc_mode fields and as gamma_enable/csc_enable are not
being used anywhere else functionally post ICL, we need not set these
fields in crtc_state.

Bspec: 69734
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 1e97020e7304..a217a67ceb43 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1090,18 +1090,19 @@ static void skl_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	u32 tmp;
 
 	crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
 	crtc_state->csc_mode = ilk_read_csc_mode(crtc);
 
-	tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
+	if (DISPLAY_VER(display) < 35) {
+		u32 tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
 
-	if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
-		crtc_state->gamma_enable = true;
+		if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
+			crtc_state->gamma_enable = true;
 
-	if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
-		crtc_state->csc_enable = true;
+		if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
+			crtc_state->csc_enable = true;
+	}
 }
 
 static void skl_color_commit_arm(struct intel_dsb *dsb,

-- 
2.51.0

[PATCH v3 08/29] drm/i915/xe3p_lpd: Add CDCLK table

[Gustavo Sousa]

Add CDCLK table for Xe3p_LPD.

Just as with Xe3_LPD, we don't need to send voltage index info in the
PMDemand message, so we are able to re-use xe3lpd_cdclk_funcs.

With the new CDCLK table, we also need to update the maximum CDCLK value
returned by intel_update_max_cdclk().

Bspec: 68861, 68863
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 44 ++++++++++++++++++++++++++++--
 1 file changed, 42 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index bdb42fcc4cb2..4d03cfefc72c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1535,6 +1535,41 @@ static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
 	{}
 };
 
+static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = {
+	{ .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 },
+	{ .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 },
+	{ .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa },
+	{ .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a },
+	{ .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 },
+	{ .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 },
+	{ .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee },
+	{ .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de },
+	{ .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff },
+	{}
+};
+
 static const int cdclk_squash_len = 16;
 
 static int cdclk_squash_divider(u16 waveform)
@@ -3561,7 +3596,9 @@ static int intel_compute_max_dotclk(struct intel_display *display)
  */
 void intel_update_max_cdclk(struct intel_display *display)
 {
-	if (DISPLAY_VERx100(display) >= 3002) {
+	if (DISPLAY_VER(display) >= 35) {
+		display->cdclk.max_cdclk_freq = 787200;
+	} else if (DISPLAY_VERx100(display) >= 3002) {
 		display->cdclk.max_cdclk_freq = 480000;
 	} else if (DISPLAY_VER(display) >= 30) {
 		display->cdclk.max_cdclk_freq = 691200;
@@ -3912,7 +3949,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
  */
 void intel_init_cdclk_hooks(struct intel_display *display)
 {
-	if (DISPLAY_VER(display) >= 30) {
+	if (DISPLAY_VER(display) >= 35) {
+		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
+		display->cdclk.table = xe3p_lpd_cdclk_table;
+	} else if (DISPLAY_VER(display) >= 30) {
 		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
 		display->cdclk.table = xe3lpd_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 20) {

-- 
2.51.0

[PATCH v3 09/29] drm/i915/xe3p_lpd: Load DMC firmware

[Gustavo Sousa]

Load the DMC firmware for Xe3p_LPD.

Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 0bddb20a7c86..1b3a9b5608c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -127,6 +127,9 @@ static bool dmc_firmware_param_disabled(struct intel_display *display)
 #define DISPLAY_VER13_DMC_MAX_FW_SIZE	0x20000
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
 
+#define XE3P_LPD_DMC_PATH		DMC_PATH(xe3p_lpd)
+MODULE_FIRMWARE(XE3P_LPD_DMC_PATH);
+
 #define XE3LPD_3002_DMC_PATH		DMC_PATH(xe3lpd_3002)
 MODULE_FIRMWARE(XE3LPD_3002_DMC_PATH);
 
@@ -186,7 +189,11 @@ static const char *dmc_firmware_default(struct intel_display *display, u32 *size
 {
 	const char *fw_path = NULL;
 	u32 max_fw_size = 0;
-	if (DISPLAY_VERx100(display) == 3002) {
+
+	if (DISPLAY_VERx100(display) == 3500) {
+		fw_path = XE3P_LPD_DMC_PATH;
+		max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
+	} else if (DISPLAY_VERx100(display) == 3002) {
 		fw_path = XE3LPD_3002_DMC_PATH;
 		max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
 	} else if (DISPLAY_VERx100(display) == 3000) {

-- 
2.51.0

[PATCH v3 10/29] drm/i915/xe3p_lpd: Drop support for interlace mode

[Gustavo Sousa]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Interlace mode is officially removed from HW from Xe3p_LPD.  The
register TRANS_VSYNCSHIFT and the bits in TRANS_CONF are now removed, so
make sure we do not set/get these anymore.

Bspec: 69961, 70000
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 42ec78798666..25986bd8fbdd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2658,7 +2658,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
 	}
 
-	if (DISPLAY_VER(display) >= 4)
+	if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
 		intel_de_write(display,
 			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
 			       vsyncshift);
@@ -2799,7 +2799,7 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if (DISPLAY_VER(display) == 2)
+	if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35)
 		return false;
 
 	if (DISPLAY_VER(display) >= 9 ||
@@ -3190,10 +3190,12 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
 	if (display->platform.haswell && crtc_state->dither)
 		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
 
-	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
-		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
-	else
-		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
+	if (DISPLAY_VER(display) < 35) {
+		if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+			val |= TRANSCONF_INTERLACE_IF_ID_ILK;
+		else
+			val |= TRANSCONF_INTERLACE_PF_PD_ILK;
+	}
 
 	if (display->platform.haswell &&
 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)

-- 
2.51.0

[PATCH v3 11/29] drm/i915/xe3p_lpd: Extend Wa_16025573575

[Gustavo Sousa]

Wa_16025573575 also applies to Xe3p_LPD, so let's include it in the IP
version checks.

Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index c528aaa679ca..e38e5e87877c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -49,7 +49,8 @@ void intel_display_wa_apply(struct intel_display *display)
  */
 static bool intel_display_needs_wa_16025573575(struct intel_display *display)
 {
-	return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002;
+	return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002 ||
+		DISPLAY_VERx100(display) == 3500;
 }
 
 /*

-- 
2.51.0

[PATCH v3 12/29] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format

[Gustavo Sousa]

From: Juha-pekka Heikkila <juha-pekka.heikkila@intel.com>

Disable support for odd panning and size in y direction when running on
display version 35 and using semiplanar formats.

Bspec: 68903
Signed-off-by: Juha-pekka Heikkila <juha-pekka.heikkila@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_plane.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 505c776c0585..5105e3278bc4 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -1051,6 +1051,9 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		     DISPLAY_VERx100(display) == 3002) &&
 		     src_x % 2 != 0)
 			hsub = 2;
+
+		if (DISPLAY_VER(display) == 35)
+			vsub = 2;
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;

-- 
2.51.0

[PATCH v3 13/29] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D

[Gustavo Sousa]

Xe3p_LPD has the same behavior as for Xe3_LPD with respect to DMC
context data for pipes C and D, which are lost when their power wells
are disabled.  As such, let's extend the condition for Xe3_LPD in
need_pipedmc_load_mmio() to also catch Xe3p_LPD.

Bspec: 68851
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1b3a9b5608c0..ca70cc4932df 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -718,11 +718,11 @@ static bool need_pipedmc_load_program(struct intel_display *display)
 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)
 {
 	/*
-	 * PTL:
+	 * Xe3_LPD/Xe3p_LPD:
 	 * - pipe A/B DMC doesn't need save/restore
 	 * - pipe C/D DMC is in PG0, needs manual save/restore
 	 */
-	if (DISPLAY_VER(display) == 30)
+	if (IS_DISPLAY_VER(display, 30, 35))
 		return pipe >= PIPE_C;
 
 	/*

-- 
2.51.0

[PATCH v3 14/29] drm/i915/wm: don't use method1 in Xe3p_LPD onwards

[Gustavo Sousa]

From: Luca Coelho <luciano.coelho@intel.com>

Starting from display version 35, we don't need to use method1 to
calculate the watermark values anymore, so skip it.

Bspec: 68985
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 6d050408618c..c888b0896d89 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1812,6 +1812,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 
 	if (wp->y_tiled) {
 		selected_result = max_fixed16(method2, wp->y_tile_minimum);
+	} else if (DISPLAY_VER(display) >= 35) {
+		selected_result = method2;
 	} else {
 		if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
 		     wp->dbuf_block_size < 1) &&

-- 
2.51.0

[PATCH v3 15/29] drm/i915/dram: Add field ecc_impacting_de_bw

[Gustavo Sousa]

Starting with Xe3p_LPD, we now have a new field in MEM_SS_INFO_GLOBAL
that indicates whether the memory has enabled ECC that limits display
bandwidth.  Add the field ecc_impacting_de_bw to struct dram_info to
contain that information and set it appropriately when probing for
memory info.

Currently there are no instructions in Bspec on how to handle that case,
so let's throw a warning if we ever find such a scenario.

v2:
  - s/ecc_impacting_de/ecc_impacting_de_bw/ to be more specific. (Matt
    Atwood)
  - Add warning if ecc_impacting_de_bw is true, since we currently do
    not have instructions on how to handle it. (Matt Roper)
v3:
  - Check on ecc_impacting_de_bw for the warning only for Xe3p_LPD and
    beyond.
  - Change warning macro from drm_WARN_ON_ONCE() to drm_WARN_ON().

Bspec: 69131
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/soc/intel_dram.c   | 4 ++++
 drivers/gpu/drm/i915/soc/intel_dram.h   | 1 +
 4 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 919b25a5fbac..1f6461be50ef 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -805,6 +805,15 @@ void intel_bw_init_hw(struct intel_display *display)
 	if (!HAS_DISPLAY(display))
 		return;
 
+	/*
+	 * Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
+	 * enabled that would impact display bandwidth.  However, so far there
+	 * are no instructions in Bspec on how to handle that case.  Let's
+	 * complain if we ever find such a scenario.
+	 */
+	if (DISPLAY_VER(display) >= 35)
+		drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
+
 	if (DISPLAY_VER(display) >= 30) {
 		if (DISPLAY_VERx100(display) == 3002)
 			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 354ef75ef6a5..5bf3b4ab2baa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1233,6 +1233,7 @@
 #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
 
 #define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
+#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
 #define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
 #define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
 #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 2e16346a6cc0..3e588762709a 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -686,6 +686,7 @@ static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *
 
 static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
 {
+	struct intel_display *display = i915->display;
 	u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
 
 	switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
@@ -724,6 +725,9 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info
 	dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
 	/* PSF GV points not supported in D14+ */
 
+	if (DISPLAY_VER(display) >= 35)
+		dram_info->ecc_impacting_de_bw = REG_FIELD_GET(XE3P_ECC_IMPACTING_DE, val);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h
index 03a973f1c941..8475ee379daa 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.h
+++ b/drivers/gpu/drm/i915/soc/intel_dram.h
@@ -30,6 +30,7 @@ struct dram_info {
 	u8 num_channels;
 	u8 num_qgv_points;
 	u8 num_psf_gv_points;
+	bool ecc_impacting_de_bw; /* Only valid from Xe3p_LPD onward. */
 	bool symmetric_memory;
 	bool has_16gb_dimms;
 };

-- 
2.51.0

Re: [PATCH v3 15/29] drm/i915/dram: Add field ecc_impacting_de_bw

[Matt Roper]

On Mon, Nov 03, 2025 at 02:18:06PM -0300, Gustavo Sousa wrote:
> Starting with Xe3p_LPD, we now have a new field in MEM_SS_INFO_GLOBAL
> that indicates whether the memory has enabled ECC that limits display
> bandwidth.  Add the field ecc_impacting_de_bw to struct dram_info to
> contain that information and set it appropriately when probing for
> memory info.
> 
> Currently there are no instructions in Bspec on how to handle that case,
> so let's throw a warning if we ever find such a scenario.
> 
> v2:
>   - s/ecc_impacting_de/ecc_impacting_de_bw/ to be more specific. (Matt
>     Atwood)
>   - Add warning if ecc_impacting_de_bw is true, since we currently do
>     not have instructions on how to handle it. (Matt Roper)
> v3:
>   - Check on ecc_impacting_de_bw for the warning only for Xe3p_LPD and
>     beyond.
>   - Change warning macro from drm_WARN_ON_ONCE() to drm_WARN_ON().
> 
> Bspec: 69131
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 9 +++++++++
>  drivers/gpu/drm/i915/i915_reg.h         | 1 +
>  drivers/gpu/drm/i915/soc/intel_dram.c   | 4 ++++
>  drivers/gpu/drm/i915/soc/intel_dram.h   | 1 +
>  4 files changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 919b25a5fbac..1f6461be50ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -805,6 +805,15 @@ void intel_bw_init_hw(struct intel_display *display)
>  	if (!HAS_DISPLAY(display))
>  		return;
>  
> +	/*
> +	 * Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
> +	 * enabled that would impact display bandwidth.  However, so far there
> +	 * are no instructions in Bspec on how to handle that case.  Let's
> +	 * complain if we ever find such a scenario.
> +	 */
> +	if (DISPLAY_VER(display) >= 35)
> +		drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
> +
>  	if (DISPLAY_VER(display) >= 30) {
>  		if (DISPLAY_VERx100(display) == 3002)
>  			tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 354ef75ef6a5..5bf3b4ab2baa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1233,6 +1233,7 @@
>  #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
>  
>  #define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> +#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
>  #define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
>  #define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
>  #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 2e16346a6cc0..3e588762709a 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -686,6 +686,7 @@ static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *
>  
>  static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
>  {
> +	struct intel_display *display = i915->display;
>  	u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
>  
>  	switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
> @@ -724,6 +725,9 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info
>  	dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
>  	/* PSF GV points not supported in D14+ */
>  
> +	if (DISPLAY_VER(display) >= 35)
> +		dram_info->ecc_impacting_de_bw = REG_FIELD_GET(XE3P_ECC_IMPACTING_DE, val);

I don't think we really need REG_FIELD_GET() when checking a single bit
to set a bool.  A simple '&' would work as well.  But it doesn't really
hurt anything either so,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


Matt

> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h
> index 03a973f1c941..8475ee379daa 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.h
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.h
> @@ -30,6 +30,7 @@ struct dram_info {
>  	u8 num_channels;
>  	u8 num_qgv_points;
>  	u8 num_psf_gv_points;
> +	bool ecc_impacting_de_bw; /* Only valid from Xe3p_LPD onward. */
>  	bool symmetric_memory;
>  	bool has_16gb_dimms;
>  };
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v3 16/29] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Starting with Xe3p_LPD, we get two new registers and some bits in
existing registers that expose hardware state information at the time of
underrun notification that can be relevant to debugging.

Add the necessary logic in the driver to print the available debug
information when an underrun happens.

Note that the register FBC_DEBUG_STATUS also got a bit to indicate that
the respective FBC was decompressing when the underrun happened, but we
leave that one to be handled in an upcoming change.

v2:
  - Use seq_buf to generate planes string. (Jani)
  - Move definition of FBC_DEBUG_STATUS to intel_fbc_regs.h. (Ville)
  - Change logic for processing UNDERRUN_DBG1 to use loops and move it
    to a separate function. (Gustavo)
  - Always print underrun error message, even if there wouldn't be any
    debug info associated to the underrun. (Gustavo)
v3:
  - Use REG_FIELD_GET() for fields of UNDERRUN_DBG1. (Matt)
  - Move handling of FBC_DEBUG_STATUS to a separate patch that adds
    extra logic to match FBCs by pipe. (Gustavo)

Bspec: 69111, 69561, 74411, 74412
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Co-developed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h  | 20 ++++++
 drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 72 ++++++++++++++++++++++
 2 files changed, 92 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9d71e26a4fa2..c9f8b90faa42 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -882,6 +882,25 @@
 #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */
 #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)	REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
 
+#define _UNDERRUN_DBG1_A				0x70064
+#define _UNDERRUN_DBG1_B				0x71064
+#define UNDERRUN_DBG1(pipe)				_MMIO_PIPE(pipe, \
+								   _UNDERRUN_DBG1_A, \
+								   _UNDERRUN_DBG1_B)
+#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK		REG_GENMASK(29, 24)
+#define   UNDERRUN_DDB_EMPTY_MASK			REG_GENMASK(21, 16)
+#define   UNDERRUN_DBUF_NOT_FILLED_MASK			REG_GENMASK(13, 8)
+#define   UNDERRUN_BELOW_WM0_MASK			REG_GENMASK(5, 0)
+
+#define _UNDERRUN_DBG2_A				0x70068
+#define _UNDERRUN_DBG2_B				0x71068
+#define UNDERRUN_DBG2(pipe)				_MMIO_PIPE(pipe, \
+								   _UNDERRUN_DBG2_A, \
+								   _UNDERRUN_DBG2_B)
+#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN		REG_BIT(31)
+#define   UNDERRUN_PIPE_FRAME_COUNT_MASK		REG_GENMASK(30, 20)
+#define   UNDERRUN_LINE_COUNT_MASK			REG_GENMASK(19, 0)
+
 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
 #define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)
 #define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
@@ -1416,6 +1435,7 @@
 
 #define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
 #define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
+#define  XE3P_UNDERRUN_PKGC				REG_BIT(21)
 
 #define FUSE_STRAP		_MMIO(0x42014)
 #define   ILK_INTERNAL_GRAPHICS_DISABLE	REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index c2ce8461ac9e..1da90c99f93f 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -25,6 +25,8 @@
  *
  */
 
+#include <linux/seq_buf.h>
+
 #include <drm/drm_print.h>
 
 #include "i915_reg.h"
@@ -352,6 +354,73 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
 	return old;
 }
 
+#define UNDERRUN_DBG1_NUM_PLANES 6
+
+static void process_underrun_dbg1(struct intel_display *display,
+				  enum pipe pipe)
+{
+	u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));
+	struct {
+		u32 plane_mask;
+		const char *info;
+	} masks[] = {
+		{ REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val), "DBUF block not valid" },
+		{ REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val), "DDB empty" },
+		{ REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val), "DBUF not completely filled" },
+		{ REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val), "DBUF below WM0" },
+	};
+	DECLARE_SEQ_BUF(planes_desc, 32);
+
+	intel_de_write(display, UNDERRUN_DBG1(pipe), val);
+
+	for (int i = 0; i < ARRAY_SIZE(masks); i++) {
+		if (!masks[i].plane_mask)
+			continue;
+
+		seq_buf_clear(&planes_desc);
+
+		for (int j = 0; j < UNDERRUN_DBG1_NUM_PLANES; j++) {
+			if (!(masks[i].plane_mask & REG_BIT(j)))
+				continue;
+
+			if (j == 0)
+				seq_buf_puts(&planes_desc, "[C]");
+			else
+				seq_buf_printf(&planes_desc, "[%d]", j);
+		}
+
+		drm_err(display->drm,
+			"Pipe %c FIFO underrun info: %s on planes: %s\n",
+			pipe_name(pipe), masks[i].info, seq_buf_str(&planes_desc));
+
+		drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc));
+	}
+}
+
+static void xe3p_lpd_log_underrun(struct intel_display *display,
+				  enum pipe pipe)
+{
+	u32 val;
+
+	process_underrun_dbg1(display, pipe);
+
+	val = intel_de_read(display, UNDERRUN_DBG2(pipe));
+	if (val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN) {
+		intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
+		drm_err(display->drm, "Pipe %c FIFO underrun info: Frame count: %u, Line count: %u\n",
+			pipe_name(pipe),
+			REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val),
+			REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val));
+	}
+
+	val = intel_de_read(display, GEN12_DCPR_STATUS_1);
+	if (val & XE3P_UNDERRUN_PKGC) {
+		intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
+		drm_err(display->drm, "Pipe %c FIFO underrun info: Pkgc blocking memory\n",
+			pipe_name(pipe));
+	}
+}
+
 /**
  * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
  * @display: display device instance
@@ -379,6 +448,9 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
 		trace_intel_cpu_fifo_underrun(display, pipe);
 
 		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
+
+		if (DISPLAY_VER(display) >= 35)
+			xe3p_lpd_log_underrun(display, pipe);
 	}
 
 	intel_fbc_handle_fifo_underrun_irq(display);

-- 
2.51.0

Re: [PATCH v3 16/29] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints

[Matt Roper]

On Mon, Nov 03, 2025 at 02:18:07PM -0300, Gustavo Sousa wrote:
> From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> 
> Starting with Xe3p_LPD, we get two new registers and some bits in
> existing registers that expose hardware state information at the time of
> underrun notification that can be relevant to debugging.
> 
> Add the necessary logic in the driver to print the available debug
> information when an underrun happens.
> 
> Note that the register FBC_DEBUG_STATUS also got a bit to indicate that
> the respective FBC was decompressing when the underrun happened, but we
> leave that one to be handled in an upcoming change.
> 
> v2:
>   - Use seq_buf to generate planes string. (Jani)
>   - Move definition of FBC_DEBUG_STATUS to intel_fbc_regs.h. (Ville)
>   - Change logic for processing UNDERRUN_DBG1 to use loops and move it
>     to a separate function. (Gustavo)
>   - Always print underrun error message, even if there wouldn't be any
>     debug info associated to the underrun. (Gustavo)
> v3:
>   - Use REG_FIELD_GET() for fields of UNDERRUN_DBG1. (Matt)
>   - Move handling of FBC_DEBUG_STATUS to a separate patch that adds
>     extra logic to match FBCs by pipe. (Gustavo)
> 
> Bspec: 69111, 69561, 74411, 74412
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> Co-developed-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h  | 20 ++++++
>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 72 ++++++++++++++++++++++
>  2 files changed, 92 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9d71e26a4fa2..c9f8b90faa42 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -882,6 +882,25 @@
>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */
>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)	REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
>  
> +#define _UNDERRUN_DBG1_A				0x70064
> +#define _UNDERRUN_DBG1_B				0x71064
> +#define UNDERRUN_DBG1(pipe)				_MMIO_PIPE(pipe, \
> +								   _UNDERRUN_DBG1_A, \
> +								   _UNDERRUN_DBG1_B)
> +#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK		REG_GENMASK(29, 24)
> +#define   UNDERRUN_DDB_EMPTY_MASK			REG_GENMASK(21, 16)
> +#define   UNDERRUN_DBUF_NOT_FILLED_MASK			REG_GENMASK(13, 8)
> +#define   UNDERRUN_BELOW_WM0_MASK			REG_GENMASK(5, 0)
> +
> +#define _UNDERRUN_DBG2_A				0x70068
> +#define _UNDERRUN_DBG2_B				0x71068
> +#define UNDERRUN_DBG2(pipe)				_MMIO_PIPE(pipe, \
> +								   _UNDERRUN_DBG2_A, \
> +								   _UNDERRUN_DBG2_B)
> +#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN		REG_BIT(31)
> +#define   UNDERRUN_PIPE_FRAME_COUNT_MASK		REG_GENMASK(30, 20)
> +#define   UNDERRUN_LINE_COUNT_MASK			REG_GENMASK(19, 0)
> +
>  #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
>  #define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)
>  #define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
> @@ -1416,6 +1435,7 @@
>  
>  #define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
>  #define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
> +#define  XE3P_UNDERRUN_PKGC				REG_BIT(21)
>  
>  #define FUSE_STRAP		_MMIO(0x42014)
>  #define   ILK_INTERNAL_GRAPHICS_DISABLE	REG_BIT(31)
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index c2ce8461ac9e..1da90c99f93f 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -25,6 +25,8 @@
>   *
>   */
>  
> +#include <linux/seq_buf.h>
> +
>  #include <drm/drm_print.h>
>  
>  #include "i915_reg.h"
> @@ -352,6 +354,73 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
>  	return old;
>  }
>  
> +#define UNDERRUN_DBG1_NUM_PLANES 6
> +
> +static void process_underrun_dbg1(struct intel_display *display,
> +				  enum pipe pipe)
> +{
> +	u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));
> +	struct {
> +		u32 plane_mask;
> +		const char *info;
> +	} masks[] = {
> +		{ REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val), "DBUF block not valid" },
> +		{ REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val), "DDB empty" },
> +		{ REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val), "DBUF not completely filled" },
> +		{ REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val), "DBUF below WM0" },
> +	};
> +	DECLARE_SEQ_BUF(planes_desc, 32);
> +
> +	intel_de_write(display, UNDERRUN_DBG1(pipe), val);
> +
> +	for (int i = 0; i < ARRAY_SIZE(masks); i++) {
> +		if (!masks[i].plane_mask)
> +			continue;
> +
> +		seq_buf_clear(&planes_desc);
> +
> +		for (int j = 0; j < UNDERRUN_DBG1_NUM_PLANES; j++) {
> +			if (!(masks[i].plane_mask & REG_BIT(j)))
> +				continue;
> +
> +			if (j == 0)
> +				seq_buf_puts(&planes_desc, "[C]");
> +			else
> +				seq_buf_printf(&planes_desc, "[%d]", j);
> +		}
> +
> +		drm_err(display->drm,
> +			"Pipe %c FIFO underrun info: %s on planes: %s\n",
> +			pipe_name(pipe), masks[i].info, seq_buf_str(&planes_desc));
> +
> +		drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc));
> +	}
> +}
> +
> +static void xe3p_lpd_log_underrun(struct intel_display *display,
> +				  enum pipe pipe)
> +{
> +	u32 val;
> +
> +	process_underrun_dbg1(display, pipe);
> +
> +	val = intel_de_read(display, UNDERRUN_DBG2(pipe));
> +	if (val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN) {
> +		intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
> +		drm_err(display->drm, "Pipe %c FIFO underrun info: Frame count: %u, Line count: %u\n",
> +			pipe_name(pipe),
> +			REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val),
> +			REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val));
> +	}
> +
> +	val = intel_de_read(display, GEN12_DCPR_STATUS_1);
> +	if (val & XE3P_UNDERRUN_PKGC) {
> +		intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
> +		drm_err(display->drm, "Pipe %c FIFO underrun info: Pkgc blocking memory\n",
> +			pipe_name(pipe));

This is a global (not per-pipe) register here.  So if memory is
unavailable due to a package C-state, then presumably all of our active
pipes are going to be failing to fetch data (and hitting underruns)
because of this.  If we clear the sticky bit here, then the message may
only appear once.  I'd remove the "Pipe %c" prefix here so that we're
not blaming one specific pipe.


Matt

> +	}
> +}
> +
>  /**
>   * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
>   * @display: display device instance
> @@ -379,6 +448,9 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
>  		trace_intel_cpu_fifo_underrun(display, pipe);
>  
>  		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
> +
> +		if (DISPLAY_VER(display) >= 35)
> +			xe3p_lpd_log_underrun(display, pipe);
>  	}
>  
>  	intel_fbc_handle_fifo_underrun_irq(display);
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v3 16/29] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints

[Gustavo Sousa]

Quoting Matt Roper (2025-11-03 18:51:11-03:00)
>On Mon, Nov 03, 2025 at 02:18:07PM -0300, Gustavo Sousa wrote:
>> From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
>> 
>> Starting with Xe3p_LPD, we get two new registers and some bits in
>> existing registers that expose hardware state information at the time of
>> underrun notification that can be relevant to debugging.
>> 
>> Add the necessary logic in the driver to print the available debug
>> information when an underrun happens.
>> 
>> Note that the register FBC_DEBUG_STATUS also got a bit to indicate that
>> the respective FBC was decompressing when the underrun happened, but we
>> leave that one to be handled in an upcoming change.
>> 
>> v2:
>>   - Use seq_buf to generate planes string. (Jani)
>>   - Move definition of FBC_DEBUG_STATUS to intel_fbc_regs.h. (Ville)
>>   - Change logic for processing UNDERRUN_DBG1 to use loops and move it
>>     to a separate function. (Gustavo)
>>   - Always print underrun error message, even if there wouldn't be any
>>     debug info associated to the underrun. (Gustavo)
>> v3:
>>   - Use REG_FIELD_GET() for fields of UNDERRUN_DBG1. (Matt)
>>   - Move handling of FBC_DEBUG_STATUS to a separate patch that adds
>>     extra logic to match FBCs by pipe. (Gustavo)
>> 
>> Bspec: 69111, 69561, 74411, 74412
>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
>> Co-developed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_regs.h  | 20 ++++++
>>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 72 ++++++++++++++++++++++
>>  2 files changed, 92 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> index 9d71e26a4fa2..c9f8b90faa42 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> @@ -882,6 +882,25 @@
>>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK                REG_GENMASK(2, 0) /* tgl+ */
>>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)        REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
>>  
>> +#define _UNDERRUN_DBG1_A                                0x70064
>> +#define _UNDERRUN_DBG1_B                                0x71064
>> +#define UNDERRUN_DBG1(pipe)                                _MMIO_PIPE(pipe, \
>> +                                                                   _UNDERRUN_DBG1_A, \
>> +                                                                   _UNDERRUN_DBG1_B)
>> +#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK                REG_GENMASK(29, 24)
>> +#define   UNDERRUN_DDB_EMPTY_MASK                        REG_GENMASK(21, 16)
>> +#define   UNDERRUN_DBUF_NOT_FILLED_MASK                        REG_GENMASK(13, 8)
>> +#define   UNDERRUN_BELOW_WM0_MASK                        REG_GENMASK(5, 0)
>> +
>> +#define _UNDERRUN_DBG2_A                                0x70068
>> +#define _UNDERRUN_DBG2_B                                0x71068
>> +#define UNDERRUN_DBG2(pipe)                                _MMIO_PIPE(pipe, \
>> +                                                                   _UNDERRUN_DBG2_A, \
>> +                                                                   _UNDERRUN_DBG2_B)
>> +#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN                REG_BIT(31)
>> +#define   UNDERRUN_PIPE_FRAME_COUNT_MASK                REG_GENMASK(30, 20)
>> +#define   UNDERRUN_LINE_COUNT_MASK                        REG_GENMASK(19, 0)
>> +
>>  #define DPINVGTT                                _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
>>  #define   DPINVGTT_EN_MASK_CHV                                REG_GENMASK(27, 16)
>>  #define   DPINVGTT_EN_MASK_VLV                                REG_GENMASK(23, 16)
>> @@ -1416,6 +1435,7 @@
>>  
>>  #define GEN12_DCPR_STATUS_1                                _MMIO(0x46440)
>>  #define  XELPDP_PMDEMAND_INFLIGHT_STATUS                REG_BIT(26)
>> +#define  XE3P_UNDERRUN_PKGC                                REG_BIT(21)
>>  
>>  #define FUSE_STRAP                _MMIO(0x42014)
>>  #define   ILK_INTERNAL_GRAPHICS_DISABLE        REG_BIT(31)
>> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
>> index c2ce8461ac9e..1da90c99f93f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
>> @@ -25,6 +25,8 @@
>>   *
>>   */
>>  
>> +#include <linux/seq_buf.h>
>> +
>>  #include <drm/drm_print.h>
>>  
>>  #include "i915_reg.h"
>> @@ -352,6 +354,73 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
>>          return old;
>>  }
>>  
>> +#define UNDERRUN_DBG1_NUM_PLANES 6
>> +
>> +static void process_underrun_dbg1(struct intel_display *display,
>> +                                  enum pipe pipe)
>> +{
>> +        u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));
>> +        struct {
>> +                u32 plane_mask;
>> +                const char *info;
>> +        } masks[] = {
>> +                { REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val), "DBUF block not valid" },
>> +                { REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val), "DDB empty" },
>> +                { REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val), "DBUF not completely filled" },
>> +                { REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val), "DBUF below WM0" },
>> +        };
>> +        DECLARE_SEQ_BUF(planes_desc, 32);
>> +
>> +        intel_de_write(display, UNDERRUN_DBG1(pipe), val);
>> +
>> +        for (int i = 0; i < ARRAY_SIZE(masks); i++) {
>> +                if (!masks[i].plane_mask)
>> +                        continue;
>> +
>> +                seq_buf_clear(&planes_desc);
>> +
>> +                for (int j = 0; j < UNDERRUN_DBG1_NUM_PLANES; j++) {
>> +                        if (!(masks[i].plane_mask & REG_BIT(j)))
>> +                                continue;
>> +
>> +                        if (j == 0)
>> +                                seq_buf_puts(&planes_desc, "[C]");
>> +                        else
>> +                                seq_buf_printf(&planes_desc, "[%d]", j);
>> +                }
>> +
>> +                drm_err(display->drm,
>> +                        "Pipe %c FIFO underrun info: %s on planes: %s\n",
>> +                        pipe_name(pipe), masks[i].info, seq_buf_str(&planes_desc));
>> +
>> +                drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc));
>> +        }
>> +}
>> +
>> +static void xe3p_lpd_log_underrun(struct intel_display *display,
>> +                                  enum pipe pipe)
>> +{
>> +        u32 val;
>> +
>> +        process_underrun_dbg1(display, pipe);
>> +
>> +        val = intel_de_read(display, UNDERRUN_DBG2(pipe));
>> +        if (val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN) {
>> +                intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
>> +                drm_err(display->drm, "Pipe %c FIFO underrun info: Frame count: %u, Line count: %u\n",
>> +                        pipe_name(pipe),
>> +                        REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val),
>> +                        REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val));
>> +        }
>> +
>> +        val = intel_de_read(display, GEN12_DCPR_STATUS_1);
>> +        if (val & XE3P_UNDERRUN_PKGC) {
>> +                intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
>> +                drm_err(display->drm, "Pipe %c FIFO underrun info: Pkgc blocking memory\n",
>> +                        pipe_name(pipe));
>
>This is a global (not per-pipe) register here.  So if memory is
>unavailable due to a package C-state, then presumably all of our active
>pipes are going to be failing to fetch data (and hitting underruns)
>because of this.  If we clear the sticky bit here, then the message may
>only appear once.  I'd remove the "Pipe %c" prefix here so that we're
>not blaming one specific pipe.

Yeah, good point.

Now, one thing that is bothering me is that we would be showing this
message in between pipe i and pipe (i+k) underrun error messages.  But
I'm not sure refactoring the current code so that we "isolate" this
message is worth the trouble.

What if we replace "Pipe %c" with "General", so that we are explicit
that this is general and not specific to the pipe?

--
Gustavo Sousa

>
>
>Matt
>
>> +        }
>> +}
>> +
>>  /**
>>   * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
>>   * @display: display device instance
>> @@ -379,6 +448,9 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
>>                  trace_intel_cpu_fifo_underrun(display, pipe);
>>  
>>                  drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
>> +
>> +                if (DISPLAY_VER(display) >= 35)
>> +                        xe3p_lpd_log_underrun(display, pipe);
>>          }
>>  
>>          intel_fbc_handle_fifo_underrun_irq(display);
>> 
>> -- 
>> 2.51.0
>> 
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [PATCH v3 16/29] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints

[Gustavo Sousa]

Quoting Gustavo Sousa (2025-11-05 11:42:54-03:00)
>Quoting Matt Roper (2025-11-03 18:51:11-03:00)
>>On Mon, Nov 03, 2025 at 02:18:07PM -0300, Gustavo Sousa wrote:
>>> From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
>>> 
>>> Starting with Xe3p_LPD, we get two new registers and some bits in
>>> existing registers that expose hardware state information at the time of
>>> underrun notification that can be relevant to debugging.
>>> 
>>> Add the necessary logic in the driver to print the available debug
>>> information when an underrun happens.
>>> 
>>> Note that the register FBC_DEBUG_STATUS also got a bit to indicate that
>>> the respective FBC was decompressing when the underrun happened, but we
>>> leave that one to be handled in an upcoming change.
>>> 
>>> v2:
>>>   - Use seq_buf to generate planes string. (Jani)
>>>   - Move definition of FBC_DEBUG_STATUS to intel_fbc_regs.h. (Ville)
>>>   - Change logic for processing UNDERRUN_DBG1 to use loops and move it
>>>     to a separate function. (Gustavo)
>>>   - Always print underrun error message, even if there wouldn't be any
>>>     debug info associated to the underrun. (Gustavo)
>>> v3:
>>>   - Use REG_FIELD_GET() for fields of UNDERRUN_DBG1. (Matt)
>>>   - Move handling of FBC_DEBUG_STATUS to a separate patch that adds
>>>     extra logic to match FBCs by pipe. (Gustavo)
>>> 
>>> Bspec: 69111, 69561, 74411, 74412
>>> Cc: Jani Nikula <jani.nikula@linux.intel.com>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
>>> Co-developed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/display/intel_display_regs.h  | 20 ++++++
>>>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 72 ++++++++++++++++++++++
>>>  2 files changed, 92 insertions(+)
>>> 
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
>>> index 9d71e26a4fa2..c9f8b90faa42 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
>>> @@ -882,6 +882,25 @@
>>>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK                REG_GENMASK(2, 0) /* tgl+ */
>>>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)        REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
>>>  
>>> +#define _UNDERRUN_DBG1_A                                0x70064
>>> +#define _UNDERRUN_DBG1_B                                0x71064
>>> +#define UNDERRUN_DBG1(pipe)                                _MMIO_PIPE(pipe, \
>>> +                                                                   _UNDERRUN_DBG1_A, \
>>> +                                                                   _UNDERRUN_DBG1_B)
>>> +#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK                REG_GENMASK(29, 24)
>>> +#define   UNDERRUN_DDB_EMPTY_MASK                        REG_GENMASK(21, 16)
>>> +#define   UNDERRUN_DBUF_NOT_FILLED_MASK                        REG_GENMASK(13, 8)
>>> +#define   UNDERRUN_BELOW_WM0_MASK                        REG_GENMASK(5, 0)
>>> +
>>> +#define _UNDERRUN_DBG2_A                                0x70068
>>> +#define _UNDERRUN_DBG2_B                                0x71068
>>> +#define UNDERRUN_DBG2(pipe)                                _MMIO_PIPE(pipe, \
>>> +                                                                   _UNDERRUN_DBG2_A, \
>>> +                                                                   _UNDERRUN_DBG2_B)
>>> +#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN                REG_BIT(31)
>>> +#define   UNDERRUN_PIPE_FRAME_COUNT_MASK                REG_GENMASK(30, 20)
>>> +#define   UNDERRUN_LINE_COUNT_MASK                        REG_GENMASK(19, 0)
>>> +
>>>  #define DPINVGTT                                _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
>>>  #define   DPINVGTT_EN_MASK_CHV                                REG_GENMASK(27, 16)
>>>  #define   DPINVGTT_EN_MASK_VLV                                REG_GENMASK(23, 16)
>>> @@ -1416,6 +1435,7 @@
>>>  
>>>  #define GEN12_DCPR_STATUS_1                                _MMIO(0x46440)
>>>  #define  XELPDP_PMDEMAND_INFLIGHT_STATUS                REG_BIT(26)
>>> +#define  XE3P_UNDERRUN_PKGC                                REG_BIT(21)
>>>  
>>>  #define FUSE_STRAP                _MMIO(0x42014)
>>>  #define   ILK_INTERNAL_GRAPHICS_DISABLE        REG_BIT(31)
>>> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
>>> index c2ce8461ac9e..1da90c99f93f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
>>> @@ -25,6 +25,8 @@
>>>   *
>>>   */
>>>  
>>> +#include <linux/seq_buf.h>
>>> +
>>>  #include <drm/drm_print.h>
>>>  
>>>  #include "i915_reg.h"
>>> @@ -352,6 +354,73 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
>>>          return old;
>>>  }
>>>  
>>> +#define UNDERRUN_DBG1_NUM_PLANES 6
>>> +
>>> +static void process_underrun_dbg1(struct intel_display *display,
>>> +                                  enum pipe pipe)
>>> +{
>>> +        u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));
>>> +        struct {
>>> +                u32 plane_mask;
>>> +                const char *info;
>>> +        } masks[] = {
>>> +                { REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val), "DBUF block not valid" },
>>> +                { REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val), "DDB empty" },
>>> +                { REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val), "DBUF not completely filled" },
>>> +                { REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val), "DBUF below WM0" },
>>> +        };
>>> +        DECLARE_SEQ_BUF(planes_desc, 32);
>>> +
>>> +        intel_de_write(display, UNDERRUN_DBG1(pipe), val);
>>> +
>>> +        for (int i = 0; i < ARRAY_SIZE(masks); i++) {
>>> +                if (!masks[i].plane_mask)
>>> +                        continue;
>>> +
>>> +                seq_buf_clear(&planes_desc);
>>> +
>>> +                for (int j = 0; j < UNDERRUN_DBG1_NUM_PLANES; j++) {
>>> +                        if (!(masks[i].plane_mask & REG_BIT(j)))
>>> +                                continue;
>>> +
>>> +                        if (j == 0)
>>> +                                seq_buf_puts(&planes_desc, "[C]");
>>> +                        else
>>> +                                seq_buf_printf(&planes_desc, "[%d]", j);
>>> +                }
>>> +
>>> +                drm_err(display->drm,
>>> +                        "Pipe %c FIFO underrun info: %s on planes: %s\n",
>>> +                        pipe_name(pipe), masks[i].info, seq_buf_str(&planes_desc));
>>> +
>>> +                drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc));
>>> +        }
>>> +}
>>> +
>>> +static void xe3p_lpd_log_underrun(struct intel_display *display,
>>> +                                  enum pipe pipe)
>>> +{
>>> +        u32 val;
>>> +
>>> +        process_underrun_dbg1(display, pipe);
>>> +
>>> +        val = intel_de_read(display, UNDERRUN_DBG2(pipe));
>>> +        if (val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN) {
>>> +                intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
>>> +                drm_err(display->drm, "Pipe %c FIFO underrun info: Frame count: %u, Line count: %u\n",
>>> +                        pipe_name(pipe),
>>> +                        REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val),
>>> +                        REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val));
>>> +        }
>>> +
>>> +        val = intel_de_read(display, GEN12_DCPR_STATUS_1);
>>> +        if (val & XE3P_UNDERRUN_PKGC) {
>>> +                intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
>>> +                drm_err(display->drm, "Pipe %c FIFO underrun info: Pkgc blocking memory\n",
>>> +                        pipe_name(pipe));
>>
>>This is a global (not per-pipe) register here.  So if memory is
>>unavailable due to a package C-state, then presumably all of our active
>>pipes are going to be failing to fetch data (and hitting underruns)
>>because of this.  If we clear the sticky bit here, then the message may
>>only appear once.  I'd remove the "Pipe %c" prefix here so that we're
>>not blaming one specific pipe.
>
>Yeah, good point.
>
>Now, one thing that is bothering me is that we would be showing this
>message in between pipe i and pipe (i+k) underrun error messages.  But
>I'm not sure refactoring the current code so that we "isolate" this
>message is worth the trouble.
>
>What if we replace "Pipe %c" with "General", so that we are explicit
>that this is general and not specific to the pipe?

Hm.. By the way, I think this patch still needs some rework.  We are
only clearing the stick bits when underrung reporting is enabled.  This
means that there is the possibility that we get stale bits, from a
previous underrun that was not reported.

Let me rework this.

--
Gustavo Sousa

>
>--
>Gustavo Sousa
>
>>
>>
>>Matt
>>
>>> +        }
>>> +}
>>> +
>>>  /**
>>>   * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
>>>   * @display: display device instance
>>> @@ -379,6 +448,9 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
>>>                  trace_intel_cpu_fifo_underrun(display, pipe);
>>>  
>>>                  drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
>>> +
>>> +                if (DISPLAY_VER(display) >= 35)
>>> +                        xe3p_lpd_log_underrun(display, pipe);
>>>          }
>>>  
>>>          intel_fbc_handle_fifo_underrun_irq(display);
>>> 
>>> -- 
>>> 2.51.0
>>> 
>>
>>-- 
>>Matt Roper
>>Graphics Software Engineer
>>Linux GPU Platform Enablement
>>Intel Corporation

[PATCH v3 17/29] drm/i915/xe3p_lpd: Log FBC-related debug info for PIPE underrun

[Gustavo Sousa]

Xe3p_LPD added registers and bits to provide debug information at the
time a FIFO underrun happens.  We have already handled most of them,
with FBC being left out.  Let's handle it now.

For FBC, a bit was added to FBC_DEBUG_STATUS that indicates that the
respective FBC was decompressing when a FIFO underrun happened.  Add the
logic log that info.

Bspec: 69561
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c           | 45 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_fbc.h           |  2 +
 drivers/gpu/drm/i915/display/intel_fbc_regs.h      |  2 +
 drivers/gpu/drm/i915/display/intel_fifo_underrun.c |  1 +
 4 files changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index a1e3083022ee..24b72951ea3c 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -129,6 +129,11 @@ struct intel_fbc {
 	const char *no_fbc_reason;
 };
 
+static char fbc_name(enum intel_fbc_id fbc_id)
+{
+	return 'A' + fbc_id;
+}
+
 /* plane stride in pixels */
 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
 {
@@ -2119,6 +2124,46 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)
 		__intel_fbc_handle_fifo_underrun_irq(fbc);
 }
 
+static unsigned int pipe_to_fbc_mask(struct intel_display *display, enum pipe pipe)
+{
+	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
+	struct intel_plane *plane;
+	unsigned int mask = 0;
+
+	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
+		if (plane->fbc)
+			mask |= BIT(plane->fbc->id);
+	}
+
+	return mask;
+}
+
+static void __intel_fbc_log_fifo_underrun(struct intel_fbc *fbc, enum pipe pipe)
+{
+	struct intel_display *display = fbc->display;
+	u32 val;
+
+	val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));
+	if (val & FBC_UNDERRUN_DECMPR) {
+		intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR);
+		drm_err(display->drm, "Pipe %c FIFO underrun info: FBC %c decompressing\n",
+			pipe_name(pipe), fbc_name(fbc->id));
+	}
+}
+
+void intel_fbc_log_fifo_underrun(struct intel_display *display, enum pipe pipe)
+{
+	struct intel_fbc *fbc;
+	enum intel_fbc_id fbc_id;
+	unsigned int fbc_mask;
+
+	fbc_mask = pipe_to_fbc_mask(display, pipe);
+
+	for_each_intel_fbc(display, fbc, fbc_id)
+		if (fbc_mask & BIT(fbc_id))
+			__intel_fbc_log_fifo_underrun(fbc, pipe);
+}
+
 /*
  * The DDX driver changes its behavior depending on the value it reads from
  * i915.enable_fbc, so sanitize it by translating the default value into either
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 91424563206a..d34282cbe971 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -9,6 +9,7 @@
 #include <linux/types.h>
 
 enum fb_op_origin;
+enum pipe;
 struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
@@ -46,6 +47,7 @@ void intel_fbc_flush(struct intel_display *display,
 		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
 void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
+void intel_fbc_log_fifo_underrun(struct intel_display *display, enum pipe pipe);
 void intel_fbc_reset_underrun(struct intel_display *display);
 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
 void intel_fbc_debugfs_register(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
index b1d0161a3196..77d8321c4fb3 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -88,6 +88,8 @@
 #define DPFC_FENCE_YOFF			_MMIO(0x3218)
 #define ILK_DPFC_FENCE_YOFF(fbc_id)	_MMIO_PIPE((fbc_id), 0x43218, 0x43258)
 #define DPFC_CHICKEN			_MMIO(0x3224)
+#define FBC_DEBUG_STATUS(fbc_id)	_MMIO_PIPE((fbc_id), 0x43220, 0x43260)
+#define   FBC_UNDERRUN_DECMPR			REG_BIT(27)
 #define ILK_DPFC_CHICKEN(fbc_id)	_MMIO_PIPE((fbc_id), 0x43224, 0x43264)
 #define   DPFC_HT_MODIFY			REG_BIT(31) /* pre-ivb */
 #define   DPFC_NUKE_ON_ANY_MODIFICATION		REG_BIT(23) /* bdw+ */
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 1da90c99f93f..d0dbc4faa3f4 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -403,6 +403,7 @@ static void xe3p_lpd_log_underrun(struct intel_display *display,
 	u32 val;
 
 	process_underrun_dbg1(display, pipe);
+	intel_fbc_log_fifo_underrun(display, pipe);
 
 	val = intel_de_read(display, UNDERRUN_DBG2(pipe));
 	if (val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN) {

-- 
2.51.0

Re: [PATCH v3 17/29] drm/i915/xe3p_lpd: Log FBC-related debug info for PIPE underrun

[Matt Roper]

On Mon, Nov 03, 2025 at 02:18:08PM -0300, Gustavo Sousa wrote:
> Xe3p_LPD added registers and bits to provide debug information at the
> time a FIFO underrun happens.  We have already handled most of them,
> with FBC being left out.  Let's handle it now.
> 
> For FBC, a bit was added to FBC_DEBUG_STATUS that indicates that the
> respective FBC was decompressing when a FIFO underrun happened.  Add the
> logic log that info.
> 
> Bspec: 69561
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c           | 45 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_fbc.h           |  2 +
>  drivers/gpu/drm/i915/display/intel_fbc_regs.h      |  2 +
>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c |  1 +
>  4 files changed, 50 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a1e3083022ee..24b72951ea3c 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -129,6 +129,11 @@ struct intel_fbc {
>  	const char *no_fbc_reason;
>  };
>  
> +static char fbc_name(enum intel_fbc_id fbc_id)
> +{
> +	return 'A' + fbc_id;
> +}
> +
>  /* plane stride in pixels */
>  static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
>  {
> @@ -2119,6 +2124,46 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)
>  		__intel_fbc_handle_fifo_underrun_irq(fbc);
>  }
>  
> +static unsigned int pipe_to_fbc_mask(struct intel_display *display, enum pipe pipe)
> +{
> +	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
> +	struct intel_plane *plane;
> +	unsigned int mask = 0;
> +
> +	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
> +		if (plane->fbc)
> +			mask |= BIT(plane->fbc->id);
> +	}
> +
> +	return mask;
> +}

I notice that there's also a skl_fbc_id_for_pipe in
skl_universal_plane.c that relies on the current hardware design of one
FBC unit per pipe.  What you have here is a lot more general and
future-proof if the hardware someday starts allowing multiple units per
pipe.  I don't have strong feelings about whether the simple approach or
the future-proof approach is better, but we might want to consolidate to
a single function that can be used in both places so that there isn't
confusion about why there are two ways to do the same thing in different
parts of the driver.


Matt

> +
> +static void __intel_fbc_log_fifo_underrun(struct intel_fbc *fbc, enum pipe pipe)
> +{
> +	struct intel_display *display = fbc->display;
> +	u32 val;
> +
> +	val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));
> +	if (val & FBC_UNDERRUN_DECMPR) {
> +		intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR);
> +		drm_err(display->drm, "Pipe %c FIFO underrun info: FBC %c decompressing\n",
> +			pipe_name(pipe), fbc_name(fbc->id));
> +	}
> +}
> +
> +void intel_fbc_log_fifo_underrun(struct intel_display *display, enum pipe pipe)
> +{
> +	struct intel_fbc *fbc;
> +	enum intel_fbc_id fbc_id;
> +	unsigned int fbc_mask;
> +
> +	fbc_mask = pipe_to_fbc_mask(display, pipe);
> +
> +	for_each_intel_fbc(display, fbc, fbc_id)
> +		if (fbc_mask & BIT(fbc_id))
> +			__intel_fbc_log_fifo_underrun(fbc, pipe);
> +}
> +
>  /*
>   * The DDX driver changes its behavior depending on the value it reads from
>   * i915.enable_fbc, so sanitize it by translating the default value into either
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 91424563206a..d34282cbe971 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -9,6 +9,7 @@
>  #include <linux/types.h>
>  
>  enum fb_op_origin;
> +enum pipe;
>  struct intel_atomic_state;
>  struct intel_crtc;
>  struct intel_crtc_state;
> @@ -46,6 +47,7 @@ void intel_fbc_flush(struct intel_display *display,
>  		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
>  void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
>  void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
> +void intel_fbc_log_fifo_underrun(struct intel_display *display, enum pipe pipe);
>  void intel_fbc_reset_underrun(struct intel_display *display);
>  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
>  void intel_fbc_debugfs_register(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> index b1d0161a3196..77d8321c4fb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -88,6 +88,8 @@
>  #define DPFC_FENCE_YOFF			_MMIO(0x3218)
>  #define ILK_DPFC_FENCE_YOFF(fbc_id)	_MMIO_PIPE((fbc_id), 0x43218, 0x43258)
>  #define DPFC_CHICKEN			_MMIO(0x3224)
> +#define FBC_DEBUG_STATUS(fbc_id)	_MMIO_PIPE((fbc_id), 0x43220, 0x43260)
> +#define   FBC_UNDERRUN_DECMPR			REG_BIT(27)
>  #define ILK_DPFC_CHICKEN(fbc_id)	_MMIO_PIPE((fbc_id), 0x43224, 0x43264)
>  #define   DPFC_HT_MODIFY			REG_BIT(31) /* pre-ivb */
>  #define   DPFC_NUKE_ON_ANY_MODIFICATION		REG_BIT(23) /* bdw+ */
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index 1da90c99f93f..d0dbc4faa3f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -403,6 +403,7 @@ static void xe3p_lpd_log_underrun(struct intel_display *display,
>  	u32 val;
>  
>  	process_underrun_dbg1(display, pipe);
> +	intel_fbc_log_fifo_underrun(display, pipe);
>  
>  	val = intel_de_read(display, UNDERRUN_DBG2(pipe));
>  	if (val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN) {
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v3 17/29] drm/i915/xe3p_lpd: Log FBC-related debug info for PIPE underrun

[Gustavo Sousa]

Quoting Matt Roper (2025-11-03 19:30:28-03:00)
>On Mon, Nov 03, 2025 at 02:18:08PM -0300, Gustavo Sousa wrote:
>> Xe3p_LPD added registers and bits to provide debug information at the
>> time a FIFO underrun happens.  We have already handled most of them,
>> with FBC being left out.  Let's handle it now.
>> 
>> For FBC, a bit was added to FBC_DEBUG_STATUS that indicates that the
>> respective FBC was decompressing when a FIFO underrun happened.  Add the
>> logic log that info.
>> 
>> Bspec: 69561
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_fbc.c           | 45 ++++++++++++++++++++++
>>  drivers/gpu/drm/i915/display/intel_fbc.h           |  2 +
>>  drivers/gpu/drm/i915/display/intel_fbc_regs.h      |  2 +
>>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c |  1 +
>>  4 files changed, 50 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
>> index a1e3083022ee..24b72951ea3c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> @@ -129,6 +129,11 @@ struct intel_fbc {
>>          const char *no_fbc_reason;
>>  };
>>  
>> +static char fbc_name(enum intel_fbc_id fbc_id)
>> +{
>> +        return 'A' + fbc_id;
>> +}
>> +
>>  /* plane stride in pixels */
>>  static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
>>  {
>> @@ -2119,6 +2124,46 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)
>>                  __intel_fbc_handle_fifo_underrun_irq(fbc);
>>  }
>>  
>> +static unsigned int pipe_to_fbc_mask(struct intel_display *display, enum pipe pipe)
>> +{
>> +        struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
>> +        struct intel_plane *plane;
>> +        unsigned int mask = 0;
>> +
>> +        for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
>> +                if (plane->fbc)
>> +                        mask |= BIT(plane->fbc->id);
>> +        }
>> +
>> +        return mask;
>> +}
>
>I notice that there's also a skl_fbc_id_for_pipe in
>skl_universal_plane.c that relies on the current hardware design of one
>FBC unit per pipe.  What you have here is a lot more general and
>future-proof if the hardware someday starts allowing multiple units per
>pipe.  I don't have strong feelings about whether the simple approach or
>the future-proof approach is better, but we might want to consolidate to
>a single function that can be used in both places so that there isn't
>confusion about why there are two ways to do the same thing in different
>parts of the driver.

For today's needs, I think it is probably simpler to just promote
skl_fbc_id_for_pipe() to a function exported by intel_fbc.h.  I'll do
that.

Thanks!

--
Gustavo Sousa

>
>
>Matt
>
>> +
>> +static void __intel_fbc_log_fifo_underrun(struct intel_fbc *fbc, enum pipe pipe)
>> +{
>> +        struct intel_display *display = fbc->display;
>> +        u32 val;
>> +
>> +        val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));
>> +        if (val & FBC_UNDERRUN_DECMPR) {
>> +                intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR);
>> +                drm_err(display->drm, "Pipe %c FIFO underrun info: FBC %c decompressing\n",
>> +                        pipe_name(pipe), fbc_name(fbc->id));
>> +        }
>> +}
>> +
>> +void intel_fbc_log_fifo_underrun(struct intel_display *display, enum pipe pipe)
>> +{
>> +        struct intel_fbc *fbc;
>> +        enum intel_fbc_id fbc_id;
>> +        unsigned int fbc_mask;
>> +
>> +        fbc_mask = pipe_to_fbc_mask(display, pipe);
>> +
>> +        for_each_intel_fbc(display, fbc, fbc_id)
>> +                if (fbc_mask & BIT(fbc_id))
>> +                        __intel_fbc_log_fifo_underrun(fbc, pipe);
>> +}
>> +
>>  /*
>>   * The DDX driver changes its behavior depending on the value it reads from
>>   * i915.enable_fbc, so sanitize it by translating the default value into either
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
>> index 91424563206a..d34282cbe971 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
>> @@ -9,6 +9,7 @@
>>  #include <linux/types.h>
>>  
>>  enum fb_op_origin;
>> +enum pipe;
>>  struct intel_atomic_state;
>>  struct intel_crtc;
>>  struct intel_crtc_state;
>> @@ -46,6 +47,7 @@ void intel_fbc_flush(struct intel_display *display,
>>                       unsigned int frontbuffer_bits, enum fb_op_origin origin);
>>  void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
>>  void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
>> +void intel_fbc_log_fifo_underrun(struct intel_display *display, enum pipe pipe);
>>  void intel_fbc_reset_underrun(struct intel_display *display);
>>  void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
>>  void intel_fbc_debugfs_register(struct intel_display *display);
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> index b1d0161a3196..77d8321c4fb3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> @@ -88,6 +88,8 @@
>>  #define DPFC_FENCE_YOFF                        _MMIO(0x3218)
>>  #define ILK_DPFC_FENCE_YOFF(fbc_id)        _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
>>  #define DPFC_CHICKEN                        _MMIO(0x3224)
>> +#define FBC_DEBUG_STATUS(fbc_id)        _MMIO_PIPE((fbc_id), 0x43220, 0x43260)
>> +#define   FBC_UNDERRUN_DECMPR                        REG_BIT(27)
>>  #define ILK_DPFC_CHICKEN(fbc_id)        _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
>>  #define   DPFC_HT_MODIFY                        REG_BIT(31) /* pre-ivb */
>>  #define   DPFC_NUKE_ON_ANY_MODIFICATION                REG_BIT(23) /* bdw+ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
>> index 1da90c99f93f..d0dbc4faa3f4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
>> @@ -403,6 +403,7 @@ static void xe3p_lpd_log_underrun(struct intel_display *display,
>>          u32 val;
>>  
>>          process_underrun_dbg1(display, pipe);
>> +        intel_fbc_log_fifo_underrun(display, pipe);
>>  
>>          val = intel_de_read(display, UNDERRUN_DBG2(pipe));
>>          if (val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN) {
>> 
>> -- 
>> 2.51.0
>> 
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

[PATCH v3 18/29] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers

[Gustavo Sousa]

From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>

Xe3p_LPD updated fields of registers MBUS_CTL and DBUF_CTL to
accommodate for higher MDCLK:CDCLK ratios.  Update the code to use the
new fields.

The field MBUS_TRANSLATION_THROTTLE_MIN_MASK was changed from range
[15:13] to [16:13].  Since bit 16 is not reserved in previous display
IPs and already used for something else, we can't simply extend the mask
definition to include it, but rather define an Xe3p-specific mask and
select the correct one to use based on the IP version.

Similarly, DBUF_MIN_TRACKER_STATE_SERVICE_MASK was changed from range
[18:16] to [20:16]. For the same reasons stated above, it needs a
Xe3p-specific mask definition.

v2:
  - Keep definitions in the same line (i.e. without line continuation
    breaks) for better readability. (Jani)
v3:
  - Keep mask fields sorted by the upper limit. (Matt)
  - Extend commit message to indicate why we need Xe3p-specific
    definitions of the masks instead of just extending the existing
    ones. (Matt)

Bspec: 68868, 68872
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c      | 16 +++++--
 drivers/gpu/drm/i915/display/skl_watermark_regs.h | 52 ++++++++++++-----------
 2 files changed, 40 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index c888b0896d89..d20c88ebe919 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3479,7 +3479,10 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
 	if (!HAS_MBUS_JOINING(display))
 		return;
 
-	if (DISPLAY_VER(display) >= 20)
+	if (DISPLAY_VER(display) >= 35)
+		intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK,
+			     XE3P_MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
+	else if (DISPLAY_VER(display) >= 20)
 		intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,
 			     MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
 
@@ -3490,9 +3493,14 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
 		    ratio, str_yes_no(joined_mbus));
 
 	for_each_dbuf_slice(display, slice)
-		intel_de_rmw(display, DBUF_CTL_S(slice),
-			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
-			     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
+		if (DISPLAY_VER(display) >= 35)
+			intel_de_rmw(display, DBUF_CTL_S(slice),
+				     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+				     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
+		else
+			intel_de_rmw(display, DBUF_CTL_S(slice),
+				     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+				     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
 }
 
 static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
index c5572fc0e847..abf56ac31105 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
@@ -32,16 +32,18 @@
 #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
 
-#define MBUS_CTL				_MMIO(0x4438C)
-#define   MBUS_JOIN				REG_BIT(31)
-#define   MBUS_HASHING_MODE_MASK		REG_BIT(30)
-#define   MBUS_HASHING_MODE_2x2			REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
-#define   MBUS_HASHING_MODE_1x4			REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
-#define   MBUS_JOIN_PIPE_SELECT_MASK		REG_GENMASK(28, 26)
-#define   MBUS_JOIN_PIPE_SELECT(pipe)		REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
-#define   MBUS_JOIN_PIPE_SELECT_NONE		MBUS_JOIN_PIPE_SELECT(7)
-#define   MBUS_TRANSLATION_THROTTLE_MIN_MASK	REG_GENMASK(15, 13)
-#define   MBUS_TRANSLATION_THROTTLE_MIN(val)	REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
+#define MBUS_CTL					_MMIO(0x4438C)
+#define   MBUS_JOIN					REG_BIT(31)
+#define   MBUS_HASHING_MODE_MASK			REG_BIT(30)
+#define   MBUS_HASHING_MODE_2x2				REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
+#define   MBUS_HASHING_MODE_1x4				REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
+#define   MBUS_JOIN_PIPE_SELECT_MASK			REG_GENMASK(28, 26)
+#define   MBUS_JOIN_PIPE_SELECT(pipe)			REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
+#define   MBUS_JOIN_PIPE_SELECT_NONE			MBUS_JOIN_PIPE_SELECT(7)
+#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK	REG_GENMASK(16, 13)
+#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val)	REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
+#define   MBUS_TRANSLATION_THROTTLE_MIN_MASK		REG_GENMASK(15, 13)
+#define   MBUS_TRANSLATION_THROTTLE_MIN(val)		REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
 
 /*
  * The below are numbered starting from "S1" on gen11/gen12, but starting
@@ -51,20 +53,22 @@
  * way things will be named by the hardware team going forward, plus it's more
  * consistent with how most of the rest of our registers are named.
  */
-#define _DBUF_CTL_S0				0x45008
-#define _DBUF_CTL_S1				0x44FE8
-#define _DBUF_CTL_S2				0x44300
-#define _DBUF_CTL_S3				0x44304
-#define DBUF_CTL_S(slice)			_MMIO(_PICK(slice, \
-							    _DBUF_CTL_S0, \
-							    _DBUF_CTL_S1, \
-							    _DBUF_CTL_S2, \
-							    _DBUF_CTL_S3))
-#define  DBUF_POWER_REQUEST			REG_BIT(31)
-#define  DBUF_POWER_STATE			REG_BIT(30)
-#define  DBUF_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(23, 19)
-#define  DBUF_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
-#define  DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(18, 16) /* ADL-P+ */
+#define _DBUF_CTL_S0					0x45008
+#define _DBUF_CTL_S1					0x44FE8
+#define _DBUF_CTL_S2					0x44300
+#define _DBUF_CTL_S3					0x44304
+#define DBUF_CTL_S(slice)				_MMIO(_PICK(slice, \
+								    _DBUF_CTL_S0, \
+								    _DBUF_CTL_S1, \
+								    _DBUF_CTL_S2, \
+								    _DBUF_CTL_S3))
+#define  DBUF_POWER_REQUEST				REG_BIT(31)
+#define  DBUF_POWER_STATE				REG_BIT(30)
+#define  DBUF_TRACKER_STATE_SERVICE_MASK		REG_GENMASK(23, 19)
+#define  DBUF_TRACKER_STATE_SERVICE(x)			REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
+#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(20, 16)
+#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x)
+#define  DBUF_MIN_TRACKER_STATE_SERVICE_MASK		REG_GENMASK(18, 16) /* ADL-P+ */
 #define  DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
 
 #define MTL_LATENCY_LP0_LP1		_MMIO(0x45780)

-- 
2.51.0

Re: [PATCH v3 18/29] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers

[Matt Roper]

On Mon, Nov 03, 2025 at 02:18:09PM -0300, Gustavo Sousa wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> 
> Xe3p_LPD updated fields of registers MBUS_CTL and DBUF_CTL to
> accommodate for higher MDCLK:CDCLK ratios.  Update the code to use the
> new fields.
> 
> The field MBUS_TRANSLATION_THROTTLE_MIN_MASK was changed from range
> [15:13] to [16:13].  Since bit 16 is not reserved in previous display
> IPs and already used for something else, we can't simply extend the mask
> definition to include it, but rather define an Xe3p-specific mask and
> select the correct one to use based on the IP version.
> 
> Similarly, DBUF_MIN_TRACKER_STATE_SERVICE_MASK was changed from range
> [18:16] to [20:16]. For the same reasons stated above, it needs a
> Xe3p-specific mask definition.
> 
> v2:
>   - Keep definitions in the same line (i.e. without line continuation
>     breaks) for better readability. (Jani)
> v3:
>   - Keep mask fields sorted by the upper limit. (Matt)
>   - Extend commit message to indicate why we need Xe3p-specific
>     definitions of the masks instead of just extending the existing
>     ones. (Matt)
> 
> Bspec: 68868, 68872
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c      | 16 +++++--
>  drivers/gpu/drm/i915/display/skl_watermark_regs.h | 52 ++++++++++++-----------
>  2 files changed, 40 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index c888b0896d89..d20c88ebe919 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3479,7 +3479,10 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
>  	if (!HAS_MBUS_JOINING(display))
>  		return;
>  
> -	if (DISPLAY_VER(display) >= 20)
> +	if (DISPLAY_VER(display) >= 35)
> +		intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK,
> +			     XE3P_MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
> +	else if (DISPLAY_VER(display) >= 20)
>  		intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,
>  			     MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
>  
> @@ -3490,9 +3493,14 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
>  		    ratio, str_yes_no(joined_mbus));
>  
>  	for_each_dbuf_slice(display, slice)
> -		intel_de_rmw(display, DBUF_CTL_S(slice),
> -			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> -			     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> +		if (DISPLAY_VER(display) >= 35)
> +			intel_de_rmw(display, DBUF_CTL_S(slice),
> +				     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> +				     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> +		else
> +			intel_de_rmw(display, DBUF_CTL_S(slice),
> +				     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> +				     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
>  }
>  
>  static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> index c5572fc0e847..abf56ac31105 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> @@ -32,16 +32,18 @@
>  #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
>  #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
>  
> -#define MBUS_CTL				_MMIO(0x4438C)
> -#define   MBUS_JOIN				REG_BIT(31)
> -#define   MBUS_HASHING_MODE_MASK		REG_BIT(30)
> -#define   MBUS_HASHING_MODE_2x2			REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
> -#define   MBUS_HASHING_MODE_1x4			REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
> -#define   MBUS_JOIN_PIPE_SELECT_MASK		REG_GENMASK(28, 26)
> -#define   MBUS_JOIN_PIPE_SELECT(pipe)		REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
> -#define   MBUS_JOIN_PIPE_SELECT_NONE		MBUS_JOIN_PIPE_SELECT(7)
> -#define   MBUS_TRANSLATION_THROTTLE_MIN_MASK	REG_GENMASK(15, 13)
> -#define   MBUS_TRANSLATION_THROTTLE_MIN(val)	REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
> +#define MBUS_CTL					_MMIO(0x4438C)
> +#define   MBUS_JOIN					REG_BIT(31)
> +#define   MBUS_HASHING_MODE_MASK			REG_BIT(30)
> +#define   MBUS_HASHING_MODE_2x2				REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
> +#define   MBUS_HASHING_MODE_1x4				REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
> +#define   MBUS_JOIN_PIPE_SELECT_MASK			REG_GENMASK(28, 26)
> +#define   MBUS_JOIN_PIPE_SELECT(pipe)			REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
> +#define   MBUS_JOIN_PIPE_SELECT_NONE			MBUS_JOIN_PIPE_SELECT(7)
> +#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK	REG_GENMASK(16, 13)
> +#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val)	REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
> +#define   MBUS_TRANSLATION_THROTTLE_MIN_MASK		REG_GENMASK(15, 13)
> +#define   MBUS_TRANSLATION_THROTTLE_MIN(val)		REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
>  
>  /*
>   * The below are numbered starting from "S1" on gen11/gen12, but starting
> @@ -51,20 +53,22 @@
>   * way things will be named by the hardware team going forward, plus it's more
>   * consistent with how most of the rest of our registers are named.
>   */
> -#define _DBUF_CTL_S0				0x45008
> -#define _DBUF_CTL_S1				0x44FE8
> -#define _DBUF_CTL_S2				0x44300
> -#define _DBUF_CTL_S3				0x44304
> -#define DBUF_CTL_S(slice)			_MMIO(_PICK(slice, \
> -							    _DBUF_CTL_S0, \
> -							    _DBUF_CTL_S1, \
> -							    _DBUF_CTL_S2, \
> -							    _DBUF_CTL_S3))
> -#define  DBUF_POWER_REQUEST			REG_BIT(31)
> -#define  DBUF_POWER_STATE			REG_BIT(30)
> -#define  DBUF_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(23, 19)
> -#define  DBUF_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
> -#define  DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(18, 16) /* ADL-P+ */
> +#define _DBUF_CTL_S0					0x45008
> +#define _DBUF_CTL_S1					0x44FE8
> +#define _DBUF_CTL_S2					0x44300
> +#define _DBUF_CTL_S3					0x44304
> +#define DBUF_CTL_S(slice)				_MMIO(_PICK(slice, \
> +								    _DBUF_CTL_S0, \
> +								    _DBUF_CTL_S1, \
> +								    _DBUF_CTL_S2, \
> +								    _DBUF_CTL_S3))
> +#define  DBUF_POWER_REQUEST				REG_BIT(31)
> +#define  DBUF_POWER_STATE				REG_BIT(30)
> +#define  DBUF_TRACKER_STATE_SERVICE_MASK		REG_GENMASK(23, 19)
> +#define  DBUF_TRACKER_STATE_SERVICE(x)			REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
> +#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(20, 16)
> +#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x)
> +#define  DBUF_MIN_TRACKER_STATE_SERVICE_MASK		REG_GENMASK(18, 16) /* ADL-P+ */
>  #define  DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
>  
>  #define MTL_LATENCY_LP0_LP1		_MMIO(0x45780)
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v3 19/29] drm/i915/wm: Do not make latency values monotonic on Xe3 onward

[Gustavo Sousa]

The Windows driver is rejecting non-monotonic ranges latency values for
Xe3.  Let's make sure that we do not call make_wm_latency_monotonic()
for Xe3 and beyond.

Also, because of that, let's add a check at the end of
adjust_wm_latency() to ensure we raise a warning if the final list of
latency values is not monotonic.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index d20c88ebe919..e13324af7afb 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3211,6 +3211,18 @@ static void make_wm_latency_monotonic(struct intel_display *display)
 	}
 }
 
+static bool is_wm_latency_monotonic(struct intel_display *display)
+{
+	u16 *wm = display->wm.skl_latency;
+	int level, num_levels = display->wm.num_levels;
+
+	for (level = 1; level < num_levels; level++)
+		if (wm[level] < wm[level - 1])
+			return false;
+
+	return true;
+}
+
 static void
 adjust_wm_latency(struct intel_display *display)
 {
@@ -3221,7 +3233,8 @@ adjust_wm_latency(struct intel_display *display)
 
 	sanitize_wm_latency(display);
 
-	make_wm_latency_monotonic(display);
+	if (DISPLAY_VER(display) < 30)
+		make_wm_latency_monotonic(display);
 
 	/*
 	 * WaWmMemoryReadLatency
@@ -3241,6 +3254,8 @@ adjust_wm_latency(struct intel_display *display)
 	 */
 	if (need_16gb_dimm_wa(display))
 		increase_wm_latency(display, 1);
+
+	drm_WARN_ON(display->drm, !is_wm_latency_monotonic(display));
 }
 
 static void mtl_read_wm_latency(struct intel_display *display)

-- 
2.51.0

Re: [PATCH v3 19/29] drm/i915/wm: Do not make latency values monotonic on Xe3 onward

[Matt Roper]

On Mon, Nov 03, 2025 at 02:18:10PM -0300, Gustavo Sousa wrote:
> The Windows driver is rejecting non-monotonic ranges latency values for
> Xe3.  Let's make sure that we do not call make_wm_latency_monotonic()
> for Xe3 and beyond.

So is Windows just refusing to drive the display at all if the latencies
look invalid?  If we're trying to match their behavior and avoid
supporting bogus BIOS values, should we be propagating an error up the
call stack and failing the display initialization?

If that's too drastic and we want to try to forge onward anyway after
raising the error message, then is there a reason to also avoid doing
the value adjustment?  I think the goal was to make sure we weren't
letting bad settings go through silently, but once we've taken care of
that it still seems like doing the adjustment might give us a higher
chance of having a working display output?


Matt

> 
> Also, because of that, let's add a check at the end of
> adjust_wm_latency() to ensure we raise a warning if the final list of
> latency values is not monotonic.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index d20c88ebe919..e13324af7afb 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3211,6 +3211,18 @@ static void make_wm_latency_monotonic(struct intel_display *display)
>  	}
>  }
>  
> +static bool is_wm_latency_monotonic(struct intel_display *display)
> +{
> +	u16 *wm = display->wm.skl_latency;
> +	int level, num_levels = display->wm.num_levels;
> +
> +	for (level = 1; level < num_levels; level++)
> +		if (wm[level] < wm[level - 1])
> +			return false;
> +
> +	return true;
> +}
> +
>  static void
>  adjust_wm_latency(struct intel_display *display)
>  {
> @@ -3221,7 +3233,8 @@ adjust_wm_latency(struct intel_display *display)
>  
>  	sanitize_wm_latency(display);
>  
> -	make_wm_latency_monotonic(display);
> +	if (DISPLAY_VER(display) < 30)
> +		make_wm_latency_monotonic(display);
>  
>  	/*
>  	 * WaWmMemoryReadLatency
> @@ -3241,6 +3254,8 @@ adjust_wm_latency(struct intel_display *display)
>  	 */
>  	if (need_16gb_dimm_wa(display))
>  		increase_wm_latency(display, 1);
> +
> +	drm_WARN_ON(display->drm, !is_wm_latency_monotonic(display));
>  }
>  
>  static void mtl_read_wm_latency(struct intel_display *display)
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v3 19/29] drm/i915/wm: Do not make latency values monotonic on Xe3 onward

[Gustavo Sousa]

Quoting Matt Roper (2025-11-03 19:48:27-03:00)
>On Mon, Nov 03, 2025 at 02:18:10PM -0300, Gustavo Sousa wrote:
>> The Windows driver is rejecting non-monotonic ranges latency values for
>> Xe3.  Let's make sure that we do not call make_wm_latency_monotonic()
>> for Xe3 and beyond.
>
>So is Windows just refusing to drive the display at all if the latencies
>look invalid?  If we're trying to match their behavior and avoid
>supporting bogus BIOS values, should we be propagating an error up the
>call stack and failing the display initialization?
>
>If that's too drastic and we want to try to forge onward anyway after
>raising the error message, then is there a reason to also avoid doing
>the value adjustment?  I think the goal was to make sure we weren't
>letting bad settings go through silently, but once we've taken care of
>that it still seems like doing the adjustment might give us a higher
>chance of having a working display output?

When I read Ville's initial feedback (see the discussion at [1]), I
interpreted "reject" possibly as simply refusing to use them and use
only the ones from the initial valid subsequence.  I think Ville might
clarify this.

That said, I believe Ville had a different view of how we should handle
that.  I might have misunderstood something and this patch might not
fully reflect the feedback, though.

Ville, thoughts?

[1] https://lore.kernel.org/all/aQOGWm9x-ZERKfZA@intel.com/

--
Gustavo Sousa

>
>
>Matt
>
>> 
>> Also, because of that, let's add a check at the end of
>> adjust_wm_latency() to ensure we raise a warning if the final list of
>> latency values is not monotonic.
>> 
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/skl_watermark.c | 17 ++++++++++++++++-
>>  1 file changed, 16 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>> index d20c88ebe919..e13324af7afb 100644
>> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
>> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>> @@ -3211,6 +3211,18 @@ static void make_wm_latency_monotonic(struct intel_display *display)
>>          }
>>  }
>>  
>> +static bool is_wm_latency_monotonic(struct intel_display *display)
>> +{
>> +        u16 *wm = display->wm.skl_latency;
>> +        int level, num_levels = display->wm.num_levels;
>> +
>> +        for (level = 1; level < num_levels; level++)
>> +                if (wm[level] < wm[level - 1])
>> +                        return false;
>> +
>> +        return true;
>> +}
>> +
>>  static void
>>  adjust_wm_latency(struct intel_display *display)
>>  {
>> @@ -3221,7 +3233,8 @@ adjust_wm_latency(struct intel_display *display)
>>  
>>          sanitize_wm_latency(display);
>>  
>> -        make_wm_latency_monotonic(display);
>> +        if (DISPLAY_VER(display) < 30)
>> +                make_wm_latency_monotonic(display);
>>  
>>          /*
>>           * WaWmMemoryReadLatency
>> @@ -3241,6 +3254,8 @@ adjust_wm_latency(struct intel_display *display)
>>           */
>>          if (need_16gb_dimm_wa(display))
>>                  increase_wm_latency(display, 1);
>> +
>> +        drm_WARN_ON(display->drm, !is_wm_latency_monotonic(display));
>>  }
>>  
>>  static void mtl_read_wm_latency(struct intel_display *display)
>> 
>> -- 
>> 2.51.0
>> 
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

[PATCH v3 20/29] drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency

[Gustavo Sousa]

When reading memory latencies for watermark calculations, previous
display releases instructed to apply an adjustment of adding a certain
value (e.g. 6us) to all levels when the level 0's memory latency read
from hardware was zero.

For Xe3p_LPD, the instruction is to always use 6us for level 0 and to
add that value to the other levels.  Add the necessary code in
sanitize_wm_latency() so that WaWmMemoryReadLatency is always applied
for Xe3p_LPD and beyond.

v2:
  - Rebased after addition of prep patch "drm/i915/wm: Reorder
    adjust_wm_latency() for Xe3_LPD" (dropped in v3).
v3:
  - Back to the simpler approach of doing the 'wm[0] = 0' step without
    modifying the rest of the code, and that inside
    sanitize_wm_latency(). (Matt Roper, Ville)

Bspec: 68986, 69126
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index e13324af7afb..ed55fe84e930 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3184,6 +3184,13 @@ static void sanitize_wm_latency(struct intel_display *display)
 	u16 *wm = display->wm.skl_latency;
 	int level, num_levels = display->wm.num_levels;
 
+	/*
+	 * Xe3p and beyond should ignore level 0's reported latency and
+	 * always apply WaWmMemoryReadLatency logic.
+	 */
+	if (DISPLAY_VER(display) >= 35)
+		wm[0] = 0;
+
 	/*
 	 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
 	 * need to be disabled. We make sure to sanitize the values out

-- 
2.51.0

Re: [PATCH v3 20/29] drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency

[Matt Roper]

On Mon, Nov 03, 2025 at 02:18:11PM -0300, Gustavo Sousa wrote:
> When reading memory latencies for watermark calculations, previous
> display releases instructed to apply an adjustment of adding a certain
> value (e.g. 6us) to all levels when the level 0's memory latency read
> from hardware was zero.
> 
> For Xe3p_LPD, the instruction is to always use 6us for level 0 and to
> add that value to the other levels.  Add the necessary code in
> sanitize_wm_latency() so that WaWmMemoryReadLatency is always applied
> for Xe3p_LPD and beyond.
> 
> v2:
>   - Rebased after addition of prep patch "drm/i915/wm: Reorder
>     adjust_wm_latency() for Xe3_LPD" (dropped in v3).
> v3:
>   - Back to the simpler approach of doing the 'wm[0] = 0' step without
>     modifying the rest of the code, and that inside
>     sanitize_wm_latency(). (Matt Roper, Ville)
> 
> Bspec: 68986, 69126
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index e13324af7afb..ed55fe84e930 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3184,6 +3184,13 @@ static void sanitize_wm_latency(struct intel_display *display)
>  	u16 *wm = display->wm.skl_latency;
>  	int level, num_levels = display->wm.num_levels;
>  
> +	/*
> +	 * Xe3p and beyond should ignore level 0's reported latency and
> +	 * always apply WaWmMemoryReadLatency logic.
> +	 */
> +	if (DISPLAY_VER(display) >= 35)
> +		wm[0] = 0;
> +
>  	/*
>  	 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
>  	 * need to be disabled. We make sure to sanitize the values out
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v3 21/29] drm/i915/xe3p_lpd: Enable system caching for FBC

[Gustavo Sousa]

From: Vinod Govindapillai <vinod.govindapillai@intel.com>

Configure one of the FBC instances to use system caching. FBC
read/write requests are tagged as cacheable till a programmed
limit is reached by the hw.

Bspec: 74722
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c      | 47 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_fbc_regs.h |  9 +++++
 2 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 24b72951ea3c..e2e55c58ddbc 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -127,6 +127,9 @@ struct intel_fbc {
 	 */
 	struct intel_fbc_state state;
 	const char *no_fbc_reason;
+
+	/* Only one of FBC instances can use the system cache */
+	bool own_sys_cache;
 };
 
 static char fbc_name(enum intel_fbc_id fbc_id)
@@ -569,12 +572,51 @@ static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
 	return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
 }
 
+static void nvl_fbc_program_system_cache(struct intel_fbc *fbc, bool enable)
+{
+	struct intel_display *display = fbc->display;
+	u32 cfb_offset, usage;
+
+	lockdep_assert_held(&fbc->lock);
+
+	usage = intel_de_read(display, NVL_FBC_SYS_CACHE_USAGE_CFG);
+
+	/* System cache already being used by another pipe */
+	if (enable && (usage & FBC_SYS_CACHE_TAG_USE_RES_SPACE))
+		return;
+
+	/* Only the fbc instance which owns system cache can disable it */
+	if (!enable && !fbc->own_sys_cache)
+		return;
+
+	/*
+	 * Not programming the cache limit and cache reading enable bits explicitly
+	 * here. The default values should take care of those and that could leave
+	 * adjustments of those bits to the system hw policy
+	 *
+	 * TODO: check if we need to explicitly program these?
+	 */
+	cfb_offset = enable ? i915_gem_stolen_node_offset(fbc->compressed_fb) : 0;
+	usage |= FBC_SYS_CACHE_START_BASE(cfb_offset);
+	usage |= enable ? FBC_SYS_CACHE_TAG_USE_RES_SPACE : FBC_SYS_CACHE_TAG_DONT_CACHE;
+
+	intel_de_write(display, NVL_FBC_SYS_CACHE_USAGE_CFG, usage);
+
+	fbc->own_sys_cache = enable;
+
+	drm_dbg_kms(display->drm, "System caching for FBC[%d] %s\n",
+		    fbc->id, enable ? "configured" : "cleared");
+}
+
 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
 {
 	struct intel_display *display = fbc->display;
 
 	intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
 		       i915_gem_stolen_node_offset(fbc->compressed_fb));
+
+	if (DISPLAY_VER(display) >= 35)
+		nvl_fbc_program_system_cache(fbc, true);
 }
 
 static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -952,6 +994,8 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
 
 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 {
+	struct intel_display *display = fbc->display;
+
 	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
 		return;
 
@@ -959,6 +1003,9 @@ static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 		i915_gem_stolen_remove_node(fbc->compressed_llb);
 	if (i915_gem_stolen_node_allocated(fbc->compressed_fb))
 		i915_gem_stolen_remove_node(fbc->compressed_fb);
+
+	if (DISPLAY_VER(display) >= 35)
+		nvl_fbc_program_system_cache(fbc, false);
 }
 
 void intel_fbc_cleanup(struct intel_display *display)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
index 77d8321c4fb3..592cd2384255 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -128,4 +128,13 @@
 #define   FBC_REND_NUKE			REG_BIT(2)
 #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
 
+#define NVL_FBC_SYS_CACHE_USAGE_CFG             _MMIO(0x1344E0)
+#define   FBC_SYS_CACHE_START_BASE_MASK         REG_GENMASK(31, 16)
+#define   FBC_SYS_CACHE_START_BASE(base)        REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
+#define   FBC_SYS_CACHEABLE_RANGE_MASK          REG_GENMASK(15, 4)
+#define   FBC_SYS_CACHEABLE_RANGE(range)        REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
+#define   FBC_SYS_CACHE_TAG_MASK                REG_GENMASK(3, 2)
+#define   FBC_SYS_CACHE_TAG_DONT_CACHE          REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
+#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE       REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
+
 #endif /* __INTEL_FBC_REGS__ */

-- 
2.51.0

Re: [PATCH v3 21/29] drm/i915/xe3p_lpd: Enable system caching for FBC

[Matt Roper]

On Mon, Nov 03, 2025 at 02:18:12PM -0300, Gustavo Sousa wrote:
> From: Vinod Govindapillai <vinod.govindapillai@intel.com>
> 
> Configure one of the FBC instances to use system caching. FBC
> read/write requests are tagged as cacheable till a programmed
> limit is reached by the hw.

What exactly is "system caching?"  We have lots of different caches in
current platforms, and it's not really obvious to me from the
description here (or the bspec page) exactly which cache(s) are involved
here.

Is turning this on always a win or is it situational?  I.e., is there
any potential for display memory traffic to fill a cache with FBC data
by evicting data that was part of the CPU or GT's working set?  If so,
that seems like it could potentially harm the performance of other
workloads running on the platform.

Or is this whole thing about a completely new cache (unrelated to
and unusable by anything else) which is devoted solely to FBC?

> 
> Bspec: 74722

You might want to add 68881 here since it has a bit more information
about how we're actually supposed to set the fields documented on 74722.

> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c      | 47 +++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_fbc_regs.h |  9 +++++
>  2 files changed, 56 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 24b72951ea3c..e2e55c58ddbc 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -127,6 +127,9 @@ struct intel_fbc {
>  	 */
>  	struct intel_fbc_state state;
>  	const char *no_fbc_reason;
> +
> +	/* Only one of FBC instances can use the system cache */
> +	bool own_sys_cache;
>  };
>  
>  static char fbc_name(enum intel_fbc_id fbc_id)
> @@ -569,12 +572,51 @@ static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
>  	return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
>  }
>  
> +static void nvl_fbc_program_system_cache(struct intel_fbc *fbc, bool enable)
> +{
> +	struct intel_display *display = fbc->display;
> +	u32 cfb_offset, usage;
> +
> +	lockdep_assert_held(&fbc->lock);
> +
> +	usage = intel_de_read(display, NVL_FBC_SYS_CACHE_USAGE_CFG);
> +
> +	/* System cache already being used by another pipe */
> +	if (enable && (usage & FBC_SYS_CACHE_TAG_USE_RES_SPACE))
> +		return;

Rather than relying on the current register contents, should we be
sanitizing this on driver probe (in case the pre-OS firmware already set
this up) and then making our own decisions (as part of an atomic
transaction) about which pipe to prioritize after that?

> +
> +	/* Only the fbc instance which owns system cache can disable it */
> +	if (!enable && !fbc->own_sys_cache)
> +		return;
> +
> +	/*
> +	 * Not programming the cache limit and cache reading enable bits explicitly
> +	 * here. The default values should take care of those and that could leave
> +	 * adjustments of those bits to the system hw policy
> +	 *
> +	 * TODO: check if we need to explicitly program these?

There's no hardware default documented for the range field, so unless
the pre-OS firmware sets it up (which we probably shouldn't rely on),
I'd expect this to be 0; I don't think that's what we want.

> +	 */
> +	cfb_offset = enable ? i915_gem_stolen_node_offset(fbc->compressed_fb) : 0;
> +	usage |= FBC_SYS_CACHE_START_BASE(cfb_offset);

And if something *did* set this up already, then OR'ing a new address
over the old one isn't going to work.  We'd need "(old & ~mask) | new"
to ensure we don't have leftover bits still set by accident.  But it
would probably be better to just avoid RMW-style handling in general and
build a complete register value with exactly what we want rather than
trying to modify the pre-existing value.

> +	usage |= enable ? FBC_SYS_CACHE_TAG_USE_RES_SPACE : FBC_SYS_CACHE_TAG_DONT_CACHE;
> +
> +	intel_de_write(display, NVL_FBC_SYS_CACHE_USAGE_CFG, usage);
> +
> +	fbc->own_sys_cache = enable;

It feels like instead of having this as a boolean flag in fbc, this
should be a pointer/ID tracked at the intel_display level.  E.g.,

        display->sys_cache_fbc = fbc;

or possibly converted over to something tracked with atomic state so
that we can make better high-level decisions about which FBC we want to
enable this on as various displays get enabled/disabled.


Matt

> +
> +	drm_dbg_kms(display->drm, "System caching for FBC[%d] %s\n",
> +		    fbc->id, enable ? "configured" : "cleared");
> +}
> +
>  static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
>  {
>  	struct intel_display *display = fbc->display;
>  
>  	intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
>  		       i915_gem_stolen_node_offset(fbc->compressed_fb));
> +
> +	if (DISPLAY_VER(display) >= 35)
> +		nvl_fbc_program_system_cache(fbc, true);
>  }
>  
>  static const struct intel_fbc_funcs ilk_fbc_funcs = {
> @@ -952,6 +994,8 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
>  
>  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>  {
> +	struct intel_display *display = fbc->display;
> +
>  	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
>  		return;
>  
> @@ -959,6 +1003,9 @@ static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>  		i915_gem_stolen_remove_node(fbc->compressed_llb);
>  	if (i915_gem_stolen_node_allocated(fbc->compressed_fb))
>  		i915_gem_stolen_remove_node(fbc->compressed_fb);
> +
> +	if (DISPLAY_VER(display) >= 35)
> +		nvl_fbc_program_system_cache(fbc, false);
>  }
>  
>  void intel_fbc_cleanup(struct intel_display *display)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> index 77d8321c4fb3..592cd2384255 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -128,4 +128,13 @@
>  #define   FBC_REND_NUKE			REG_BIT(2)
>  #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
>  
> +#define NVL_FBC_SYS_CACHE_USAGE_CFG             _MMIO(0x1344E0)
> +#define   FBC_SYS_CACHE_START_BASE_MASK         REG_GENMASK(31, 16)
> +#define   FBC_SYS_CACHE_START_BASE(base)        REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
> +#define   FBC_SYS_CACHEABLE_RANGE_MASK          REG_GENMASK(15, 4)
> +#define   FBC_SYS_CACHEABLE_RANGE(range)        REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
> +#define   FBC_SYS_CACHE_TAG_MASK                REG_GENMASK(3, 2)
> +#define   FBC_SYS_CACHE_TAG_DONT_CACHE          REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
> +#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE       REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
> +
>  #endif /* __INTEL_FBC_REGS__ */
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v3 21/29] drm/i915/xe3p_lpd: Enable system caching for FBC

[Gustavo Sousa]

Quoting Matt Roper (2025-11-03 21:15:37-03:00)
>On Mon, Nov 03, 2025 at 02:18:12PM -0300, Gustavo Sousa wrote:
>> From: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> 
>> Configure one of the FBC instances to use system caching. FBC
>> read/write requests are tagged as cacheable till a programmed
>> limit is reached by the hw.
>
>What exactly is "system caching?"  We have lots of different caches in
>current platforms, and it's not really obvious to me from the
>description here (or the bspec page) exactly which cache(s) are involved
>here.

Perhaps Vinod would provide more assertive answers for this and other
questions, but I'll also try to reply based on my research on this
topic.

Although the Bspec does not make it clear, by digging a bit deeper into
other documentation, "system cache" appears to be the SoC-level cache.

>
>Is turning this on always a win or is it situational?  I.e., is there
>any potential for display memory traffic to fill a cache with FBC data
>by evicting data that was part of the CPU or GT's working set?  If so,
>that seems like it could potentially harm the performance of other
>workloads running on the platform.
>
>Or is this whole thing about a completely new cache (unrelated to
>and unusable by anything else) which is devoted solely to FBC?

From what I understood in the docs, the value
FBC_SYS_CACHE_TAG_USE_RES_SPACE (i.e. 0b11) for field "Cache Tags"
indicates that the caching will happen in a reserved space dedicated to
the display engine.  So I believe we wouldn't be interfering with other
agents.

>
>> 
>> Bspec: 74722
>
>You might want to add 68881 here since it has a bit more information
>about how we're actually supposed to set the fields documented on 74722.

Agreed.

>
>> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_fbc.c      | 47 +++++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/display/intel_fbc_regs.h |  9 +++++
>>  2 files changed, 56 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
>> index 24b72951ea3c..e2e55c58ddbc 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> @@ -127,6 +127,9 @@ struct intel_fbc {
>>           */
>>          struct intel_fbc_state state;
>>          const char *no_fbc_reason;
>> +
>> +        /* Only one of FBC instances can use the system cache */
>> +        bool own_sys_cache;

If we go ahead with using this member, I would prefer that we used
"owns_sys_cache" (just like we use "has_something" instead of
"have_something").

>>  };
>>  
>>  static char fbc_name(enum intel_fbc_id fbc_id)
>> @@ -569,12 +572,51 @@ static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
>>          return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
>>  }
>>  
>> +static void nvl_fbc_program_system_cache(struct intel_fbc *fbc, bool enable)
>> +{
>> +        struct intel_display *display = fbc->display;
>> +        u32 cfb_offset, usage;
>> +
>> +        lockdep_assert_held(&fbc->lock);
>> +
>> +        usage = intel_de_read(display, NVL_FBC_SYS_CACHE_USAGE_CFG);
>> +
>> +        /* System cache already being used by another pipe */
>> +        if (enable && (usage & FBC_SYS_CACHE_TAG_USE_RES_SPACE))
>> +                return;
>
>Rather than relying on the current register contents, should we be
>sanitizing this on driver probe (in case the pre-OS firmware already set
>this up) and then making our own decisions (as part of an atomic
>transaction) about which pipe to prioritize after that?

I agree.

>
>> +
>> +        /* Only the fbc instance which owns system cache can disable it */
>> +        if (!enable && !fbc->own_sys_cache)
>> +                return;
>> +
>> +        /*
>> +         * Not programming the cache limit and cache reading enable bits explicitly
>> +         * here. The default values should take care of those and that could leave
>> +         * adjustments of those bits to the system hw policy
>> +         *
>> +         * TODO: check if we need to explicitly program these?
>
>There's no hardware default documented for the range field, so unless
>the pre-OS firmware sets it up (which we probably shouldn't rely on),
>I'd expect this to be 0; I don't think that's what we want.

Agreed.

The Bspec clearly states that we should set "Cacheable Range" to 32, the
equivalent of 2MB (i.e. 32 chunks of 64KB).  So yes, we shouldn't rely
on any existing value and always use 32.

>
>> +         */
>> +        cfb_offset = enable ? i915_gem_stolen_node_offset(fbc->compressed_fb) : 0;
>> +        usage |= FBC_SYS_CACHE_START_BASE(cfb_offset);
>
>And if something *did* set this up already, then OR'ing a new address
>over the old one isn't going to work.  We'd need "(old & ~mask) | new"
>to ensure we don't have leftover bits still set by accident.  But it

Yeah.  The current code is not accouting for any pre-existing value here
and is subject to corruption by simply OR'ing.  This needs to be fixed.

Another thing to fix here is that the field "Cache Start Base" needs to
be in "4k byte chunks" and we are currently using cfb_offset directly
instead of applying the necessary shift.

>would probably be better to just avoid RMW-style handling in general and
>build a complete register value with exactly what we want rather than
>trying to modify the pre-existing value.

The Bspec says that we should keep other fields with their default
values.  So, I believe we do need to have RMW logic here.

>
>> +        usage |= enable ? FBC_SYS_CACHE_TAG_USE_RES_SPACE : FBC_SYS_CACHE_TAG_DONT_CACHE;
>> +
>> +        intel_de_write(display, NVL_FBC_SYS_CACHE_USAGE_CFG, usage);
>> +
>> +        fbc->own_sys_cache = enable;
>
>It feels like instead of having this as a boolean flag in fbc, this
>should be a pointer/ID tracked at the intel_display level.  E.g.,
>
>        display->sys_cache_fbc = fbc;

Yeah.  A single member instead of one for each FBC seems to be enough.

>
>or possibly converted over to something tracked with atomic state so
>that we can make better high-level decisions about which FBC we want to
>enable this on as various displays get enabled/disabled.

That would be nice.  I see it as something that could be done as a
follow-up.

>
>
>Matt
>
>> +
>> +        drm_dbg_kms(display->drm, "System caching for FBC[%d] %s\n",
>> +                    fbc->id, enable ? "configured" : "cleared");
>> +}
>> +
>>  static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
>>  {
>>          struct intel_display *display = fbc->display;
>>  
>>          intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
>>                         i915_gem_stolen_node_offset(fbc->compressed_fb));
>> +
>> +        if (DISPLAY_VER(display) >= 35)
>> +                nvl_fbc_program_system_cache(fbc, true);

One thing that concerns me here is that we are programming
SYS_CACHE_USAGE multiple times and the Bspec seems to indicate that we
should do it only once:

    "Configure SYS_CACHE_USAGE to setup the caching before enabling
    first FBC and leave it alone after that."

I believe we should get some clarification with the HW team to verify if
what we are doing here is legal.  By doing it multiple times, we could
be interfering with other agents (e.g. PCode) that could be doing some
dynamic adjustments.

--
Gustavo Sousa

>>  }
>>  
>>  static const struct intel_fbc_funcs ilk_fbc_funcs = {
>> @@ -952,6 +994,8 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
>>  
>>  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>>  {
>> +        struct intel_display *display = fbc->display;
>> +
>>          if (WARN_ON(intel_fbc_hw_is_active(fbc)))
>>                  return;
>>  
>> @@ -959,6 +1003,9 @@ static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>>                  i915_gem_stolen_remove_node(fbc->compressed_llb);
>>          if (i915_gem_stolen_node_allocated(fbc->compressed_fb))
>>                  i915_gem_stolen_remove_node(fbc->compressed_fb);
>> +
>> +        if (DISPLAY_VER(display) >= 35)
>> +                nvl_fbc_program_system_cache(fbc, false);
>>  }
>>  
>>  void intel_fbc_cleanup(struct intel_display *display)
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> index 77d8321c4fb3..592cd2384255 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> @@ -128,4 +128,13 @@
>>  #define   FBC_REND_NUKE                        REG_BIT(2)
>>  #define   FBC_REND_CACHE_CLEAN                REG_BIT(1)
>>  
>> +#define NVL_FBC_SYS_CACHE_USAGE_CFG             _MMIO(0x1344E0)
>> +#define   FBC_SYS_CACHE_START_BASE_MASK         REG_GENMASK(31, 16)
>> +#define   FBC_SYS_CACHE_START_BASE(base)        REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
>> +#define   FBC_SYS_CACHEABLE_RANGE_MASK          REG_GENMASK(15, 4)
>> +#define   FBC_SYS_CACHEABLE_RANGE(range)        REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
>> +#define   FBC_SYS_CACHE_TAG_MASK                REG_GENMASK(3, 2)
>> +#define   FBC_SYS_CACHE_TAG_DONT_CACHE          REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
>> +#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE       REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
>> +
>>  #endif /* __INTEL_FBC_REGS__ */
>> 
>> -- 
>> 2.51.0
>> 
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [PATCH v3 21/29] drm/i915/xe3p_lpd: Enable system caching for FBC

[Gustavo Sousa]

Quoting Gustavo Sousa (2025-11-04 13:16:01-03:00)
>Quoting Matt Roper (2025-11-03 21:15:37-03:00)
>>On Mon, Nov 03, 2025 at 02:18:12PM -0300, Gustavo Sousa wrote:
>>> From: Vinod Govindapillai <vinod.govindapillai@intel.com>
>>> 
>>> Configure one of the FBC instances to use system caching. FBC
>>> read/write requests are tagged as cacheable till a programmed
>>> limit is reached by the hw.
>>
>>What exactly is "system caching?"  We have lots of different caches in
>>current platforms, and it's not really obvious to me from the
>>description here (or the bspec page) exactly which cache(s) are involved
>>here.
>
>Perhaps Vinod would provide more assertive answers for this and other
>questions, but I'll also try to reply based on my research on this
>topic.
>
>Although the Bspec does not make it clear, by digging a bit deeper into
>other documentation, "system cache" appears to be the SoC-level cache.
>
>>
>>Is turning this on always a win or is it situational?  I.e., is there
>>any potential for display memory traffic to fill a cache with FBC data
>>by evicting data that was part of the CPU or GT's working set?  If so,
>>that seems like it could potentially harm the performance of other
>>workloads running on the platform.
>>
>>Or is this whole thing about a completely new cache (unrelated to
>>and unusable by anything else) which is devoted solely to FBC?
>
>From what I understood in the docs, the value
>FBC_SYS_CACHE_TAG_USE_RES_SPACE (i.e. 0b11) for field "Cache Tags"
>indicates that the caching will happen in a reserved space dedicated to
>the display engine.  So I believe we wouldn't be interfering with other
>agents.
>
>>
>>> 
>>> Bspec: 74722
>>
>>You might want to add 68881 here since it has a bit more information
>>about how we're actually supposed to set the fields documented on 74722.
>
>Agreed.
>
>>
>>> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/display/intel_fbc.c      | 47 +++++++++++++++++++++++++++
>>>  drivers/gpu/drm/i915/display/intel_fbc_regs.h |  9 +++++
>>>  2 files changed, 56 insertions(+)
>>> 
>>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
>>> index 24b72951ea3c..e2e55c58ddbc 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>>> @@ -127,6 +127,9 @@ struct intel_fbc {
>>>           */
>>>          struct intel_fbc_state state;
>>>          const char *no_fbc_reason;
>>> +
>>> +        /* Only one of FBC instances can use the system cache */
>>> +        bool own_sys_cache;
>
>If we go ahead with using this member, I would prefer that we used
>"owns_sys_cache" (just like we use "has_something" instead of
>"have_something").
>
>>>  };
>>>  
>>>  static char fbc_name(enum intel_fbc_id fbc_id)
>>> @@ -569,12 +572,51 @@ static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
>>>          return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
>>>  }
>>>  
>>> +static void nvl_fbc_program_system_cache(struct intel_fbc *fbc, bool enable)
>>> +{
>>> +        struct intel_display *display = fbc->display;
>>> +        u32 cfb_offset, usage;
>>> +
>>> +        lockdep_assert_held(&fbc->lock);
>>> +
>>> +        usage = intel_de_read(display, NVL_FBC_SYS_CACHE_USAGE_CFG);
>>> +
>>> +        /* System cache already being used by another pipe */
>>> +        if (enable && (usage & FBC_SYS_CACHE_TAG_USE_RES_SPACE))
>>> +                return;
>>
>>Rather than relying on the current register contents, should we be
>>sanitizing this on driver probe (in case the pre-OS firmware already set
>>this up) and then making our own decisions (as part of an atomic
>>transaction) about which pipe to prioritize after that?
>
>I agree.
>
>>
>>> +
>>> +        /* Only the fbc instance which owns system cache can disable it */
>>> +        if (!enable && !fbc->own_sys_cache)
>>> +                return;
>>> +
>>> +        /*
>>> +         * Not programming the cache limit and cache reading enable bits explicitly
>>> +         * here. The default values should take care of those and that could leave
>>> +         * adjustments of those bits to the system hw policy
>>> +         *
>>> +         * TODO: check if we need to explicitly program these?
>>
>>There's no hardware default documented for the range field, so unless
>>the pre-OS firmware sets it up (which we probably shouldn't rely on),
>>I'd expect this to be 0; I don't think that's what we want.
>
>Agreed.
>
>The Bspec clearly states that we should set "Cacheable Range" to 32, the
>equivalent of 2MB (i.e. 32 chunks of 64KB).  So yes, we shouldn't rely
>on any existing value and always use 32.
>
>>
>>> +         */
>>> +        cfb_offset = enable ? i915_gem_stolen_node_offset(fbc->compressed_fb) : 0;
>>> +        usage |= FBC_SYS_CACHE_START_BASE(cfb_offset);
>>
>>And if something *did* set this up already, then OR'ing a new address
>>over the old one isn't going to work.  We'd need "(old & ~mask) | new"
>>to ensure we don't have leftover bits still set by accident.  But it
>
>Yeah.  The current code is not accouting for any pre-existing value here
>and is subject to corruption by simply OR'ing.  This needs to be fixed.
>
>Another thing to fix here is that the field "Cache Start Base" needs to
>be in "4k byte chunks" and we are currently using cfb_offset directly
>instead of applying the necessary shift.
>
>>would probably be better to just avoid RMW-style handling in general and
>>build a complete register value with exactly what we want rather than
>>trying to modify the pre-existing value.
>
>The Bspec says that we should keep other fields with their default
>values.  So, I believe we do need to have RMW logic here.
>
>>
>>> +        usage |= enable ? FBC_SYS_CACHE_TAG_USE_RES_SPACE : FBC_SYS_CACHE_TAG_DONT_CACHE;
>>> +
>>> +        intel_de_write(display, NVL_FBC_SYS_CACHE_USAGE_CFG, usage);
>>> +
>>> +        fbc->own_sys_cache = enable;
>>
>>It feels like instead of having this as a boolean flag in fbc, this
>>should be a pointer/ID tracked at the intel_display level.  E.g.,
>>
>>        display->sys_cache_fbc = fbc;
>
>Yeah.  A single member instead of one for each FBC seems to be enough.
>
>>
>>or possibly converted over to something tracked with atomic state so
>>that we can make better high-level decisions about which FBC we want to
>>enable this on as various displays get enabled/disabled.
>
>That would be nice.  I see it as something that could be done as a
>follow-up.
>
>>
>>
>>Matt
>>
>>> +
>>> +        drm_dbg_kms(display->drm, "System caching for FBC[%d] %s\n",
>>> +                    fbc->id, enable ? "configured" : "cleared");
>>> +}
>>> +
>>>  static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
>>>  {
>>>          struct intel_display *display = fbc->display;
>>>  
>>>          intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
>>>                         i915_gem_stolen_node_offset(fbc->compressed_fb));
>>> +
>>> +        if (DISPLAY_VER(display) >= 35)

I forgot to mention this on my previous email: I think Bspec is missing
this info, but this feature is applicable only to integrated display, so
we probably want to limit the condition above to reflect that.

Perhaps it would be good to have a macro like

  #define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)

--
Gustavo Sousa

>>> +                nvl_fbc_program_system_cache(fbc, true);
>
>One thing that concerns me here is that we are programming
>SYS_CACHE_USAGE multiple times and the Bspec seems to indicate that we
>should do it only once:
>
>    "Configure SYS_CACHE_USAGE to setup the caching before enabling
>    first FBC and leave it alone after that."
>
>I believe we should get some clarification with the HW team to verify if
>what we are doing here is legal.  By doing it multiple times, we could
>be interfering with other agents (e.g. PCode) that could be doing some
>dynamic adjustments.
>
>--
>Gustavo Sousa
>
>>>  }
>>>  
>>>  static const struct intel_fbc_funcs ilk_fbc_funcs = {
>>> @@ -952,6 +994,8 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
>>>  
>>>  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>>>  {
>>> +        struct intel_display *display = fbc->display;
>>> +
>>>          if (WARN_ON(intel_fbc_hw_is_active(fbc)))
>>>                  return;
>>>  
>>> @@ -959,6 +1003,9 @@ static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>>>                  i915_gem_stolen_remove_node(fbc->compressed_llb);
>>>          if (i915_gem_stolen_node_allocated(fbc->compressed_fb))
>>>                  i915_gem_stolen_remove_node(fbc->compressed_fb);
>>> +
>>> +        if (DISPLAY_VER(display) >= 35)
>>> +                nvl_fbc_program_system_cache(fbc, false);
>>>  }
>>>  
>>>  void intel_fbc_cleanup(struct intel_display *display)
>>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>>> index 77d8321c4fb3..592cd2384255 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>>> @@ -128,4 +128,13 @@
>>>  #define   FBC_REND_NUKE                        REG_BIT(2)
>>>  #define   FBC_REND_CACHE_CLEAN                REG_BIT(1)
>>>  
>>> +#define NVL_FBC_SYS_CACHE_USAGE_CFG             _MMIO(0x1344E0)
>>> +#define   FBC_SYS_CACHE_START_BASE_MASK         REG_GENMASK(31, 16)
>>> +#define   FBC_SYS_CACHE_START_BASE(base)        REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
>>> +#define   FBC_SYS_CACHEABLE_RANGE_MASK          REG_GENMASK(15, 4)
>>> +#define   FBC_SYS_CACHEABLE_RANGE(range)        REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
>>> +#define   FBC_SYS_CACHE_TAG_MASK                REG_GENMASK(3, 2)
>>> +#define   FBC_SYS_CACHE_TAG_DONT_CACHE          REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
>>> +#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE       REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
>>> +
>>>  #endif /* __INTEL_FBC_REGS__ */
>>> 
>>> -- 
>>> 2.51.0
>>> 
>>
>>-- 
>>Matt Roper
>>Graphics Software Engineer
>>Linux GPU Platform Enablement
>>Intel Corporation

Re: [PATCH v3 21/29] drm/i915/xe3p_lpd: Enable system caching for FBC

[Govindapillai, Vinod]

On Tue, 2025-11-04 at 13:28 -0300, Gustavo Sousa wrote:
> Quoting Gustavo Sousa (2025-11-04 13:16:01-03:00)
> > Quoting Matt Roper (2025-11-03 21:15:37-03:00)
> > > On Mon, Nov 03, 2025 at 02:18:12PM -0300, Gustavo Sousa wrote:
> > > > From: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > > > 
> > > > Configure one of the FBC instances to use system caching. FBC
> > > > read/write requests are tagged as cacheable till a programmed
> > > > limit is reached by the hw.
> > > 
> > > What exactly is "system caching?"  We have lots of different
> > > caches in
> > > current platforms, and it's not really obvious to me from the
> > > description here (or the bspec page) exactly which cache(s) are
> > > involved
> > > here.
> > 
> > Perhaps Vinod would provide more assertive answers for this and
> > other
> > questions, but I'll also try to reply based on my research on this
> > topic.
> > 
> > Although the Bspec does not make it clear, by digging a bit deeper
> > into
> > other documentation, "system cache" appears to be the SoC-level
> > cache.
> > 
> > > 
> > > Is turning this on always a win or is it situational?  I.e., is
> > > there
> > > any potential for display memory traffic to fill a cache with FBC
> > > data
> > > by evicting data that was part of the CPU or GT's working set? 
> > > If so,
> > > that seems like it could potentially harm the performance of
> > > other
> > > workloads running on the platform.
> > > 
> > > Or is this whole thing about a completely new cache (unrelated to
> > > and unusable by anything else) which is devoted solely to FBC?
> > 
> > From what I understood in the docs, the value
> > FBC_SYS_CACHE_TAG_USE_RES_SPACE (i.e. 0b11) for field "Cache Tags"
> > indicates that the caching will happen in a reserved space
> > dedicated to
> > the display engine.  So I believe we wouldn't be interfering with
> > other
> > agents.
> > 
> > > 
> > > > 
> > > > Bspec: 74722
> > > 
> > > You might want to add 68881 here since it has a bit more
> > > information
> > > about how we're actually supposed to set the fields documented on
> > > 74722.
> > 
> > Agreed.
> > 
> > > 
> > > > Signed-off-by: Vinod Govindapillai
> > > > <vinod.govindapillai@intel.com>
> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_fbc.c      | 47
> > > > +++++++++++++++++++++++++++
> > > >  drivers/gpu/drm/i915/display/intel_fbc_regs.h |  9 +++++
> > > >  2 files changed, 56 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > index 24b72951ea3c..e2e55c58ddbc 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > @@ -127,6 +127,9 @@ struct intel_fbc {
> > > >           */
> > > >          struct intel_fbc_state state;
> > > >          const char *no_fbc_reason;
> > > > +
> > > > +        /* Only one of FBC instances can use the system cache
> > > > */
> > > > +        bool own_sys_cache;
> > 
> > If we go ahead with using this member, I would prefer that we used
> > "owns_sys_cache" (just like we use "has_something" instead of
> > "have_something").
> > 
> > > >  };
> > > >  
> > > >  static char fbc_name(enum intel_fbc_id fbc_id)
> > > > @@ -569,12 +572,51 @@ static bool ilk_fbc_is_compressing(struct
> > > > intel_fbc *fbc)
> > > >          return intel_de_read(fbc->display,
> > > > ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
> > > >  }
> > > >  
> > > > +static void nvl_fbc_program_system_cache(struct intel_fbc
> > > > *fbc, bool enable)
> > > > +{
> > > > +        struct intel_display *display = fbc->display;
> > > > +        u32 cfb_offset, usage;
> > > > +
> > > > +        lockdep_assert_held(&fbc->lock);
> > > > +
> > > > +        usage = intel_de_read(display,
> > > > NVL_FBC_SYS_CACHE_USAGE_CFG);
> > > > +
> > > > +        /* System cache already being used by another pipe */
> > > > +        if (enable && (usage &
> > > > FBC_SYS_CACHE_TAG_USE_RES_SPACE))
> > > > +                return;
> > > 
> > > Rather than relying on the current register contents, should we
> > > be
> > > sanitizing this on driver probe (in case the pre-OS firmware
> > > already set
> > > this up) and then making our own decisions (as part of an atomic
> > > transaction) about which pipe to prioritize after that?
> > 
> > I agree.
> > 
> > > 
> > > > +
> > > > +        /* Only the fbc instance which owns system cache can
> > > > disable it */
> > > > +        if (!enable && !fbc->own_sys_cache)
> > > > +                return;
> > > > +
> > > > +        /*
> > > > +         * Not programming the cache limit and cache reading
> > > > enable bits explicitly
> > > > +         * here. The default values should take care of those
> > > > and that could leave
> > > > +         * adjustments of those bits to the system hw policy
> > > > +         *
> > > > +         * TODO: check if we need to explicitly program these?
> > > 
> > > There's no hardware default documented for the range field, so
> > > unless
> > > the pre-OS firmware sets it up (which we probably shouldn't rely
> > > on),
> > > I'd expect this to be 0; I don't think that's what we want.
> > 
> > Agreed.
> > 
> > The Bspec clearly states that we should set "Cacheable Range" to
> > 32, the
> > equivalent of 2MB (i.e. 32 chunks of 64KB).  So yes, we shouldn't
> > rely
> > on any existing value and always use 32.
> > 
> > > 
> > > > +         */
> > > > +        cfb_offset = enable ? i915_gem_stolen_node_offset(fbc-
> > > > >compressed_fb) : 0;
> > > > +        usage |= FBC_SYS_CACHE_START_BASE(cfb_offset);
> > > 
> > > And if something *did* set this up already, then OR'ing a new
> > > address
> > > over the old one isn't going to work.  We'd need "(old & ~mask) |
> > > new"
> > > to ensure we don't have leftover bits still set by accident.  But
> > > it
> > 
> > Yeah.  The current code is not accouting for any pre-existing value
> > here
> > and is subject to corruption by simply OR'ing.  This needs to be
> > fixed.
> > 
> > Another thing to fix here is that the field "Cache Start Base"
> > needs to
> > be in "4k byte chunks" and we are currently using cfb_offset
> > directly
> > instead of applying the necessary shift.
> > 
> > > would probably be better to just avoid RMW-style handling in
> > > general and
> > > build a complete register value with exactly what we want rather
> > > than
> > > trying to modify the pre-existing value.
> > 
> > The Bspec says that we should keep other fields with their default
> > values.  So, I believe we do need to have RMW logic here.
> > 
> > > 
> > > > +        usage |= enable ? FBC_SYS_CACHE_TAG_USE_RES_SPACE :
> > > > FBC_SYS_CACHE_TAG_DONT_CACHE;
> > > > +
> > > > +        intel_de_write(display, NVL_FBC_SYS_CACHE_USAGE_CFG,
> > > > usage);
> > > > +
> > > > +        fbc->own_sys_cache = enable;
> > > 
> > > It feels like instead of having this as a boolean flag in fbc,
> > > this
> > > should be a pointer/ID tracked at the intel_display level.  E.g.,
> > > 
> > >        display->sys_cache_fbc = fbc;
> > 
> > Yeah.  A single member instead of one for each FBC seems to be
> > enough.
> > 
> > > 
> > > or possibly converted over to something tracked with atomic state
> > > so
> > > that we can make better high-level decisions about which FBC we
> > > want to
> > > enable this on as various displays get enabled/disabled.
> > 
> > That would be nice.  I see it as something that could be done as a
> > follow-up.
> > 
> > > 
> > > 
> > > Matt
> > > 
> > > > +
> > > > +        drm_dbg_kms(display->drm, "System caching for FBC[%d]
> > > > %s\n",
> > > > +                    fbc->id, enable ? "configured" :
> > > > "cleared");
> > > > +}
> > > > +
> > > >  static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
> > > >  {
> > > >          struct intel_display *display = fbc->display;
> > > >  
> > > >          intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
> > > >                         i915_gem_stolen_node_offset(fbc-
> > > > >compressed_fb));
> > > > +
> > > > +        if (DISPLAY_VER(display) >= 35)
> 
> I forgot to mention this on my previous email: I think Bspec is
> missing
> this info, but this feature is applicable only to integrated display,
> so
> we probably want to limit the condition above to reflect that.
> 
> Perhaps it would be good to have a macro like
> 
>   #define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35
> && !(__display)->platform.dgfx)

Ack.

BR
Vinod

> 
> --
> Gustavo Sousa
> 
> > > > +                nvl_fbc_program_system_cache(fbc, true);
> > 
> > One thing that concerns me here is that we are programming
> > SYS_CACHE_USAGE multiple times and the Bspec seems to indicate that
> > we
> > should do it only once:
> > 
> >    "Configure SYS_CACHE_USAGE to setup the caching before enabling
> >    first FBC and leave it alone after that."
> > 
> > I believe we should get some clarification with the HW team to
> > verify if
> > what we are doing here is legal.  By doing it multiple times, we
> > could
> > be interfering with other agents (e.g. PCode) that could be doing
> > some
> > dynamic adjustments.
> > 
> > --
> > Gustavo Sousa
> > 
> > > >  }
> > > >  
> > > >  static const struct intel_fbc_funcs ilk_fbc_funcs = {
> > > > @@ -952,6 +994,8 @@ static void
> > > > intel_fbc_program_workarounds(struct intel_fbc *fbc)
> > > >  
> > > >  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
> > > >  {
> > > > +        struct intel_display *display = fbc->display;
> > > > +
> > > >          if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> > > >                  return;
> > > >  
> > > > @@ -959,6 +1003,9 @@ static void __intel_fbc_cleanup_cfb(struct
> > > > intel_fbc *fbc)
> > > >                  i915_gem_stolen_remove_node(fbc-
> > > > >compressed_llb);
> > > >          if (i915_gem_stolen_node_allocated(fbc-
> > > > >compressed_fb))
> > > >                  i915_gem_stolen_remove_node(fbc-
> > > > >compressed_fb);
> > > > +
> > > > +        if (DISPLAY_VER(display) >= 35)
> > > > +                nvl_fbc_program_system_cache(fbc, false);
> > > >  }
> > > >  
> > > >  void intel_fbc_cleanup(struct intel_display *display)
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > > index 77d8321c4fb3..592cd2384255 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > > @@ -128,4 +128,13 @@
> > > >  #define   FBC_REND_NUKE                        REG_BIT(2)
> > > >  #define   FBC_REND_CACHE_CLEAN                REG_BIT(1)
> > > >  
> > > > +#define NVL_FBC_SYS_CACHE_USAGE_CFG            
> > > > _MMIO(0x1344E0)
> > > > +#define   FBC_SYS_CACHE_START_BASE_MASK        
> > > > REG_GENMASK(31, 16)
> > > > +#define   FBC_SYS_CACHE_START_BASE(base)       
> > > > REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
> > > > +#define   FBC_SYS_CACHEABLE_RANGE_MASK         
> > > > REG_GENMASK(15, 4)
> > > > +#define   FBC_SYS_CACHEABLE_RANGE(range)       
> > > > REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
> > > > +#define   FBC_SYS_CACHE_TAG_MASK                REG_GENMASK(3,
> > > > 2)
> > > > +#define   FBC_SYS_CACHE_TAG_DONT_CACHE         
> > > > REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
> > > > +#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE      
> > > > REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
> > > > +
> > > >  #endif /* __INTEL_FBC_REGS__ */
> > > > 
> > > > -- 
> > > > 2.51.0
> > > > 
> > > 
> > > -- 
> > > Matt Roper
> > > Graphics Software Engineer
> > > Linux GPU Platform Enablement
> > > Intel Corporation

Re: [PATCH v3 21/29] drm/i915/xe3p_lpd: Enable system caching for FBC

[Govindapillai, Vinod]

Hi Matt,


On Mon, 2025-11-03 at 16:15 -0800, Matt Roper wrote:
> On Mon, Nov 03, 2025 at 02:18:12PM -0300, Gustavo Sousa wrote:
> > From: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > 
> > Configure one of the FBC instances to use system caching. FBC
> > read/write requests are tagged as cacheable till a programmed
> > limit is reached by the hw.
> 
> What exactly is "system caching?"  We have lots of different caches
> in
> current platforms, and it's not really obvious to me from the
> description here (or the bspec page) exactly which cache(s) are
> involved
> here.
> 
> Is turning this on always a win or is it situational?  I.e., is there
> any potential for display memory traffic to fill a cache with FBC
> data
> by evicting data that was part of the CPU or GT's working set?  If
> so,
> that seems like it could potentially harm the performance of other
> workloads running on the platform.
> 
> Or is this whole thing about a completely new cache (unrelated to
> and unusable by anything else) which is devoted solely to FBC?
> 
> > 
> > Bspec: 74722
> 
> You might want to add 68881 here since it has a bit more information
> about how we're actually supposed to set the fields documented on
> 74722.

Okay I will include that. I guess, the HAS also talks about "system
cache" - no further explanation. But only a fixed portion is allocated
specifically for the display use and is "configurable". Motivation is
to reduce to memory subsystem power especially in idle scenarios.

> 
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c      | 47
> > +++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_fbc_regs.h |  9 +++++
> >  2 files changed, 56 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 24b72951ea3c..e2e55c58ddbc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -127,6 +127,9 @@ struct intel_fbc {
> >  	 */
> >  	struct intel_fbc_state state;
> >  	const char *no_fbc_reason;
> > +
> > +	/* Only one of FBC instances can use the system cache */
> > +	bool own_sys_cache;
> >  };
> >  
> >  static char fbc_name(enum intel_fbc_id fbc_id)
> > @@ -569,12 +572,51 @@ static bool ilk_fbc_is_compressing(struct
> > intel_fbc *fbc)
> >  	return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc-
> > >id)) & DPFC_COMP_SEG_MASK;
> >  }
> >  
> > +static void nvl_fbc_program_system_cache(struct intel_fbc *fbc,
> > bool enable)
> > +{
> > +	struct intel_display *display = fbc->display;
> > +	u32 cfb_offset, usage;
> > +
> > +	lockdep_assert_held(&fbc->lock);
> > +
> > +	usage = intel_de_read(display,
> > NVL_FBC_SYS_CACHE_USAGE_CFG);
> > +
> > +	/* System cache already being used by another pipe */
> > +	if (enable && (usage & FBC_SYS_CACHE_TAG_USE_RES_SPACE))
> > +		return;
> 
> Rather than relying on the current register contents, should we be
> sanitizing this on driver probe (in case the pre-OS firmware already
> set
> this up) and then making our own decisions (as part of an atomic
> transaction) about which pipe to prioritize after that?


> 
> > +
> > +	/* Only the fbc instance which owns system cache can
> > disable it */
> > +	if (!enable && !fbc->own_sys_cache)
> > +		return;
> > +
> > +	/*
> > +	 * Not programming the cache limit and cache reading
> > enable bits explicitly
> > +	 * here. The default values should take care of those and
> > that could leave
> > +	 * adjustments of those bits to the system hw policy
> > +	 *
> > +	 * TODO: check if we need to explicitly program these?
> 
> There's no hardware default documented for the range field, so unless
> the pre-OS firmware sets it up (which we probably shouldn't rely on),
> I'd expect this to be 0; I don't think that's what we want.

The Bspec says it is 2MB. But according to the HAS it is "configurable"
and I clarified that this is at the moment 2MB but can change. So I
read it as something already configured and set as the default value to
the register and it could be changed by the soc policy. Thats the
reason I thought it be kept untouched. Will forward on email
conversation I had.


> 
> > +	 */
> > +	cfb_offset = enable ? i915_gem_stolen_node_offset(fbc-
> > >compressed_fb) : 0;
> > +	usage |= FBC_SYS_CACHE_START_BASE(cfb_offset);
> 
> And if something *did* set this up already, then OR'ing a new address
> over the old one isn't going to work.  We'd need "(old & ~mask) |
> new"
> to ensure we don't have leftover bits still set by accident.  But it
> would probably be better to just avoid RMW-style handling in general
> and
> build a complete register value with exactly what we want rather than
> trying to modify the pre-existing value.
> 
> > +	usage |= enable ? FBC_SYS_CACHE_TAG_USE_RES_SPACE :
> > FBC_SYS_CACHE_TAG_DONT_CACHE;
> > +
> > +	intel_de_write(display, NVL_FBC_SYS_CACHE_USAGE_CFG,
> > usage);
> > +
> > +	fbc->own_sys_cache = enable;

Okay. Thanks. Will fix that!

> 
> It feels like instead of having this as a boolean flag in fbc, this
> should be a pointer/ID tracked at the intel_display level.  E.g.,
> 
>         display->sys_cache_fbc = fbc;
> 
> or possibly converted over to something tracked with atomic state so
> that we can make better high-level decisions about which FBC we want
> to
> enable this on as various displays get enabled/disabled.

Okay. Will check this and get rid of the bool from the intel_fbc
structure! At the moment we can allocate only based on the firt pipe
enabling the fbc. But may be in future we could have some logic for
this I guess.

> Matt
> 
> > +
> > +	drm_dbg_kms(display->drm, "System caching for FBC[%d]
> > %s\n",
> > +		    fbc->id, enable ? "configured" : "cleared");
> > +}
> > +
> >  static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
> >  {
> >  	struct intel_display *display = fbc->display;
> >  
> >  	intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
> >  		       i915_gem_stolen_node_offset(fbc-
> > >compressed_fb));
> > +
> > +	if (DISPLAY_VER(display) >= 35)
> > +		nvl_fbc_program_system_cache(fbc, true);
> >  }
> >  
> >  static const struct intel_fbc_funcs ilk_fbc_funcs = {
> > @@ -952,6 +994,8 @@ static void
> > intel_fbc_program_workarounds(struct intel_fbc *fbc)
> >  
> >  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
> >  {
> > +	struct intel_display *display = fbc->display;
> > +
> >  	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> >  		return;
> >  
> > @@ -959,6 +1003,9 @@ static void __intel_fbc_cleanup_cfb(struct
> > intel_fbc *fbc)
> >  		i915_gem_stolen_remove_node(fbc->compressed_llb);
> >  	if (i915_gem_stolen_node_allocated(fbc->compressed_fb))
> >  		i915_gem_stolen_remove_node(fbc->compressed_fb);
> > +
> > +	if (DISPLAY_VER(display) >= 35)
> > +		nvl_fbc_program_system_cache(fbc, false);
> >  }
> >  
> >  void intel_fbc_cleanup(struct intel_display *display)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > index 77d8321c4fb3..592cd2384255 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > @@ -128,4 +128,13 @@
> >  #define   FBC_REND_NUKE			REG_BIT(2)
> >  #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
> >  
> > +#define NVL_FBC_SYS_CACHE_USAGE_CFG             _MMIO(0x1344E0)
> > +#define   FBC_SYS_CACHE_START_BASE_MASK         REG_GENMASK(31,
> > 16)
> > +#define   FBC_SYS_CACHE_START_BASE(base)       
> > REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
> > +#define   FBC_SYS_CACHEABLE_RANGE_MASK          REG_GENMASK(15, 4)
> > +#define   FBC_SYS_CACHEABLE_RANGE(range)       
> > REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
> > +#define   FBC_SYS_CACHE_TAG_MASK                REG_GENMASK(3, 2)
> > +#define   FBC_SYS_CACHE_TAG_DONT_CACHE         
> > REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
> > +#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE      
> > REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
> > +
> >  #endif /* __INTEL_FBC_REGS__ */
> > 
> > -- 
> > 2.51.0
> > 
> 

Re: [PATCH v3 21/29] drm/i915/xe3p_lpd: Enable system caching for FBC

[Gustavo Sousa]

Quoting Govindapillai, Vinod (2025-11-04 13:35:43-03:00)
>Hi Matt,
>
>
>On Mon, 2025-11-03 at 16:15 -0800, Matt Roper wrote:
>> On Mon, Nov 03, 2025 at 02:18:12PM -0300, Gustavo Sousa wrote:
>> > From: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> > 
>> > Configure one of the FBC instances to use system caching. FBC
>> > read/write requests are tagged as cacheable till a programmed
>> > limit is reached by the hw.
>> 
>> What exactly is "system caching?"  We have lots of different caches
>> in
>> current platforms, and it's not really obvious to me from the
>> description here (or the bspec page) exactly which cache(s) are
>> involved
>> here.
>> 
>> Is turning this on always a win or is it situational?  I.e., is there
>> any potential for display memory traffic to fill a cache with FBC
>> data
>> by evicting data that was part of the CPU or GT's working set?  If
>> so,
>> that seems like it could potentially harm the performance of other
>> workloads running on the platform.
>> 
>> Or is this whole thing about a completely new cache (unrelated to
>> and unusable by anything else) which is devoted solely to FBC?
>> 
>> > 
>> > Bspec: 74722
>> 
>> You might want to add 68881 here since it has a bit more information
>> about how we're actually supposed to set the fields documented on
>> 74722.
>
>Okay I will include that. I guess, the HAS also talks about "system
>cache" - no further explanation. But only a fixed portion is allocated
>specifically for the display use and is "configurable". Motivation is
>to reduce to memory subsystem power especially in idle scenarios.
>
>> 
>> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_fbc.c      | 47
>> > +++++++++++++++++++++++++++
>> >  drivers/gpu/drm/i915/display/intel_fbc_regs.h |  9 +++++
>> >  2 files changed, 56 insertions(+)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > index 24b72951ea3c..e2e55c58ddbc 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > @@ -127,6 +127,9 @@ struct intel_fbc {
>> >           */
>> >          struct intel_fbc_state state;
>> >          const char *no_fbc_reason;
>> > +
>> > +        /* Only one of FBC instances can use the system cache */
>> > +        bool own_sys_cache;
>> >  };
>> >  
>> >  static char fbc_name(enum intel_fbc_id fbc_id)
>> > @@ -569,12 +572,51 @@ static bool ilk_fbc_is_compressing(struct
>> > intel_fbc *fbc)
>> >          return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc-
>> > >id)) & DPFC_COMP_SEG_MASK;
>> >  }
>> >  
>> > +static void nvl_fbc_program_system_cache(struct intel_fbc *fbc,
>> > bool enable)
>> > +{
>> > +        struct intel_display *display = fbc->display;
>> > +        u32 cfb_offset, usage;
>> > +
>> > +        lockdep_assert_held(&fbc->lock);
>> > +
>> > +        usage = intel_de_read(display,
>> > NVL_FBC_SYS_CACHE_USAGE_CFG);
>> > +
>> > +        /* System cache already being used by another pipe */
>> > +        if (enable && (usage & FBC_SYS_CACHE_TAG_USE_RES_SPACE))
>> > +                return;
>> 
>> Rather than relying on the current register contents, should we be
>> sanitizing this on driver probe (in case the pre-OS firmware already
>> set
>> this up) and then making our own decisions (as part of an atomic
>> transaction) about which pipe to prioritize after that?
>
>
>> 
>> > +
>> > +        /* Only the fbc instance which owns system cache can
>> > disable it */
>> > +        if (!enable && !fbc->own_sys_cache)
>> > +                return;
>> > +
>> > +        /*
>> > +         * Not programming the cache limit and cache reading
>> > enable bits explicitly
>> > +         * here. The default values should take care of those and
>> > that could leave
>> > +         * adjustments of those bits to the system hw policy
>> > +         *
>> > +         * TODO: check if we need to explicitly program these?
>> 
>> There's no hardware default documented for the range field, so unless
>> the pre-OS firmware sets it up (which we probably shouldn't rely on),
>> I'd expect this to be 0; I don't think that's what we want.
>
>The Bspec says it is 2MB. But according to the HAS it is "configurable"
>and I clarified that this is at the moment 2MB but can change. So I
>read it as something already configured and set as the default value to
>the register and it could be changed by the soc policy. Thats the
>reason I thought it be kept untouched. Will forward on email
>conversation I had.

FWIW, I checked it on a NVL system and it was zero prior to loading the
driver.

--
Gustavo Sousa

>
>
>> 
>> > +         */
>> > +        cfb_offset = enable ? i915_gem_stolen_node_offset(fbc-
>> > >compressed_fb) : 0;
>> > +        usage |= FBC_SYS_CACHE_START_BASE(cfb_offset);
>> 
>> And if something *did* set this up already, then OR'ing a new address
>> over the old one isn't going to work.  We'd need "(old & ~mask) |
>> new"
>> to ensure we don't have leftover bits still set by accident.  But it
>> would probably be better to just avoid RMW-style handling in general
>> and
>> build a complete register value with exactly what we want rather than
>> trying to modify the pre-existing value.
>> 
>> > +        usage |= enable ? FBC_SYS_CACHE_TAG_USE_RES_SPACE :
>> > FBC_SYS_CACHE_TAG_DONT_CACHE;
>> > +
>> > +        intel_de_write(display, NVL_FBC_SYS_CACHE_USAGE_CFG,
>> > usage);
>> > +
>> > +        fbc->own_sys_cache = enable;
>
>Okay. Thanks. Will fix that!
>
>> 
>> It feels like instead of having this as a boolean flag in fbc, this
>> should be a pointer/ID tracked at the intel_display level.  E.g.,
>> 
>>         display->sys_cache_fbc = fbc;
>> 
>> or possibly converted over to something tracked with atomic state so
>> that we can make better high-level decisions about which FBC we want
>> to
>> enable this on as various displays get enabled/disabled.
>
>Okay. Will check this and get rid of the bool from the intel_fbc
>structure! At the moment we can allocate only based on the firt pipe
>enabling the fbc. But may be in future we could have some logic for
>this I guess.
>
>> Matt
>> 
>> > +
>> > +        drm_dbg_kms(display->drm, "System caching for FBC[%d]
>> > %s\n",
>> > +                    fbc->id, enable ? "configured" : "cleared");
>> > +}
>> > +
>> >  static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
>> >  {
>> >          struct intel_display *display = fbc->display;
>> >  
>> >          intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
>> >                         i915_gem_stolen_node_offset(fbc-
>> > >compressed_fb));
>> > +
>> > +        if (DISPLAY_VER(display) >= 35)
>> > +                nvl_fbc_program_system_cache(fbc, true);
>> >  }
>> >  
>> >  static const struct intel_fbc_funcs ilk_fbc_funcs = {
>> > @@ -952,6 +994,8 @@ static void
>> > intel_fbc_program_workarounds(struct intel_fbc *fbc)
>> >  
>> >  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>> >  {
>> > +        struct intel_display *display = fbc->display;
>> > +
>> >          if (WARN_ON(intel_fbc_hw_is_active(fbc)))
>> >                  return;
>> >  
>> > @@ -959,6 +1003,9 @@ static void __intel_fbc_cleanup_cfb(struct
>> > intel_fbc *fbc)
>> >                  i915_gem_stolen_remove_node(fbc->compressed_llb);
>> >          if (i915_gem_stolen_node_allocated(fbc->compressed_fb))
>> >                  i915_gem_stolen_remove_node(fbc->compressed_fb);
>> > +
>> > +        if (DISPLAY_VER(display) >= 35)
>> > +                nvl_fbc_program_system_cache(fbc, false);
>> >  }
>> >  
>> >  void intel_fbc_cleanup(struct intel_display *display)
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > index 77d8321c4fb3..592cd2384255 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > @@ -128,4 +128,13 @@
>> >  #define   FBC_REND_NUKE                        REG_BIT(2)
>> >  #define   FBC_REND_CACHE_CLEAN                REG_BIT(1)
>> >  
>> > +#define NVL_FBC_SYS_CACHE_USAGE_CFG             _MMIO(0x1344E0)
>> > +#define   FBC_SYS_CACHE_START_BASE_MASK         REG_GENMASK(31,
>> > 16)
>> > +#define   FBC_SYS_CACHE_START_BASE(base)       
>> > REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
>> > +#define   FBC_SYS_CACHEABLE_RANGE_MASK          REG_GENMASK(15, 4)
>> > +#define   FBC_SYS_CACHEABLE_RANGE(range)       
>> > REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
>> > +#define   FBC_SYS_CACHE_TAG_MASK                REG_GENMASK(3, 2)
>> > +#define   FBC_SYS_CACHE_TAG_DONT_CACHE         
>> > REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
>> > +#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE      
>> > REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
>> > +
>> >  #endif /* __INTEL_FBC_REGS__ */
>> > 
>> > -- 
>> > 2.51.0
>> > 
>> 
>

Re: [PATCH v3 21/29] drm/i915/xe3p_lpd: Enable system caching for FBC

[Gustavo Sousa]

Quoting Govindapillai, Vinod (2025-11-04 13:35:43-03:00)
>Hi Matt,
>
>
>On Mon, 2025-11-03 at 16:15 -0800, Matt Roper wrote:
>> On Mon, Nov 03, 2025 at 02:18:12PM -0300, Gustavo Sousa wrote:
>> > From: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> > 
>> > Configure one of the FBC instances to use system caching. FBC
>> > read/write requests are tagged as cacheable till a programmed
>> > limit is reached by the hw.
>> 
>> What exactly is "system caching?"  We have lots of different caches
>> in
>> current platforms, and it's not really obvious to me from the
>> description here (or the bspec page) exactly which cache(s) are
>> involved
>> here.
>> 
>> Is turning this on always a win or is it situational?  I.e., is there
>> any potential for display memory traffic to fill a cache with FBC
>> data
>> by evicting data that was part of the CPU or GT's working set?  If
>> so,
>> that seems like it could potentially harm the performance of other
>> workloads running on the platform.
>> 
>> Or is this whole thing about a completely new cache (unrelated to
>> and unusable by anything else) which is devoted solely to FBC?
>> 
>> > 
>> > Bspec: 74722
>> 
>> You might want to add 68881 here since it has a bit more information
>> about how we're actually supposed to set the fields documented on
>> 74722.
>
>Okay I will include that. I guess, the HAS also talks about "system
>cache" - no further explanation. But only a fixed portion is allocated
>specifically for the display use and is "configurable". Motivation is
>to reduce to memory subsystem power especially in idle scenarios.
>
>> 
>> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_fbc.c      | 47
>> > +++++++++++++++++++++++++++
>> >  drivers/gpu/drm/i915/display/intel_fbc_regs.h |  9 +++++
>> >  2 files changed, 56 insertions(+)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > index 24b72951ea3c..e2e55c58ddbc 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > @@ -127,6 +127,9 @@ struct intel_fbc {
>> >           */
>> >          struct intel_fbc_state state;
>> >          const char *no_fbc_reason;
>> > +
>> > +        /* Only one of FBC instances can use the system cache */
>> > +        bool own_sys_cache;
>> >  };
>> >  
>> >  static char fbc_name(enum intel_fbc_id fbc_id)
>> > @@ -569,12 +572,51 @@ static bool ilk_fbc_is_compressing(struct
>> > intel_fbc *fbc)
>> >          return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc-
>> > >id)) & DPFC_COMP_SEG_MASK;
>> >  }
>> >  
>> > +static void nvl_fbc_program_system_cache(struct intel_fbc *fbc,
>> > bool enable)
>> > +{
>> > +        struct intel_display *display = fbc->display;
>> > +        u32 cfb_offset, usage;
>> > +
>> > +        lockdep_assert_held(&fbc->lock);
>> > +
>> > +        usage = intel_de_read(display,
>> > NVL_FBC_SYS_CACHE_USAGE_CFG);
>> > +
>> > +        /* System cache already being used by another pipe */
>> > +        if (enable && (usage & FBC_SYS_CACHE_TAG_USE_RES_SPACE))
>> > +                return;
>> 
>> Rather than relying on the current register contents, should we be
>> sanitizing this on driver probe (in case the pre-OS firmware already
>> set
>> this up) and then making our own decisions (as part of an atomic
>> transaction) about which pipe to prioritize after that?
>
>
>> 
>> > +
>> > +        /* Only the fbc instance which owns system cache can
>> > disable it */
>> > +        if (!enable && !fbc->own_sys_cache)
>> > +                return;
>> > +
>> > +        /*
>> > +         * Not programming the cache limit and cache reading
>> > enable bits explicitly
>> > +         * here. The default values should take care of those and
>> > that could leave
>> > +         * adjustments of those bits to the system hw policy
>> > +         *
>> > +         * TODO: check if we need to explicitly program these?
>> 
>> There's no hardware default documented for the range field, so unless
>> the pre-OS firmware sets it up (which we probably shouldn't rely on),
>> I'd expect this to be 0; I don't think that's what we want.
>
>The Bspec says it is 2MB. But according to the HAS it is "configurable"
>and I clarified that this is at the moment 2MB but can change. So I
>read it as something already configured and set as the default value to
>the register and it could be changed by the soc policy. Thats the
>reason I thought it be kept untouched. Will forward on email
>conversation I had.
>
>
>> 
>> > +         */
>> > +        cfb_offset = enable ? i915_gem_stolen_node_offset(fbc-
>> > >compressed_fb) : 0;
>> > +        usage |= FBC_SYS_CACHE_START_BASE(cfb_offset);
>> 
>> And if something *did* set this up already, then OR'ing a new address
>> over the old one isn't going to work.  We'd need "(old & ~mask) |
>> new"
>> to ensure we don't have leftover bits still set by accident.  But it
>> would probably be better to just avoid RMW-style handling in general
>> and
>> build a complete register value with exactly what we want rather than
>> trying to modify the pre-existing value.
>> 
>> > +        usage |= enable ? FBC_SYS_CACHE_TAG_USE_RES_SPACE :
>> > FBC_SYS_CACHE_TAG_DONT_CACHE;
>> > +
>> > +        intel_de_write(display, NVL_FBC_SYS_CACHE_USAGE_CFG,
>> > usage);
>> > +
>> > +        fbc->own_sys_cache = enable;
>
>Okay. Thanks. Will fix that!
>
>> 
>> It feels like instead of having this as a boolean flag in fbc, this
>> should be a pointer/ID tracked at the intel_display level.  E.g.,
>> 
>>         display->sys_cache_fbc = fbc;
>> 
>> or possibly converted over to something tracked with atomic state so
>> that we can make better high-level decisions about which FBC we want
>> to
>> enable this on as various displays get enabled/disabled.
>
>Okay. Will check this and get rid of the bool from the intel_fbc
>structure! At the moment we can allocate only based on the firt pipe
>enabling the fbc. But may be in future we could have some logic for
>this I guess.


Vinod, based on your replies here, I'm assuming you are going to send an
updated version of this patch.  I'll drop it in the v4 of this series.

--
Gustavo Sousa

>
>> Matt
>> 
>> > +
>> > +        drm_dbg_kms(display->drm, "System caching for FBC[%d]
>> > %s\n",
>> > +                    fbc->id, enable ? "configured" : "cleared");
>> > +}
>> > +
>> >  static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
>> >  {
>> >          struct intel_display *display = fbc->display;
>> >  
>> >          intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
>> >                         i915_gem_stolen_node_offset(fbc-
>> > >compressed_fb));
>> > +
>> > +        if (DISPLAY_VER(display) >= 35)
>> > +                nvl_fbc_program_system_cache(fbc, true);
>> >  }
>> >  
>> >  static const struct intel_fbc_funcs ilk_fbc_funcs = {
>> > @@ -952,6 +994,8 @@ static void
>> > intel_fbc_program_workarounds(struct intel_fbc *fbc)
>> >  
>> >  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>> >  {
>> > +        struct intel_display *display = fbc->display;
>> > +
>> >          if (WARN_ON(intel_fbc_hw_is_active(fbc)))
>> >                  return;
>> >  
>> > @@ -959,6 +1003,9 @@ static void __intel_fbc_cleanup_cfb(struct
>> > intel_fbc *fbc)
>> >                  i915_gem_stolen_remove_node(fbc->compressed_llb);
>> >          if (i915_gem_stolen_node_allocated(fbc->compressed_fb))
>> >                  i915_gem_stolen_remove_node(fbc->compressed_fb);
>> > +
>> > +        if (DISPLAY_VER(display) >= 35)
>> > +                nvl_fbc_program_system_cache(fbc, false);
>> >  }
>> >  
>> >  void intel_fbc_cleanup(struct intel_display *display)
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > index 77d8321c4fb3..592cd2384255 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > @@ -128,4 +128,13 @@
>> >  #define   FBC_REND_NUKE                        REG_BIT(2)
>> >  #define   FBC_REND_CACHE_CLEAN                REG_BIT(1)
>> >  
>> > +#define NVL_FBC_SYS_CACHE_USAGE_CFG             _MMIO(0x1344E0)
>> > +#define   FBC_SYS_CACHE_START_BASE_MASK         REG_GENMASK(31,
>> > 16)
>> > +#define   FBC_SYS_CACHE_START_BASE(base)       
>> > REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
>> > +#define   FBC_SYS_CACHEABLE_RANGE_MASK          REG_GENMASK(15, 4)
>> > +#define   FBC_SYS_CACHEABLE_RANGE(range)       
>> > REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
>> > +#define   FBC_SYS_CACHE_TAG_MASK                REG_GENMASK(3, 2)
>> > +#define   FBC_SYS_CACHE_TAG_DONT_CACHE         
>> > REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
>> > +#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE      
>> > REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
>> > +
>> >  #endif /* __INTEL_FBC_REGS__ */
>> > 
>> > -- 
>> > 2.51.0
>> > 
>> 
>

Re: [PATCH v3 21/29] drm/i915/xe3p_lpd: Enable system caching for FBC

[Govindapillai, Vinod]

On Fri, 2025-11-07 at 20:22 -0300, Gustavo Sousa wrote:
> Quoting Govindapillai, Vinod (2025-11-04 13:35:43-03:00)
> > Hi Matt,
> > 
> > 
> > On Mon, 2025-11-03 at 16:15 -0800, Matt Roper wrote:
> > > On Mon, Nov 03, 2025 at 02:18:12PM -0300, Gustavo Sousa wrote:
> > > > From: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > > > 
> > > > Configure one of the FBC instances to use system caching. FBC
> > > > read/write requests are tagged as cacheable till a programmed
> > > > limit is reached by the hw.
> > > 
> > > What exactly is "system caching?"  We have lots of different
> > > caches
> > > in
> > > current platforms, and it's not really obvious to me from the
> > > description here (or the bspec page) exactly which cache(s) are
> > > involved
> > > here.
> > > 
> > > Is turning this on always a win or is it situational?  I.e., is
> > > there
> > > any potential for display memory traffic to fill a cache with FBC
> > > data
> > > by evicting data that was part of the CPU or GT's working set? 
> > > If
> > > so,
> > > that seems like it could potentially harm the performance of
> > > other
> > > workloads running on the platform.
> > > 
> > > Or is this whole thing about a completely new cache (unrelated to
> > > and unusable by anything else) which is devoted solely to FBC?
> > > 
> > > > 
> > > > Bspec: 74722
> > > 
> > > You might want to add 68881 here since it has a bit more
> > > information
> > > about how we're actually supposed to set the fields documented on
> > > 74722.
> > 
> > Okay I will include that. I guess, the HAS also talks about "system
> > cache" - no further explanation. But only a fixed portion is
> > allocated
> > specifically for the display use and is "configurable". Motivation
> > is
> > to reduce to memory subsystem power especially in idle scenarios.
> > 
> > > 
> > > > Signed-off-by: Vinod Govindapillai
> > > > <vinod.govindapillai@intel.com>
> > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_fbc.c      | 47
> > > > +++++++++++++++++++++++++++
> > > >  drivers/gpu/drm/i915/display/intel_fbc_regs.h |  9 +++++
> > > >  2 files changed, 56 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > index 24b72951ea3c..e2e55c58ddbc 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > @@ -127,6 +127,9 @@ struct intel_fbc {
> > > >           */
> > > >          struct intel_fbc_state state;
> > > >          const char *no_fbc_reason;
> > > > +
> > > > +        /* Only one of FBC instances can use the system cache
> > > > */
> > > > +        bool own_sys_cache;
> > > >  };
> > > >  
> > > >  static char fbc_name(enum intel_fbc_id fbc_id)
> > > > @@ -569,12 +572,51 @@ static bool ilk_fbc_is_compressing(struct
> > > > intel_fbc *fbc)
> > > >          return intel_de_read(fbc->display,
> > > > ILK_DPFC_STATUS(fbc-
> > > > > id)) & DPFC_COMP_SEG_MASK;
> > > >  }
> > > >  
> > > > +static void nvl_fbc_program_system_cache(struct intel_fbc
> > > > *fbc,
> > > > bool enable)
> > > > +{
> > > > +        struct intel_display *display = fbc->display;
> > > > +        u32 cfb_offset, usage;
> > > > +
> > > > +        lockdep_assert_held(&fbc->lock);
> > > > +
> > > > +        usage = intel_de_read(display,
> > > > NVL_FBC_SYS_CACHE_USAGE_CFG);
> > > > +
> > > > +        /* System cache already being used by another pipe */
> > > > +        if (enable && (usage &
> > > > FBC_SYS_CACHE_TAG_USE_RES_SPACE))
> > > > +                return;
> > > 
> > > Rather than relying on the current register contents, should we
> > > be
> > > sanitizing this on driver probe (in case the pre-OS firmware
> > > already
> > > set
> > > this up) and then making our own decisions (as part of an atomic
> > > transaction) about which pipe to prioritize after that?
> > 
> > 
> > > 
> > > > +
> > > > +        /* Only the fbc instance which owns system cache can
> > > > disable it */
> > > > +        if (!enable && !fbc->own_sys_cache)
> > > > +                return;
> > > > +
> > > > +        /*
> > > > +         * Not programming the cache limit and cache reading
> > > > enable bits explicitly
> > > > +         * here. The default values should take care of those
> > > > and
> > > > that could leave
> > > > +         * adjustments of those bits to the system hw policy
> > > > +         *
> > > > +         * TODO: check if we need to explicitly program these?
> > > 
> > > There's no hardware default documented for the range field, so
> > > unless
> > > the pre-OS firmware sets it up (which we probably shouldn't rely
> > > on),
> > > I'd expect this to be 0; I don't think that's what we want.
> > 
> > The Bspec says it is 2MB. But according to the HAS it is
> > "configurable"
> > and I clarified that this is at the moment 2MB but can change. So I
> > read it as something already configured and set as the default
> > value to
> > the register and it could be changed by the soc policy. Thats the
> > reason I thought it be kept untouched. Will forward on email
> > conversation I had.
> > 
> > 
> > > 
> > > > +         */
> > > > +        cfb_offset = enable ? i915_gem_stolen_node_offset(fbc-
> > > > > compressed_fb) : 0;
> > > > +        usage |= FBC_SYS_CACHE_START_BASE(cfb_offset);
> > > 
> > > And if something *did* set this up already, then OR'ing a new
> > > address
> > > over the old one isn't going to work.  We'd need "(old & ~mask) |
> > > new"
> > > to ensure we don't have leftover bits still set by accident.  But
> > > it
> > > would probably be better to just avoid RMW-style handling in
> > > general
> > > and
> > > build a complete register value with exactly what we want rather
> > > than
> > > trying to modify the pre-existing value.
> > > 
> > > > +        usage |= enable ? FBC_SYS_CACHE_TAG_USE_RES_SPACE :
> > > > FBC_SYS_CACHE_TAG_DONT_CACHE;
> > > > +
> > > > +        intel_de_write(display, NVL_FBC_SYS_CACHE_USAGE_CFG,
> > > > usage);
> > > > +
> > > > +        fbc->own_sys_cache = enable;
> > 
> > Okay. Thanks. Will fix that!
> > 
> > > 
> > > It feels like instead of having this as a boolean flag in fbc,
> > > this
> > > should be a pointer/ID tracked at the intel_display level.  E.g.,
> > > 
> > >         display->sys_cache_fbc = fbc;
> > > 
> > > or possibly converted over to something tracked with atomic state
> > > so
> > > that we can make better high-level decisions about which FBC we
> > > want
> > > to
> > > enable this on as various displays get enabled/disabled.
> > 
> > Okay. Will check this and get rid of the bool from the intel_fbc
> > structure! At the moment we can allocate only based on the firt
> > pipe
> > enabling the fbc. But may be in future we could have some logic for
> > this I guess.
> 
> 
> Vinod, based on your replies here, I'm assuming you are going to send
> an
> updated version of this patch.  I'll drop it in the v4 of this
> series.
> 
> --
> Gustavo Sousa

Yes. I am working on this. Will update this one separately.

Thanks
Vinod

> 
> > 
> > > Matt
> > > 
> > > > +
> > > > +        drm_dbg_kms(display->drm, "System caching for FBC[%d]
> > > > %s\n",
> > > > +                    fbc->id, enable ? "configured" :
> > > > "cleared");
> > > > +}
> > > > +
> > > >  static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
> > > >  {
> > > >          struct intel_display *display = fbc->display;
> > > >  
> > > >          intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
> > > >                         i915_gem_stolen_node_offset(fbc-
> > > > > compressed_fb));
> > > > +
> > > > +        if (DISPLAY_VER(display) >= 35)
> > > > +                nvl_fbc_program_system_cache(fbc, true);
> > > >  }
> > > >  
> > > >  static const struct intel_fbc_funcs ilk_fbc_funcs = {
> > > > @@ -952,6 +994,8 @@ static void
> > > > intel_fbc_program_workarounds(struct intel_fbc *fbc)
> > > >  
> > > >  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
> > > >  {
> > > > +        struct intel_display *display = fbc->display;
> > > > +
> > > >          if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> > > >                  return;
> > > >  
> > > > @@ -959,6 +1003,9 @@ static void __intel_fbc_cleanup_cfb(struct
> > > > intel_fbc *fbc)
> > > >                  i915_gem_stolen_remove_node(fbc-
> > > > >compressed_llb);
> > > >          if (i915_gem_stolen_node_allocated(fbc-
> > > > >compressed_fb))
> > > >                  i915_gem_stolen_remove_node(fbc-
> > > > >compressed_fb);
> > > > +
> > > > +        if (DISPLAY_VER(display) >= 35)
> > > > +                nvl_fbc_program_system_cache(fbc, false);
> > > >  }
> > > >  
> > > >  void intel_fbc_cleanup(struct intel_display *display)
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > > index 77d8321c4fb3..592cd2384255 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > > @@ -128,4 +128,13 @@
> > > >  #define   FBC_REND_NUKE                        REG_BIT(2)
> > > >  #define   FBC_REND_CACHE_CLEAN                REG_BIT(1)
> > > >  
> > > > +#define NVL_FBC_SYS_CACHE_USAGE_CFG            
> > > > _MMIO(0x1344E0)
> > > > +#define   FBC_SYS_CACHE_START_BASE_MASK        
> > > > REG_GENMASK(31,
> > > > 16)
> > > > +#define   FBC_SYS_CACHE_START_BASE(base)       
> > > > REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
> > > > +#define   FBC_SYS_CACHEABLE_RANGE_MASK         
> > > > REG_GENMASK(15, 4)
> > > > +#define   FBC_SYS_CACHEABLE_RANGE(range)       
> > > > REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
> > > > +#define   FBC_SYS_CACHE_TAG_MASK                REG_GENMASK(3,
> > > > 2)
> > > > +#define   FBC_SYS_CACHE_TAG_DONT_CACHE         
> > > > REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
> > > > +#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE      
> > > > REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
> > > > +
> > > >  #endif /* __INTEL_FBC_REGS__ */
> > > > 
> > > > -- 
> > > > 2.51.0
> > > > 
> > > 
> > 

[PATCH v3 22/29] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Gustavo Sousa]

VBT version 264 adds new fields associated to Xe3p_LPD's new ways of
configuring SoC for TC ports and PHYs.  Update the code to match the
updates in VBT.

The new field dedicated_external is used to represent TC ports that are
connected to PHYs outside of the Type-C subsystem, meaning that they
behave like dedicated ports and don't require the extra Type-C
programming.  In an upcoming change, we will update the driver to take
this field into consideration when detecting the type of port.

The new field dyn_port_over_tc is used to inform that the TC port can be
dynamically allocated for a legacy connector in the Type-C subsystem,
which is a new feature in Xe3p_LPD.  In upcoming changes, we will use
that field in order to handle the IOM resource management programming
required for that.

Note that, when dedicated_external is set, the fields dp_usb_type_c and
tbt are tagged as "don't care" in the spec, so they should be ignored in
that case, so also add a sanitization function to take care of forcing
them to zero when dedicated_external is true.

v2:
  - Use sanitization function to force dp_usb_type_c and tbt fields to
    be zero instead of adding a
    intel_bios_encoder_is_dedicated_external() check in each of their
    respective accessor functions. (Jani)
  - Print info about dedicated external ports in print_ddi_port().
    (Jani)

Bspec: 20124, 68954, 74304
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 54 ++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bios.h     |  2 +
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  3 +-
 3 files changed, 56 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 852e4d6db8a3..1487d5e5a69d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2530,6 +2530,36 @@ intel_bios_encoder_reject_edp_rate(const struct intel_bios_encoder_data *devdata
 	return devdata->child.edp_data_rate_override & edp_rate_override_mask(rate);
 }
 
+static void sanitize_dedicated_external(struct intel_bios_encoder_data *devdata,
+					enum port port)
+{
+	struct intel_display *display = devdata->display;
+
+	if (!intel_bios_encoder_is_dedicated_external(devdata))
+		return;
+
+	/*
+	 * Fields dp_usb_type_c and tbt must be ignored when
+	 * dedicated_external is set.  Since dedicated_external is for
+	 * ports connected to PHYs outside of the Type-C subsystem, it
+	 * is safe to force those fields to zero.
+	 */
+
+	if (devdata->child.dp_usb_type_c) {
+		drm_dbg_kms(display->drm,
+			    "VBT claims Port %c supports USB Type-C, but the port is dedicated external, ignoring\n",
+			    port_name(port));
+		devdata->child.dp_usb_type_c = 0;
+	}
+
+	if (devdata->child.tbt) {
+		drm_dbg_kms(display->drm,
+			    "VBT claims Port %c supports TBT, but the port is dedicated external, ignoring\n",
+			    port_name(port));
+		devdata->child.tbt = 0;
+	}
+}
+
 static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
 				 enum port port)
 {
@@ -2668,7 +2698,8 @@ static void print_ddi_port(const struct intel_bios_encoder_data *devdata)
 {
 	struct intel_display *display = devdata->display;
 	const struct child_device_config *child = &devdata->child;
-	bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt, supports_typec_usb, supports_tbt;
+	bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt, supports_typec_usb,
+		supports_tbt, dedicated_external;
 	int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock;
 	enum port port;
 
@@ -2694,6 +2725,12 @@ static void print_ddi_port(const struct intel_bios_encoder_data *devdata)
 		    supports_typec_usb, supports_tbt,
 		    devdata->dsc != NULL);
 
+	dedicated_external = intel_bios_encoder_is_dedicated_external(devdata);
+	if (dedicated_external)
+		drm_dbg_kms(display->drm,
+			    "Port %c is dedicated external\n",
+			    port_name(port));
+
 	hdmi_level_shift = intel_bios_hdmi_level_shift(devdata);
 	if (hdmi_level_shift >= 0) {
 		drm_dbg_kms(display->drm,
@@ -2751,6 +2788,7 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
 		return;
 	}
 
+	sanitize_dedicated_external(devdata, port);
 	sanitize_device_type(devdata, port);
 	sanitize_hdmi_level_shift(devdata, port);
 }
@@ -2778,7 +2816,7 @@ static int child_device_expected_size(u16 version)
 {
 	BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
 
-	if (version > 263)
+	if (version > 264)
 		return -ENOENT;
 	else if (version >= 263)
 		return 44;
@@ -3723,6 +3761,18 @@ bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devda
 	return devdata->display->vbt.version >= 209 && devdata->child.tbt;
 }
 
+bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata)
+{
+	return devdata->display->vbt.version >= 264 &&
+		devdata->child.dedicated_external;
+}
+
+bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata)
+{
+	return devdata->display->vbt.version >= 264 &&
+		devdata->child.dyn_port_over_tc;
+}
+
 bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)
 {
 	return devdata && devdata->child.lane_reversal;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index f9e438b2787b..75dff27b4228 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -79,6 +79,8 @@ bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdat
 bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
+bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata);
+bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 70e31520c560..57fda5824c9c 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -554,7 +554,8 @@ struct child_device_config {
 	u8 dvo_function;
 	u8 dp_usb_type_c:1;					/* 195+ */
 	u8 tbt:1;						/* 209+ */
-	u8 flags2_reserved:2;					/* 195+ */
+	u8 dedicated_external:1;				/* 264+ */
+	u8 dyn_port_over_tc:1;					/* 264+ */
 	u8 dp_port_trace_length:4;				/* 209+ */
 	u8 dp_gpio_index;					/* 195+ */
 	u16 dp_gpio_pin_num;					/* 195+ */

-- 
2.51.0

[PATCH v3 23/29] drm/i915/power: Use intel_encoder_is_tc()

[Gustavo Sousa]

Starting with Xe3p_LPD, when intel_phy_is_tc() returns true, it does
not necessarily mean that the port is connected to a PHY in the Type-C
subsystem.  The reason is that there is now a VBT field called
dedicated_external that will indicate that a Type-C capable port is
connected to a (most likely) combo/dedicated PHY.  When that's the case,
we must not do the extra programming required for Type-C connections.

In an upcoming change, we will modify intel_encoder_is_tc() to take the
VBT field dedicated_external into consideration.  Update
intel_display_power_well.c to use that function instead of
intel_phy_is_tc().

Note that, even though icl_aux_power_well_{enable,disable} are not part
of Xe3p_LPD's display paths, we modify them anyway for uniformity.

Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 .../drm/i915/display/intel_display_power_well.c    | 26 +++++++++++++++-------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index eab7019f2252..1485fc65ab87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -258,8 +258,9 @@ aux_ch_to_digital_port(struct intel_display *display,
 	return NULL;
 }
 
-static enum phy icl_aux_pw_to_phy(struct intel_display *display,
-				  const struct i915_power_well *power_well)
+static struct intel_encoder *
+icl_aux_pw_to_encoder(struct intel_display *display,
+		      const struct i915_power_well *power_well)
 {
 	enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
 	struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
@@ -271,7 +272,15 @@ static enum phy icl_aux_pw_to_phy(struct intel_display *display,
 	 * as HDMI-only and routed to a combo PHY, the encoder either won't be
 	 * present at all or it will not have an aux_ch assigned.
 	 */
-	return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE;
+	return dig_port ? &dig_port->base : NULL;
+}
+
+static enum phy icl_aux_pw_to_phy(struct intel_display *display,
+				  const struct i915_power_well *power_well)
+{
+	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
+
+	return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE;
 }
 
 static void hsw_wait_for_power_well_enable(struct intel_display *display,
@@ -570,9 +579,9 @@ static void
 icl_aux_power_well_enable(struct intel_display *display,
 			  struct i915_power_well *power_well)
 {
-	enum phy phy = icl_aux_pw_to_phy(display, power_well);
+	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
 
-	if (intel_phy_is_tc(display, phy))
+	if (encoder && intel_encoder_is_tc(encoder))
 		return icl_tc_phy_aux_power_well_enable(display, power_well);
 	else if (display->platform.icelake)
 		return icl_combo_phy_aux_power_well_enable(display,
@@ -585,9 +594,9 @@ static void
 icl_aux_power_well_disable(struct intel_display *display,
 			   struct i915_power_well *power_well)
 {
-	enum phy phy = icl_aux_pw_to_phy(display, power_well);
+	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
 
-	if (intel_phy_is_tc(display, phy))
+	if (encoder && intel_encoder_is_tc(encoder))
 		return hsw_power_well_disable(display, power_well);
 	else if (display->platform.icelake)
 		return icl_combo_phy_aux_power_well_disable(display,
@@ -1849,10 +1858,11 @@ tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display,
 static void xelpdp_aux_power_well_enable(struct intel_display *display,
 					 struct i915_power_well *power_well)
 {
+	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
 	enum phy phy = icl_aux_pw_to_phy(display, power_well);
 
-	if (intel_phy_is_tc(display, phy))
+	if (encoder && intel_encoder_is_tc(encoder))
 		icl_tc_port_assert_ref_held(display, power_well,
 					    aux_ch_to_digital_port(display, aux_ch));
 

-- 
2.51.0

[PATCH v3 24/29] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()

[Gustavo Sousa]

Starting with Xe3p_LPD, the VBT has a new field, called in the driver
"dedicated_external", which tells that a Type-C capable port is
physically connected to a PHY outside of the Type-C subsystem.  When
that's the case, the driver must not do the extra Type-C programming for
that port.  Update intel_encoder_is_tc() to check for that case.

While at it, add a note to intel_phy_is_tc() to remind us that it is
about whether the respective port is a Type-C capable port rather than
the PHY itself.

(Maybe it would be a nice idea to rename intel_phy_is_tc()?)

Note that this was handled with a new bool member added to struct
intel_digital_port instead of having querying the VBT directly because
VBT memory is freed (intel_bios_driver_remove) before encoder cleanup
(intel_ddi_encoder_destroy), which would cause an oops to happen when
the latter calls intel_encoder_is_tc().  This could be fixed by keeping
VBT data around longer, but that's left for a follow-up work, if deemed
necessary.

v2:
  - Drop printing info about dedicated external, now that we are doing
    it when parsing the VBT. (Jani)
  - Add a FIXME comment on the code explaining why we need to store
    dedicated_external in struct intel_digital_port. (Jani)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c           | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_display.c       | 19 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 733ef4559131..d9aaeafd1570 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5376,6 +5376,17 @@ void intel_ddi_init(struct intel_display *display,
 			goto err;
 	}
 
+	/*
+	 * FIXME: We currently need to store dedicated_external because devdata
+	 * does not live long enough for when intel_encoder_is_tc() is called on
+	 * the unbind path.  This needs to be fixed by making sure that the VBT
+	 * data is kept long enough, so that
+	 * intel_bios_encoder_is_dedicated_external() can be called directly
+	 * from intel_encoder_is_tc().
+	 */
+	if (intel_bios_encoder_is_dedicated_external(devdata))
+		dig_port->dedicated_external = true;
+
 	if (intel_encoder_is_tc(encoder)) {
 		bool is_legacy =
 			!intel_bios_encoder_supports_typec_usb(devdata) &&
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 25986bd8fbdd..431f7f030a9b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1800,7 +1800,17 @@ bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
 		return false;
 }
 
-/* Prefer intel_encoder_is_tc() */
+/*
+ * This function returns true if the DDI port respective to the PHY enumeration
+ * is a Type-C capable port.
+ *
+ * Depending on the VBT, the port might be configured
+ * as a "dedicated external" port, meaning that actual physical PHY is outside
+ * of the Type-C subsystem and, as such, not really a "Type-C PHY".
+ *
+ * Prefer intel_encoder_is_tc(), especially if you really need to know if we
+ * are dealing with Type-C connections.
+ */
 bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
 {
 	/*
@@ -1885,6 +1895,13 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 
+	if (intel_encoder_is_dig_port(encoder)) {
+		struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+		if (dig_port->dedicated_external)
+			return false;
+	}
+
 	return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 00600134bda0..8bf392bc0d5d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1937,6 +1937,7 @@ struct intel_digital_port {
 	bool lane_reversal;
 	bool ddi_a_4_lanes;
 	bool release_cl2_override;
+	bool dedicated_external;
 	u8 max_lanes;
 	/* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
 	enum aux_ch aux_ch;

-- 
2.51.0

[PATCH v3 25/29] drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation

[Gustavo Sousa]

Xe3p_LPD has a new feature that allows the driver to allocate at runtime
the DDI (TC ones) port to drive a legacy connection on the Type-C
subsystem.  This allows better resource utilization, because now there
is no need to statically reserve ports for legacy connectors on the
Type-C subsystem.

That said, our driver is not yet ready for the dynamic allocation.
Thus, as an incremental step, let's add the logic containing the
required programming sequence for the allocation, but, instead of
selecting the first available port, we try so use the 1:1 mapping
expected by the driver today.

Bspec: 68954
Co-developed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---

NOTE: This patch is still a WIP. There are some opens to resolve here.
Nevertheless, I'm sending it here for early feedback.

For the HIP-index stuff, I have a local refactor started and need to
finish it up and send it.

The other open is about concurrent calls to iom_dp_resource_lock().  It
is likely that we need to have a software lock to prevent concurrent
access to IOM_DP_HW_RESOURCE_SEMAPHORE from our driver.
---
 drivers/gpu/drm/i915/display/intel_display_regs.h |  20 ++-
 drivers/gpu/drm/i915/display/intel_tc.c           | 151 +++++++++++++++++++++-
 2 files changed, 169 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index c9f8b90faa42..21600dee2603 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2912,6 +2912,25 @@ enum skl_power_gate {
 #define   DP_PIN_ASSIGNMENT(idx, x)		((x) << ((idx) * 4))
 /* See enum intel_tc_pin_assignment for the pin assignment field values. */
 
+/*
+ * FIXME: There is also a definition for this register in intel_dkl_phy_regs.h.
+ * We need to consolidate the definitions.
+ */
+#define HIP_INDEX_REG0				_MMIO(0x1010a0)
+#define   HIP_168_INDEX_MASK			REG_GENMASK(3, 0)
+#define   HIP_168_IOM_RES_MGMT			REG_FIELD_PREP(HIP_168_INDEX_MASK, 0x1)
+
+#define IOM_DP_HW_RESOURCE_SEMAPHORE		_MMIO(0x168038)
+#define   IOM_DP_HW_SEMLOCK			REG_BIT(31)
+#define   IOM_REQUESTOR_ID_MASK			REG_GENMASK(3, 0)
+#define   IOM_REQUESTOR_ID_DISPLAY_ENGINE	REG_FIELD_PREP(IOM_REQUESTOR_ID_MASK, 0x4)
+
+#define IOM_DP_RESOURCE_MNG			_MMIO(0x16802c)
+#define   IOM_DDI_CONSUMER_SHIFT(tc_port)	((tc_port) * 4)
+#define   IOM_DDI_CONSUMER_MASK(tc_port)	(0xf << IOM_DDI_CONSUMER_SHIFT(tc_port))
+#define   IOM_DDI_CONSUMER(tc_port, x)		((x) << IOM_DDI_CONSUMER_SHIFT(tc_port))
+#define   IOM_DDI_CONSUMER_STATIC_TC(tc_port)	IOM_DDI_CONSUMER(tc_port, 0x8 + (tc_port))
+
 #define _TCSS_DDI_STATUS_1			0x161500
 #define _TCSS_DDI_STATUS_2			0x161504
 #define TCSS_DDI_STATUS(tc)			_MMIO(_PICK_EVEN(tc, \
@@ -2950,5 +2969,4 @@ enum skl_power_gate {
 #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
 
 
-
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index f1ed50be3247..3703834c1eeb 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -9,6 +9,7 @@
 
 #include "i915_reg.h"
 #include "intel_atomic.h"
+#include "intel_bios.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
 #include "intel_de.h"
@@ -25,6 +26,9 @@
 #include "intel_modeset_lock.h"
 #include "intel_tc.h"
 
+#define IOM_DP_RES_SEMAPHORE_LOCK_TIMEOUT_US	10
+#define IOM_DP_RES_SEMAPHORE_RETRY_TIMEOUT_US	10000
+
 enum tc_port_mode {
 	TC_PORT_DISCONNECTED,
 	TC_PORT_TBT_ALT,
@@ -1200,6 +1204,143 @@ static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc)
 	__tc_cold_unblock(tc, domain, tc_cold_wref);
 }
 
+static void iom_res_mgmt_prepare_reg_access(struct intel_display *display)
+{
+	/*
+	 * IOM resource management registers live in the 2nd 4KB page of IOM
+	 * address space. So we need to configure HIP_INDEX_REG0 with the
+	 * correct index.
+	 *
+	 * FIXME: We need to have this and dekel PHY implementation using a
+	 * common abstraction to access registers on the HIP-indexed ranges, and
+	 * this function would then be dropped.
+	 */
+	intel_de_rmw(display, HIP_INDEX_REG0,
+		     HIP_168_INDEX_MASK, HIP_168_IOM_RES_MGMT);
+}
+
+/*
+ * FIXME: This function also needs to avoid concurrent accesses from the driver
+ * itself, possibly via a software lock.
+ */
+static int iom_dp_resource_lock(struct intel_tc_port *tc)
+{
+	struct intel_display *display = to_intel_display(tc->dig_port);
+	u32 val = IOM_DP_HW_SEMLOCK | IOM_REQUESTOR_ID_DISPLAY_ENGINE;
+	int ret;
+
+	iom_res_mgmt_prepare_reg_access(display);
+	ret = poll_timeout_us(intel_de_write(display, IOM_DP_HW_RESOURCE_SEMAPHORE, val),
+			      (intel_de_read(display, IOM_DP_HW_RESOURCE_SEMAPHORE) & val) == val,
+			      IOM_DP_RES_SEMAPHORE_LOCK_TIMEOUT_US,
+			      IOM_DP_RES_SEMAPHORE_RETRY_TIMEOUT_US, false);
+
+	if (ret)
+		drm_err(display->drm, "Port %s: timeout trying to lock IOM semaphore\n",
+			tc->port_name);
+
+	return ret;
+}
+
+static void iom_dp_resource_unlock(struct intel_tc_port *tc)
+{
+	struct intel_display *display = to_intel_display(tc->dig_port);
+
+	iom_res_mgmt_prepare_reg_access(display);
+	intel_de_write(display, IOM_DP_HW_RESOURCE_SEMAPHORE, IOM_REQUESTOR_ID_DISPLAY_ENGINE);
+}
+
+static bool xe3p_tc_iom_allocate_ddi(struct intel_tc_port *tc, bool allocate)
+{
+	struct intel_display *display = to_intel_display(tc->dig_port);
+	struct intel_digital_port *dig_port = tc->dig_port;
+	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
+	u32 val;
+	u32 consumer;
+	u32 expected_consumer;
+	bool ret;
+
+	if (DISPLAY_VER(display) < 35)
+		return true;
+
+	if (tc->mode != TC_PORT_LEGACY)
+		return true;
+
+	if (!intel_bios_encoder_supports_dyn_port_over_tc(dig_port->base.devdata))
+		return true;
+
+	if (iom_dp_resource_lock(tc))
+		return false;
+
+	val = intel_de_read(display, IOM_DP_RESOURCE_MNG);
+
+	consumer = val & IOM_DDI_CONSUMER_MASK(tc_port);
+	consumer >>= IOM_DDI_CONSUMER_SHIFT(tc_port);
+
+	/*
+	 * Bspec instructs to select first available DDI, but our driver is not
+	 * ready for such dynamic allocation yet. For now, we force a "static"
+	 * allocation: map the physical port (where HPD happens) to the
+	 * encoder's DDI (logical TC port, represented by tc_port).
+	 */
+	expected_consumer = IOM_DDI_CONSUMER_STATIC_TC(tc_port);
+	expected_consumer >>= IOM_DDI_CONSUMER_SHIFT(tc_port);
+
+	if (allocate) {
+		struct intel_encoder *other_encoder;
+
+		/*
+		 * Check if this encoder's DDI is already allocated for another
+		 * physical port, which could have happened prior to the driver
+		 * taking over (e.g. GOP).
+		 */
+		for_each_intel_encoder(display->drm, other_encoder) {
+			enum tc_port other_tc_port = intel_encoder_to_tc(other_encoder);
+			u32 other_consumer;
+
+			if (tc_port == TC_PORT_NONE || other_tc_port == tc_port)
+				continue;
+
+			other_consumer = val & IOM_DDI_CONSUMER_MASK(other_tc_port);
+			other_consumer >>= IOM_DDI_CONSUMER_SHIFT(other_tc_port);
+			if (other_consumer == expected_consumer) {
+				drm_err(display->drm, "Port %s: expected consumer %u already allocated another DDI; IOM_DP_RESOURCE_MNG=0x%08x\n",
+					tc->port_name, expected_consumer, val);
+				ret = false;
+				goto out_resource_unlock;
+			}
+		}
+
+		if (consumer == 0) {
+			/* DDI is free to use, let's allocate it. */
+			val &= ~IOM_DDI_CONSUMER_MASK(tc_port);
+			val |= IOM_DDI_CONSUMER(tc_port, expected_consumer);
+			intel_de_write(display, IOM_DP_RESOURCE_MNG, val);
+			ret = true;
+		} else if (consumer == expected_consumer) {
+			/*
+			 * Nothing to do, as the expected "static" DDI allocation is
+			 * already in place.
+			 */
+			ret = true;
+		} else {
+			drm_err(display->drm, "Port %s: DDI already allocated for consumer %u; IOM_DP_RESOURCE_MNG=0x%08x\n",
+				tc->port_name, consumer, val);
+			ret = false;
+		}
+	} else {
+		drm_WARN_ON(display->drm, consumer != expected_consumer);
+		val &= ~IOM_DDI_CONSUMER_MASK(tc_port);
+		intel_de_write(display, IOM_DP_RESOURCE_MNG, val);
+		ret = true;
+	}
+
+out_resource_unlock:
+	iom_dp_resource_unlock(tc);
+
+	return ret;
+}
+
 static bool xelpdp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
 {
 	tc->lock_wakeref = tc_cold_block(tc);
@@ -1210,9 +1351,12 @@ static bool xelpdp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
 		return true;
 	}
 
-	if (!xelpdp_tc_phy_enable_tcss_power(tc, true))
+	if (!xe3p_tc_iom_allocate_ddi(tc, true))
 		goto out_unblock_tccold;
 
+	if (!xelpdp_tc_phy_enable_tcss_power(tc, true))
+		goto out_deallocate_ddi;
+
 	xelpdp_tc_phy_take_ownership(tc, true);
 
 	read_pin_configuration(tc);
@@ -1226,6 +1370,9 @@ static bool xelpdp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
 	xelpdp_tc_phy_take_ownership(tc, false);
 	xelpdp_tc_phy_wait_for_tcss_power(tc, false);
 
+out_deallocate_ddi:
+	xe3p_tc_iom_allocate_ddi(tc, false);
+
 out_unblock_tccold:
 	tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
 
@@ -1236,6 +1383,8 @@ static void xelpdp_tc_phy_disconnect(struct intel_tc_port *tc)
 {
 	switch (tc->mode) {
 	case TC_PORT_LEGACY:
+		xe3p_tc_iom_allocate_ddi(tc, false);
+		fallthrough;
 	case TC_PORT_DP_ALT:
 		xelpdp_tc_phy_take_ownership(tc, false);
 		xelpdp_tc_phy_enable_tcss_power(tc, false);

-- 
2.51.0

[PATCH v3 26/29] drm/i915/nvls: Add NVL-S display support

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Add platform description and PCI IDs for NVL-S.

BSpec: 74201
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_display_device.h | 4 +++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 1170afaa8680..471f236c9ddf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1420,6 +1420,10 @@ static const struct platform_desc ptl_desc = {
 	}
 };
 
+static const struct platform_desc nvl_desc = {
+	PLATFORM(novalake),
+};
+
 __diag_pop();
 
 /*
@@ -1495,6 +1499,7 @@ static const struct {
 	INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc),
 	INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
 	INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
+	INTEL_NVLS_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
 };
 
 static const struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index b559ef43d547..4da4b1e3d817 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -103,7 +103,9 @@ struct pci_dev;
 	func(battlemage) \
 	/* Display ver 30 (based on GMD ID) */ \
 	func(pantherlake) \
-	func(pantherlake_wildcatlake)
+	func(pantherlake_wildcatlake) \
+	/* Display ver 35 (based on GMD ID) */ \
+	func(novalake)
 
 
 #define __MEMBER(name) unsigned long name:1;

-- 
2.51.0

[PATCH v3 27/29] drm/i915/display: Use platform check in HAS_LT_PHY()

[Gustavo Sousa]

NVL uses the Lake Tahoe PHY for display output and the driver recently
added the macro HAS_LT_PHY() to allow selecting code paths specific for
that type of PHY.

While NVL uses Xe3p_LPD as display IP, the type of PHY is actually
defined at the SoC level, so use a platform check instead of display
version.

Bspec: 74199
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index a538d4c69210..034c20c66baf 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -39,6 +39,6 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 
-#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
+#define HAS_LT_PHY(display) ((display)->platform.novalake)
 
 #endif /* __INTEL_LT_PHY_H__ */

-- 
2.51.0

RE: [PATCH v3 27/29] drm/i915/display: Use platform check in HAS_LT_PHY()

[Bhadane, Dnyaneshwar]

> -----Original Message-----
> From: Sousa, Gustavo <gustavo.sousa@intel.com>
> Sent: Monday, November 3, 2025 10:48 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>; Sousa, Gustavo
> <gustavo.sousa@intel.com>; Hogander, Jouni <jouni.hogander@intel.com>;
> Heikkila, Juha-pekka <juha-pekka.heikkila@intel.com>; Coelho, Luciano
> <luciano.coelho@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>;
> Atwood, Matthew S <matthew.s.atwood@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Vodapalli, Ravi Kumar
> <ravi.kumar.vodapalli@intel.com>; Chauhan, Shekhar
> <shekhar.chauhan@intel.com>; Govindapillai, Vinod
> <vinod.govindapillai@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v3 27/29] drm/i915/display: Use platform check in
> HAS_LT_PHY()
> 
> NVL uses the Lake Tahoe PHY for display output and the driver recently added
> the macro HAS_LT_PHY() to allow selecting code paths specific for that type of
> PHY.
> 
> While NVL uses Xe3p_LPD as display IP, the type of PHY is actually defined at
> the SoC level, so use a platform check instead of display version.
> 
> Bspec: 74199
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index a538d4c69210..034c20c66baf 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -39,6 +39,6 @@ void intel_xe3plpd_pll_enable(struct intel_encoder
> *encoder,
>  			      const struct intel_crtc_state *crtc_state);  void
> intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
> 
> -#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
> +#define HAS_LT_PHY(display) ((display)->platform.novalake)

LGTM,
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>

Dnyaneshwar
> 
>  #endif /* __INTEL_LT_PHY_H__ */
> 
> --
> 2.51.0

Re: [PATCH v3 27/29] drm/i915/display: Use platform check in HAS_LT_PHY()

[Matt Roper]

On Mon, Nov 03, 2025 at 02:18:18PM -0300, Gustavo Sousa wrote:
> NVL uses the Lake Tahoe PHY for display output and the driver recently
> added the macro HAS_LT_PHY() to allow selecting code paths specific for
> that type of PHY.
> 
> While NVL uses Xe3p_LPD as display IP, the type of PHY is actually
> defined at the SoC level, so use a platform check instead of display
> version.
> 
> Bspec: 74199
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Eventually we might need to make this a true feature flag, but this
works for now.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index a538d4c69210..034c20c66baf 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -39,6 +39,6 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *crtc_state);
>  void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
>  
> -#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
> +#define HAS_LT_PHY(display) ((display)->platform.novalake)
>  
>  #endif /* __INTEL_LT_PHY_H__ */
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH v3 27/29] drm/i915/display: Use platform check in HAS_LT_PHY()

[Gustavo Sousa]

Quoting Matt Roper (2025-11-03 14:42:23-03:00)
>On Mon, Nov 03, 2025 at 02:18:18PM -0300, Gustavo Sousa wrote:
>> NVL uses the Lake Tahoe PHY for display output and the driver recently
>> added the macro HAS_LT_PHY() to allow selecting code paths specific for
>> that type of PHY.
>> 
>> While NVL uses Xe3p_LPD as display IP, the type of PHY is actually
>> defined at the SoC level, so use a platform check instead of display
>> version.
>> 
>> Bspec: 74199
>> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>
>Eventually we might need to make this a true feature flag, but this

Agreed.

>works for now.
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

Thanks!

--
Gustavo Sousa

>
>> ---
>>  drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
>> index a538d4c69210..034c20c66baf 100644
>> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
>> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
>> @@ -39,6 +39,6 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>>                                const struct intel_crtc_state *crtc_state);
>>  void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
>>  
>> -#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
>> +#define HAS_LT_PHY(display) ((display)->platform.novalake)
>>  
>>  #endif /* __INTEL_LT_PHY_H__ */
>> 
>> -- 
>> 2.51.0
>> 
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

[PATCH v3 28/29] drm/i915/display: Move HAS_LT_PHY() to intel_display_device.h

[Gustavo Sousa]

We will need to HAS_LT_PHY() that macro in code outside of LT PHY
implementation. Move its definition to intel_display_device.h.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.h         | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 4da4b1e3d817..df464eb0be7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -187,6 +187,7 @@ struct intel_display_platforms {
 #define HAS_IPS(__display)		((__display)->platform.haswell_ult || (__display)->platform.broadwell)
 #define HAS_LRR(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_LSPCON(__display)		(IS_DISPLAY_VER(__display, 9, 10))
+#define HAS_LT_PHY(__display)		((__display)->platform.novalake)
 #define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
 #define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
 #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)->has_overlay)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 034c20c66baf..e52aadfbdf93 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -39,6 +39,4 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 
-#define HAS_LT_PHY(display) ((display)->platform.novalake)
-
 #endif /* __INTEL_LT_PHY_H__ */

-- 
2.51.0

Re: [PATCH v3 28/29] drm/i915/display: Move HAS_LT_PHY() to intel_display_device.h

[Matt Roper]

On Mon, Nov 03, 2025 at 02:18:19PM -0300, Gustavo Sousa wrote:
> We will need to HAS_LT_PHY() that macro in code outside of LT PHY
> implementation. Move its definition to intel_display_device.h.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>  drivers/gpu/drm/i915/display/intel_lt_phy.h         | 2 --
>  2 files changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 4da4b1e3d817..df464eb0be7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -187,6 +187,7 @@ struct intel_display_platforms {
>  #define HAS_IPS(__display)		((__display)->platform.haswell_ult || (__display)->platform.broadwell)
>  #define HAS_LRR(__display)		(DISPLAY_VER(__display) >= 12)
>  #define HAS_LSPCON(__display)		(IS_DISPLAY_VER(__display, 9, 10))
> +#define HAS_LT_PHY(__display)		((__display)->platform.novalake)
>  #define HAS_MBUS_JOINING(__display)	((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14)
>  #define HAS_MSO(__display)		(DISPLAY_VER(__display) >= 12)
>  #define HAS_OVERLAY(__display)		(DISPLAY_INFO(__display)->has_overlay)
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 034c20c66baf..e52aadfbdf93 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -39,6 +39,4 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *crtc_state);
>  void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
>  
> -#define HAS_LT_PHY(display) ((display)->platform.novalake)
> -
>  #endif /* __INTEL_LT_PHY_H__ */
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

[PATCH v3 29/29] drm/i915/display: Use HAS_LT_PHY() for LT PHY AUX power

[Gustavo Sousa]

Bspec states that the new AUX power enable/disable sequences are
associated with the LT PHY.  As such, use HAS_LT_PHY() instead of IP
checks in those paths in the driver code.

While at it, also move the comment that we can't use the power status
flag to the "else" branch, since that comment is not applicable for the
LT PHY.

Bspec: 68967
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 1485fc65ab87..33c9540a5d73 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1870,19 +1870,19 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
 
-	/*
-	 * The power status flag cannot be used to determine whether aux
-	 * power wells have finished powering up.  Instead we're
-	 * expected to just wait a fixed 600us after raising the request
-	 * bit.
-	 */
-	if (DISPLAY_VER(display) >= 35) {
+	if (HAS_LT_PHY(display)) {
 		if (intel_de_wait_for_set(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
 					  XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
 			drm_warn(display->drm,
 				 "Timeout waiting for PHY %c AUX channel power to be up\n",
 				 phy_name(phy));
 	} else {
+		/*
+		 * The power status flag cannot be used to determine whether aux
+		 * power wells have finished powering up.  Instead we're
+		 * expected to just wait a fixed 600us after raising the request
+		 * bit.
+		 */
 		usleep_range(600, 1200);
 	}
 }
@@ -1897,7 +1897,7 @@ static void xelpdp_aux_power_well_disable(struct intel_display *display,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     0);
 
-	if (DISPLAY_VER(display) >= 35) {
+	if (HAS_LT_PHY(display)) {
 		if (intel_de_wait_for_clear(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
 					    XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
 			drm_warn(display->drm,

-- 
2.51.0

Re: [PATCH v3 29/29] drm/i915/display: Use HAS_LT_PHY() for LT PHY AUX power

[Matt Roper]

On Mon, Nov 03, 2025 at 02:18:20PM -0300, Gustavo Sousa wrote:
> Bspec states that the new AUX power enable/disable sequences are
> associated with the LT PHY.  As such, use HAS_LT_PHY() instead of IP
> checks in those paths in the driver code.
> 
> While at it, also move the comment that we can't use the power status
> flag to the "else" branch, since that comment is not applicable for the
> LT PHY.
> 
> Bspec: 68967
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Suraj Kandpal <suraj.kandpal@intel.com>
> Suggested-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 1485fc65ab87..33c9540a5d73 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1870,19 +1870,19 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display,
>  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
>  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
>  
> -	/*
> -	 * The power status flag cannot be used to determine whether aux
> -	 * power wells have finished powering up.  Instead we're
> -	 * expected to just wait a fixed 600us after raising the request
> -	 * bit.
> -	 */
> -	if (DISPLAY_VER(display) >= 35) {
> +	if (HAS_LT_PHY(display)) {
>  		if (intel_de_wait_for_set(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
>  					  XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2))
>  			drm_warn(display->drm,
>  				 "Timeout waiting for PHY %c AUX channel power to be up\n",
>  				 phy_name(phy));
>  	} else {
> +		/*
> +		 * The power status flag cannot be used to determine whether aux
> +		 * power wells have finished powering up.  Instead we're
> +		 * expected to just wait a fixed 600us after raising the request
> +		 * bit.
> +		 */
>  		usleep_range(600, 1200);
>  	}
>  }
> @@ -1897,7 +1897,7 @@ static void xelpdp_aux_power_well_disable(struct intel_display *display,
>  		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
>  		     0);
>  
> -	if (DISPLAY_VER(display) >= 35) {
> +	if (HAS_LT_PHY(display)) {
>  		if (intel_de_wait_for_clear(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
>  					    XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
>  			drm_warn(display->drm,
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

✗ i915.CI.BAT: failure for drm/i915/display: Add initial support for Xe3p_LPD (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2752 bytes --]

== Series Details ==

Series: drm/i915/display: Add initial support for Xe3p_LPD (rev3)
URL   : https://patchwork.freedesktop.org/series/155952/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17479 -> Patchwork_155952v3
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_155952v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_155952v3, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/index.html

Participating hosts (46 -> 45)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_155952v3:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_gttfill@basic:
    - bat-mtlp-9:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/bat-mtlp-9/igt@gem_exec_gttfill@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/bat-mtlp-9/igt@gem_exec_gttfill@basic.html

  
Known issues
------------

  Here are the changes found in Patchwork_155952v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/bat-mtlp-8/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/bat-mtlp-8/igt@i915_selftest@live.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [DMESG-FAIL][5] ([i915#12061]) -> [PASS][6] +1 other test pass
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/bat-dg2-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061


Build changes
-------------

  * Linux: CI_DRM_17479 -> Patchwork_155952v3

  CI-20190529: 20190529
  CI_DRM_17479: 0c721eb082329d9ba1ef257e3cdfa8109ae9de32 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8605: 8605
  Patchwork_155952v3: 0c721eb082329d9ba1ef257e3cdfa8109ae9de32 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/index.html

[-- Attachment #2: Type: text/html, Size: 3481 bytes --]

Re: ✗ i915.CI.BAT: failure for drm/i915/display: Add initial support for Xe3p_LPD (rev3)

[Gustavo Sousa]

Quoting Patchwork (2025-11-03 16:57:56-03:00)
>== Series Details ==
>
>Series: drm/i915/display: Add initial support for Xe3p_LPD (rev3)
>URL   : https://patchwork.freedesktop.org/series/155952/
>State : failure
>
>== Summary ==
>
>CI Bug Log - changes from CI_DRM_17479 -> Patchwork_155952v3
>====================================================
>
>Summary
>-------
>
>  **FAILURE**
>
>  Serious unknown changes coming with Patchwork_155952v3 absolutely need to be
>  verified manually.
>  
>  If you think the reported changes have nothing to do with the changes
>  introduced in Patchwork_155952v3, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
>  to document this new failure mode, which will reduce false positives in CI.
>
>  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/index.html
>
>Participating hosts (46 -> 45)
>------------------------------
>
>  Missing    (1): fi-snb-2520m 
>
>Possible new issues
>-------------------
>
>  Here are the unknown changes that may have been introduced in Patchwork_155952v3:
>
>### IGT changes ###
>
>#### Possible regressions ####
>
>  * igt@gem_exec_gttfill@basic:
>    - bat-mtlp-9:         [PASS][1] -> [INCOMPLETE][2]
>   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/bat-mtlp-9/igt@gem_exec_gttfill@basic.html
>   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/bat-mtlp-9/igt@gem_exec_gttfill@basic.html

This failure happens on MTL and is not display-related.  The error
should be unrelated to the series.

Could you please re-report?

--
Gustavo Sousa

RE: ✗ i915.CI.BAT: failure for drm/i915/display: Add initial support for Xe3p_LPD (rev3)

[Ravali, JupallyX]

Hi,

https://patchwork.freedesktop.org/series/155952/
i915.CI.BAT - Re-reported.

Thanks,
Ravali.

-----Original Message-----
From: I915-ci-infra <i915-ci-infra-bounces@lists.freedesktop.org> On Behalf Of Gustavo Sousa
Sent: 04 November 2025 01:50
To: I915-ci-infra@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ i915.CI.BAT: failure for drm/i915/display: Add initial support for Xe3p_LPD (rev3)

Quoting Patchwork (2025-11-03 16:57:56-03:00)
>== Series Details ==
>
>Series: drm/i915/display: Add initial support for Xe3p_LPD (rev3)
>URL   : https://patchwork.freedesktop.org/series/155952/
>State : failure
>
>== Summary ==
>
>CI Bug Log - changes from CI_DRM_17479 -> Patchwork_155952v3 
>====================================================
>
>Summary
>-------
>
>  **FAILURE**
>
>  Serious unknown changes coming with Patchwork_155952v3 absolutely 
> need to be  verified manually.
>  
>  If you think the reported changes have nothing to do with the changes  
> introduced in Patchwork_155952v3, please notify your bug team 
> (I915-ci-infra@lists.freedesktop.org) to allow them  to document this new failure mode, which will reduce false positives in CI.
>
>  External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/index.html
>
>Participating hosts (46 -> 45)
>------------------------------
>
>  Missing    (1): fi-snb-2520m 
>
>Possible new issues
>-------------------
>
>  Here are the unknown changes that may have been introduced in Patchwork_155952v3:
>
>### IGT changes ###
>
>#### Possible regressions ####
>
>  * igt@gem_exec_gttfill@basic:
>    - bat-mtlp-9:         [PASS][1] -> [INCOMPLETE][2]
>   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/bat-mtlp-9/igt@gem_exec_gttfill@basic.html
>   [2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/bat-mtlp-9
> /igt@gem_exec_gttfill@basic.html

This failure happens on MTL and is not display-related.  The error should be unrelated to the series.

Could you please re-report?

--
Gustavo Sousa

✓ i915.CI.BAT: success for drm/i915/display: Add initial support for Xe3p_LPD (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2318 bytes --]

== Series Details ==

Series: drm/i915/display: Add initial support for Xe3p_LPD (rev3)
URL   : https://patchwork.freedesktop.org/series/155952/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17479 -> Patchwork_155952v3
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/index.html

Participating hosts (46 -> 45)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_155952v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_gttfill@basic:
    - bat-mtlp-9:         [PASS][1] -> [INCOMPLETE][2] ([i915#15230])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/bat-mtlp-9/igt@gem_exec_gttfill@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/bat-mtlp-9/igt@gem_exec_gttfill@basic.html

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/bat-mtlp-8/igt@i915_selftest@live.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/bat-mtlp-8/igt@i915_selftest@live.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [DMESG-FAIL][5] ([i915#12061]) -> [PASS][6] +1 other test pass
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/bat-dg2-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#15230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15230


Build changes
-------------

  * Linux: CI_DRM_17479 -> Patchwork_155952v3

  CI-20190529: 20190529
  CI_DRM_17479: 0c721eb082329d9ba1ef257e3cdfa8109ae9de32 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8605: 8605
  Patchwork_155952v3: 0c721eb082329d9ba1ef257e3cdfa8109ae9de32 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/index.html

[-- Attachment #2: Type: text/html, Size: 3043 bytes --]

✓ i915.CI.Full: success for drm/i915/display: Add initial support for Xe3p_LPD (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 129211 bytes --]

== Series Details ==

Series: drm/i915/display: Add initial support for Xe3p_LPD (rev3)
URL   : https://patchwork.freedesktop.org/series/155952/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17479_full -> Patchwork_155952v3_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 11)
------------------------------

  Additional (1): shard-dg2-set2 

Known issues
------------

  Here are the changes found in Patchwork_155952v3_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-dg2:          NOTRUN -> [SKIP][1] ([i915#8411])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@drm_buddy@drm_buddy@drm_test_buddy_fragmentation_performance:
    - shard-tglu:         NOTRUN -> [DMESG-WARN][2] ([i915#15095]) +1 other test dmesg-warn
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@drm_buddy@drm_buddy@drm_test_buddy_fragmentation_performance.html

  * igt@fbdev@info:
    - shard-rkl:          [PASS][3] -> [SKIP][4] ([i915#14544] / [i915#1849] / [i915#2582])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@fbdev@info.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@fbdev@info.html

  * igt@fbdev@nullptr:
    - shard-rkl:          [PASS][5] -> [SKIP][6] ([i915#14544] / [i915#2582]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@fbdev@nullptr.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@fbdev@nullptr.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-tglu-1:       NOTRUN -> [SKIP][7] ([i915#13008])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-glk:          NOTRUN -> [INCOMPLETE][8] ([i915#13356]) +1 other test incomplete
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk3/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_exec_balancer@parallel:
    - shard-tglu-1:       NOTRUN -> [SKIP][9] ([i915#4525])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#4525])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_big@single:
    - shard-tglu:         NOTRUN -> [ABORT][11] ([i915#11713])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@gem_exec_big@single.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-tglu-1:       NOTRUN -> [SKIP][12] ([i915#6334]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_reloc@basic-gtt-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][13] ([i915#3281]) +3 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@gem_exec_reloc@basic-gtt-cpu.html

  * igt@gem_fence_thrash@bo-write-verify-x:
    - shard-dg2:          NOTRUN -> [SKIP][14] ([i915#4860])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@gem_fence_thrash@bo-write-verify-x.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglu-1:       NOTRUN -> [SKIP][15] ([i915#2190])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-rkl:          NOTRUN -> [SKIP][16] ([i915#4613])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@gem_lmem_swapping@heavy-verify-multi.html
    - shard-tglu:         NOTRUN -> [SKIP][17] ([i915#4613])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
    - shard-glk:          NOTRUN -> [SKIP][18] ([i915#4613]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk9/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][19] ([i915#4613]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [PASS][20] -> [TIMEOUT][21] ([i915#5493]) +1 other test timeout
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg1-12/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_partial_pwrite_pread@write-display:
    - shard-rkl:          NOTRUN -> [SKIP][22] ([i915#3282])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@gem_partial_pwrite_pread@write-display.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-glk:          NOTRUN -> [WARN][23] ([i915#14702] / [i915#2658])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk9/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@create-protected-buffer:
    - shard-rkl:          NOTRUN -> [SKIP][24] ([i915#4270])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@gem_pxp@create-protected-buffer.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-rkl:          [PASS][25] -> [TIMEOUT][26] ([i915#12917] / [i915#12964])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@gem_pxp@protected-raw-src-copy-not-readible.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_readwrite@beyond-eob:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#3282])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@gem_readwrite@beyond-eob.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#4079])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-tglu-1:       NOTRUN -> [SKIP][29] ([i915#3297])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gen9_exec_parse@basic-rejected:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#2856])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@gen9_exec_parse@basic-rejected.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-rkl:          NOTRUN -> [SKIP][31] ([i915#2527]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@gen9_exec_parse@bb-chained.html

  * igt@gen9_exec_parse@unaligned-access:
    - shard-tglu:         NOTRUN -> [SKIP][32] ([i915#2527] / [i915#2856])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@gen9_exec_parse@unaligned-access.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-tglu-1:       NOTRUN -> [SKIP][33] ([i915#2527] / [i915#2856]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_module_load@load:
    - shard-rkl:          ([PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58]) -> ([PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [SKIP][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82]) ([i915#14785])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@i915_module_load@load.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-3/igt@i915_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@i915_module_load@load.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@i915_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-4/igt@i915_module_load@load.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-3/igt@i915_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@i915_module_load@load.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@i915_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@i915_module_load@load.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@i915_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-5/igt@i915_module_load@load.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@i915_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-5/igt@i915_module_load@load.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-5/igt@i915_module_load@load.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-5/igt@i915_module_load@load.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-4/igt@i915_module_load@load.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@i915_module_load@load.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@i915_module_load@load.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@i915_module_load@load.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@i915_module_load@load.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@i915_module_load@load.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@i915_module_load@load.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@i915_module_load@load.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@i915_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@i915_module_load@load.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@i915_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@i915_module_load@load.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@i915_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-7/igt@i915_module_load@load.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@i915_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@i915_module_load@load.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@i915_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@i915_module_load@load.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@i915_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@i915_module_load@load.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@i915_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@i915_module_load@load.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@i915_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@i915_module_load@load.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@i915_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-7/igt@i915_module_load@load.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-7/igt@i915_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@i915_module_load@load.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@i915_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@i915_module_load@load.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@i915_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-7/igt@i915_module_load@load.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@i915_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-3/igt@i915_module_load@load.html

  * igt@i915_module_load@resize-bar:
    - shard-dg2:          [PASS][83] -> [DMESG-WARN][84] ([i915#14545])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg2-8/igt@i915_module_load@resize-bar.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-3/igt@i915_module_load@resize-bar.html
    - shard-tglu-1:       NOTRUN -> [SKIP][85] ([i915#6412])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_api@freq-reset:
    - shard-rkl:          NOTRUN -> [SKIP][86] ([i915#8399])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@i915_pm_freq_api@freq-reset.html
    - shard-tglu:         NOTRUN -> [SKIP][87] ([i915#8399])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@i915_pm_freq_api@freq-reset.html

  * igt@i915_selftest@live@workarounds:
    - shard-dg2:          [PASS][88] -> [DMESG-FAIL][89] ([i915#12061]) +1 other test dmesg-fail
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg2-6/igt@i915_selftest@live@workarounds.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-6/igt@i915_selftest@live@workarounds.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-dg1:          [PASS][90] -> [DMESG-WARN][91] ([i915#4391] / [i915#4423])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg1-12/igt@i915_suspend@basic-s3-without-i915.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg1-18/igt@i915_suspend@basic-s3-without-i915.html

  * igt@i915_suspend@debugfs-reader:
    - shard-rkl:          [PASS][92] -> [INCOMPLETE][93] ([i915#4817])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@i915_suspend@debugfs-reader.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-3/igt@i915_suspend@debugfs-reader.html

  * igt@i915_suspend@forcewake:
    - shard-rkl:          [PASS][94] -> [ABORT][95] ([i915#15140])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@i915_suspend@forcewake.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@i915_suspend@forcewake.html

  * igt@intel_hwmon@hwmon-read:
    - shard-tglu-1:       NOTRUN -> [SKIP][96] ([i915#7707])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@intel_hwmon@hwmon-read.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-glk10:        NOTRUN -> [SKIP][97] ([i915#1769])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk10/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-tglu-1:       NOTRUN -> [SKIP][98] ([i915#5286]) +3 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][99] ([i915#5286]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
    - shard-tglu:         NOTRUN -> [SKIP][100] ([i915#5286])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][101] ([i915#3638])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2:          NOTRUN -> [SKIP][102] ([i915#5190])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-rkl:          NOTRUN -> [SKIP][103] +8 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][104] +30 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][105] ([i915#10307] / [i915#6095]) +84 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-3/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][106] ([i915#12313])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
    - shard-rkl:          NOTRUN -> [SKIP][107] ([i915#12313])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][108] ([i915#6095]) +19 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1:
    - shard-glk10:        NOTRUN -> [SKIP][109] +222 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk10/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#14098] / [i915#6095]) +26 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][111] ([i915#4423] / [i915#6095])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg1-12/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
    - shard-glk:          NOTRUN -> [INCOMPLETE][112] ([i915#12796]) +1 other test incomplete
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk5/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][113] ([i915#6095]) +11 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-3/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][114] ([i915#6095]) +44 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][115] ([i915#6095]) +34 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][116] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-4/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][117] ([i915#6095]) +158 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg1-13/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#13781]) +3 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-1/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#11151] / [i915#7828]) +2 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html
    - shard-tglu:         NOTRUN -> [SKIP][120] ([i915#11151] / [i915#7828]) +3 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-tglu-1:       NOTRUN -> [SKIP][121] ([i915#11151] / [i915#7828]) +2 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-dg2:          NOTRUN -> [SKIP][122] ([i915#11151] / [i915#7828])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_color@ctm-0-25:
    - shard-rkl:          [PASS][123] -> [SKIP][124] ([i915#12655] / [i915#14544]) +3 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_color@ctm-0-25.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_color@ctm-0-25.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][125] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][126] ([i915#3116] / [i915#3299])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-tglu-1:       NOTRUN -> [SKIP][127] ([i915#13049])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-256x256:
    - shard-rkl:          [PASS][128] -> [SKIP][129] ([i915#14544]) +53 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_cursor_crc@cursor-onscreen-256x256.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-256x256.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][130] ([i915#13049])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_cursor_crc@cursor-onscreen-512x512.html
    - shard-rkl:          NOTRUN -> [SKIP][131] ([i915#13049])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([i915#3555])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][133] ([i915#13566]) +1 other test fail
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [FAIL][134] ([i915#13566]) +1 other test fail
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-dg2:          NOTRUN -> [SKIP][135] ([i915#13049])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][136] ([i915#12358] / [i915#14152] / [i915#7882])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk1/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][137] ([i915#12358] / [i915#14152])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk1/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
    - shard-rkl:          [PASS][138] -> [SKIP][139] ([i915#11190] / [i915#14544]) +2 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-rkl:          NOTRUN -> [SKIP][140] ([i915#4103])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-tglu-1:       NOTRUN -> [SKIP][141] ([i915#1769] / [i915#3555] / [i915#3804])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][142] ([i915#3804])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          NOTRUN -> [SKIP][143] ([i915#3555])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-tglu-1:       NOTRUN -> [SKIP][144] ([i915#13707])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-basic:
    - shard-tglu:         NOTRUN -> [SKIP][145] ([i915#3555] / [i915#3840]) +1 other test skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#3840] / [i915#9688])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-rkl:          NOTRUN -> [SKIP][147] ([i915#3555] / [i915#3840])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-rkl:          NOTRUN -> [SKIP][148] ([i915#9934])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_flip@2x-blocking-wf_vblank.html
    - shard-tglu:         NOTRUN -> [SKIP][149] ([i915#3637] / [i915#9934])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-tglu-1:       NOTRUN -> [SKIP][150] ([i915#3637] / [i915#9934]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - shard-rkl:          [PASS][151] -> [SKIP][152] ([i915#14544] / [i915#3637]) +11 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_flip@flip-vs-dpms-on-nop:
    - shard-rkl:          [PASS][153] -> [SKIP][154] ([i915#14544] / [i915#14553])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_flip@flip-vs-dpms-on-nop.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_flip@flip-vs-dpms-on-nop.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg1:          [PASS][155] -> [DMESG-WARN][156] ([i915#4423]) +4 other tests dmesg-warn
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg1-19/igt@kms_flip@flip-vs-suspend.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg1-13/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a3:
    - shard-dg1:          NOTRUN -> [DMESG-WARN][157] ([i915#4423]) +1 other test dmesg-warn
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg1-13/igt@kms_flip@flip-vs-suspend@b-hdmi-a3.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-snb:          [PASS][158] -> [FAIL][159] ([i915#10826]) +1 other test fail
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-snb5/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-snb4/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][160] ([i915#2672]) +4 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-rkl:          [PASS][161] -> [SKIP][162] ([i915#14544] / [i915#3555]) +3 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][163] ([i915#2587] / [i915#2672] / [i915#3555])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][164] ([i915#2672] / [i915#3555])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][165] ([i915#2587] / [i915#2672]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][166] ([i915#2587] / [i915#2672]) +1 other test skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#2672] / [i915#3555]) +1 other test skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
    - shard-tglu:         NOTRUN -> [SKIP][168] ([i915#2672] / [i915#3555]) +1 other test skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-rkl:          [PASS][169] -> [SKIP][170] ([i915#14544] / [i915#1849] / [i915#5354]) +10 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move:
    - shard-tglu:         NOTRUN -> [SKIP][171] +20 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2:          NOTRUN -> [SKIP][172] ([i915#5354]) +3 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-tglu:         NOTRUN -> [SKIP][173] ([i915#15102]) +4 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-wc.html
    - shard-rkl:          NOTRUN -> [SKIP][174] ([i915#15102])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][175] ([i915#15102]) +8 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#15102] / [i915#3023]) +3 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([i915#8708])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][178] ([i915#1825]) +10 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][179] ([i915#15102] / [i915#3458])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html

  * igt@kms_hdr@bpc-switch:
    - shard-rkl:          NOTRUN -> [SKIP][180] ([i915#3555] / [i915#8228]) +1 other test skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_hdr@bpc-switch.html
    - shard-tglu:         NOTRUN -> [SKIP][181] ([i915#3555] / [i915#8228])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][182] ([i915#3555] / [i915#8228])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-rkl:          NOTRUN -> [SKIP][183] ([i915#12713])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-dg2:          [PASS][184] -> [SKIP][185] ([i915#3555] / [i915#8228]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg2-11/igt@kms_hdr@invalid-metadata-sizes.html
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-4/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_invalid_mode@bad-htotal:
    - shard-rkl:          [PASS][186] -> [SKIP][187] ([i915#14544] / [i915#3555] / [i915#8826]) +1 other test skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_invalid_mode@bad-htotal.html
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_invalid_mode@bad-htotal.html

  * igt@kms_panel_fitting@legacy:
    - shard-tglu-1:       NOTRUN -> [SKIP][188] ([i915#6301])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane@pixel-format-source-clamping:
    - shard-rkl:          [PASS][189] -> [SKIP][190] ([i915#14544] / [i915#8825])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_plane@pixel-format-source-clamping.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_plane@pixel-format-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b:
    - shard-dg2:          [PASS][191] -> [ABORT][192] ([i915#15132]) +1 other test abort
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg2-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-10/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html

  * igt@kms_plane_alpha_blend@alpha-basic:
    - shard-rkl:          [PASS][193] -> [SKIP][194] ([i915#14544] / [i915#7294]) +1 other test skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_plane_alpha_blend@alpha-basic.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_plane_alpha_blend@alpha-basic.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][195] ([i915#10647] / [i915#12169])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk5/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][196] ([i915#10647]) +1 other test fail
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk5/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_alpha_blend@constant-alpha-max:
    - shard-glk10:        NOTRUN -> [FAIL][197] ([i915#10647] / [i915#12169])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk10/igt@kms_plane_alpha_blend@constant-alpha-max.html

  * igt@kms_plane_alpha_blend@constant-alpha-max@pipe-a-hdmi-a-1:
    - shard-glk10:        NOTRUN -> [FAIL][198] ([i915#10647]) +1 other test fail
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk10/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-a-hdmi-a-1.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-tglu-1:       NOTRUN -> [SKIP][199] ([i915#13958])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][200] ([i915#13958])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers:
    - shard-rkl:          [PASS][201] -> [SKIP][202] ([i915#14544] / [i915#8152]) +1 other test skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-modifiers.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b:
    - shard-rkl:          NOTRUN -> [SKIP][203] ([i915#12247]) +3 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][204] ([i915#12247]) +9 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-c.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers:
    - shard-rkl:          [PASS][205] -> [SKIP][206] ([i915#14544] / [i915#3555] / [i915#8152])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a:
    - shard-rkl:          [PASS][207] -> [SKIP][208] ([i915#12247] / [i915#14544]) +5 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75:
    - shard-rkl:          [PASS][209] -> [SKIP][210] ([i915#12247] / [i915#14544] / [i915#3555] / [i915#6953] / [i915#8152])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5:
    - shard-rkl:          [PASS][211] -> [SKIP][212] ([i915#14544] / [i915#6953] / [i915#8152]) +1 other test skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b:
    - shard-rkl:          [PASS][213] -> [SKIP][214] ([i915#12247] / [i915#14544] / [i915#8152]) +5 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b.html

  * igt@kms_pm_backlight@fade:
    - shard-tglu-1:       NOTRUN -> [SKIP][215] ([i915#9812])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_pm_backlight@fade.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-glk:          NOTRUN -> [SKIP][216] +157 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk5/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-tglu-1:       NOTRUN -> [SKIP][217] ([i915#15073]) +1 other test skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@pm-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][218] ([i915#4077]) +1 other test skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_pm_rpm@pm-tiling.html

  * igt@kms_prime@basic-crc-vgem:
    - shard-rkl:          [PASS][219] -> [SKIP][220] ([i915#14544] / [i915#6524])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_prime@basic-crc-vgem.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_prime@basic-crc-vgem.html

  * igt@kms_properties@crtc-properties-atomic:
    - shard-rkl:          [PASS][221] -> [SKIP][222] ([i915#11521] / [i915#14544])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_properties@crtc-properties-atomic.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_properties@crtc-properties-atomic.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-rkl:          NOTRUN -> [SKIP][223] ([i915#11520]) +2 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-update-sf:
    - shard-tglu:         NOTRUN -> [SKIP][224] ([i915#11520]) +2 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_psr2_sf@pr-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb:
    - shard-glk:          NOTRUN -> [SKIP][225] ([i915#11520]) +4 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk5/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-glk10:        NOTRUN -> [SKIP][226] ([i915#11520]) +7 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk10/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-tglu-1:       NOTRUN -> [SKIP][227] ([i915#11520]) +3 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-tglu-1:       NOTRUN -> [SKIP][228] ([i915#9683])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-pr-sprite-render:
    - shard-tglu:         NOTRUN -> [SKIP][229] ([i915#9732]) +6 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_psr@fbc-pr-sprite-render.html

  * igt@kms_psr@pr-cursor-render:
    - shard-tglu-1:       NOTRUN -> [SKIP][230] ([i915#9732]) +8 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_psr@pr-cursor-render.html

  * igt@kms_psr@psr2-cursor-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][231] ([i915#1072] / [i915#9732]) +6 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_psr@psr2-cursor-mmap-gtt.html

  * igt@kms_psr@psr2-cursor-plane-move:
    - shard-dg2:          NOTRUN -> [SKIP][232] ([i915#1072] / [i915#9732])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_psr@psr2-cursor-plane-move.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-tglu-1:       NOTRUN -> [SKIP][233] ([i915#9685])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-glk10:        NOTRUN -> [ABORT][234] ([i915#13179]) +1 other test abort
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk10/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_sequence@get-busy@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][235] ([i915#12964])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_sequence@get-busy@pipe-a-hdmi-a-1.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-tglu-1:       NOTRUN -> [SKIP][236] ([i915#3555]) +1 other test skip
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2:          NOTRUN -> [SKIP][237] ([i915#8623])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][238] ([i915#12276]) +3 other tests incomplete
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk5/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2.html

  * igt@kms_vrr@max-min:
    - shard-tglu-1:       NOTRUN -> [SKIP][239] ([i915#9906])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-1/igt@kms_vrr@max-min.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-rkl:          NOTRUN -> [SKIP][240] ([i915#9906])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_vrr@seamless-rr-switch-drrs.html
    - shard-tglu:         NOTRUN -> [SKIP][241] ([i915#9906])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@perf_pmu@module-unload:
    - shard-rkl:          NOTRUN -> [FAIL][242] ([i915#14433])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@perf_pmu@module-unload.html
    - shard-tglu:         NOTRUN -> [FAIL][243] ([i915#14433])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@perf_pmu@module-unload.html

  * igt@prime_vgem@basic-fence-flip:
    - shard-rkl:          [PASS][244] -> [SKIP][245] ([i915#14544] / [i915#3708])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@prime_vgem@basic-fence-flip.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-read:
    - shard-rkl:          NOTRUN -> [SKIP][246] ([i915#3291] / [i915#3708])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@prime_vgem@basic-read.html

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - shard-tglu:         NOTRUN -> [FAIL][247] ([i915#12910]) +9 other tests fail
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-5/igt@sriov_basic@enable-vfs-autoprobe-on.html
    - shard-rkl:          NOTRUN -> [SKIP][248] ([i915#9917])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@sriov_basic@enable-vfs-autoprobe-on.html

  * igt@syncobj_wait@invalid-signal-zero-handles:
    - shard-rkl:          [PASS][249] -> [DMESG-WARN][250] ([i915#12964]) +6 other tests dmesg-warn
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@syncobj_wait@invalid-signal-zero-handles.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-7/igt@syncobj_wait@invalid-signal-zero-handles.html

  
#### Possible fixes ####

  * igt@gem_ccs@suspend-resume:
    - shard-dg2:          [INCOMPLETE][251] ([i915#13356]) -> [PASS][252]
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg2-5/igt@gem_ccs@suspend-resume.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@gem_ccs@suspend-resume.html

  * igt@gem_ccs@suspend-resume@tile64-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          [INCOMPLETE][253] ([i915#12392]) -> [PASS][254]
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg2-5/igt@gem_ccs@suspend-resume@tile64-compressed-compfmt0-smem-lmem0.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-8/igt@gem_ccs@suspend-resume@tile64-compressed-compfmt0-smem-lmem0.html

  * igt@gem_exec_balancer@sliced:
    - shard-rkl:          [DMESG-WARN][255] ([i915#12917] / [i915#12964]) -> [PASS][256]
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@gem_exec_balancer@sliced.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_exec_balancer@sliced.html

  * igt@gem_pxp@verify-pxp-stale-buf-execution:
    - shard-rkl:          [TIMEOUT][257] ([i915#12917] / [i915#12964]) -> [PASS][258] +1 other test pass
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_pxp@verify-pxp-stale-buf-execution.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@gem_pxp@verify-pxp-stale-buf-execution.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-rkl:          [ABORT][259] ([i915#15131]) -> [PASS][260]
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-4/igt@gem_workarounds@suspend-resume-context.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@gem_workarounds@suspend-resume-context.html

  * igt@i915_module_load@reload-no-display:
    - shard-snb:          [DMESG-WARN][261] ([i915#14545]) -> [PASS][262]
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-snb5/igt@i915_module_load@reload-no-display.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-snb1/igt@i915_module_load@reload-no-display.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-rkl:          [INCOMPLETE][263] ([i915#13356]) -> [PASS][264]
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@i915_pm_rpm@system-suspend-execbuf.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [SKIP][265] ([i915#7984]) -> [PASS][266]
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-mtlp-6/igt@i915_power@sanity.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-mtlp-6/igt@i915_power@sanity.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-dg1:          [FAIL][267] ([i915#14888]) -> [PASS][268] +1 other test pass
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg1-14/igt@kms_async_flips@alternate-sync-async-flip.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg1-17/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1:
    - shard-mtlp:         [FAIL][269] ([i915#5956]) -> [PASS][270] +1 other test pass
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-mtlp-4/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-mtlp-2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@pipe-a-edp-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [FAIL][271] ([i915#5138]) -> [PASS][272] +2 other tests pass
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_color@legacy-gamma-reset:
    - shard-rkl:          [SKIP][273] ([i915#12655] / [i915#14544]) -> [PASS][274]
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_color@legacy-gamma-reset.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_color@legacy-gamma-reset.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
    - shard-rkl:          [SKIP][275] ([i915#11190] / [i915#14544]) -> [PASS][276] +1 other test pass
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-rkl:          [FAIL][277] ([i915#2346]) -> [PASS][278] +1 other test pass
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-dg2:          [ABORT][279] ([i915#15066]) -> [PASS][280]
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg2-4/igt@kms_fbcon_fbt@fbc-suspend.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-4/igt@kms_fbcon_fbt@fbc-suspend.html
    - shard-rkl:          [SKIP][281] ([i915#14544] / [i915#14561]) -> [PASS][282]
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_fbcon_fbt@fbc-suspend.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-rkl:          [SKIP][283] ([i915#14544] / [i915#3637]) -> [PASS][284] +10 other tests pass
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_flip@flip-vs-suspend.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@plain-flip-ts-check:
    - shard-tglu:         [FAIL][285] ([i915#14600]) -> [PASS][286] +1 other test pass
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-tglu-2/igt@kms_flip@plain-flip-ts-check.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-9/igt@kms_flip@plain-flip-ts-check.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-rkl:          [SKIP][287] ([i915#14544] / [i915#3555]) -> [PASS][288] +4 other tests pass
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-rkl:          [SKIP][289] ([i915#14544] / [i915#1849] / [i915#5354]) -> [PASS][290] +7 other tests pass
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_invalid_mode@bad-hsync-end:
    - shard-rkl:          [SKIP][291] ([i915#14544] / [i915#3555] / [i915#8826]) -> [PASS][292] +3 other tests pass
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_invalid_mode@bad-hsync-end.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_invalid_mode@bad-hsync-end.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a:
    - shard-rkl:          [INCOMPLETE][293] ([i915#14412]) -> [PASS][294] +1 other test pass
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-rkl:          [SKIP][295] ([i915#14544] / [i915#7294]) -> [PASS][296]
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_plane_alpha_blend@alpha-opaque-fb.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_scaling@invalid-num-scalers:
    - shard-rkl:          [SKIP][297] ([i915#14544] / [i915#3555] / [i915#6953] / [i915#8152]) -> [PASS][298]
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_plane_scaling@invalid-num-scalers.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_plane_scaling@invalid-num-scalers.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format@pipe-a:
    - shard-rkl:          [SKIP][299] ([i915#12247] / [i915#14544]) -> [PASS][300] +3 other tests pass
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format@pipe-a.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format@pipe-a.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-pixel-format:
    - shard-rkl:          [SKIP][301] ([i915#14544] / [i915#8152]) -> [PASS][302] +1 other test pass
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-20x20-with-pixel-format.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_plane_scaling@plane-upscale-20x20-with-pixel-format.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75:
    - shard-rkl:          [SKIP][303] ([i915#12247] / [i915#14544] / [i915#6953] / [i915#8152]) -> [PASS][304]
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b:
    - shard-rkl:          [SKIP][305] ([i915#12247] / [i915#14544] / [i915#8152]) -> [PASS][306] +4 other tests pass
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html

  * igt@kms_pm_dc@dc5-dpms-negative:
    - shard-rkl:          [SKIP][307] ([i915#13441] / [i915#14544]) -> [PASS][308]
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_pm_dc@dc5-dpms-negative.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_pm_dc@dc5-dpms-negative.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [SKIP][309] ([i915#15073]) -> [PASS][310]
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-rkl:          [SKIP][311] ([i915#14544]) -> [PASS][312] +38 other tests pass
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_rotation_crc@primary-rotation-90.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@perf@gen12-group-concurrent-oa-buffer-read:
    - shard-rkl:          [FAIL][313] ([i915#10538]) -> [PASS][314]
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-5/igt@perf@gen12-group-concurrent-oa-buffer-read.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@perf@gen12-group-concurrent-oa-buffer-read.html
    - shard-tglu:         [FAIL][315] ([i915#10538]) -> [PASS][316]
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-tglu-2/igt@perf@gen12-group-concurrent-oa-buffer-read.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-2/igt@perf@gen12-group-concurrent-oa-buffer-read.html

  * igt@perf_pmu@most-busy-idle-check-all:
    - shard-rkl:          [FAIL][317] ([i915#4349]) -> [PASS][318] +1 other test pass
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-4/igt@perf_pmu@most-busy-idle-check-all.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@perf_pmu@most-busy-idle-check-all.html

  * igt@syncobj_timeline@invalid-query-zero-handles:
    - shard-rkl:          [DMESG-WARN][319] ([i915#12964]) -> [PASS][320] +11 other tests pass
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@syncobj_timeline@invalid-query-zero-handles.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@syncobj_timeline@invalid-query-zero-handles.html

  
#### Warnings ####

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-rkl:          [SKIP][321] ([i915#14544] / [i915#3555] / [i915#9323]) -> [SKIP][322] ([i915#3555] / [i915#9323])
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_ccs@ctrl-surf-copy.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          [SKIP][323] ([i915#13008]) -> [SKIP][324] ([i915#13008] / [i915#14544])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@gem_ccs@large-ctrl-surf-copy.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-rkl:          [SKIP][325] ([i915#14544] / [i915#6335]) -> [SKIP][326] ([i915#6335])
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_create@create-ext-cpu-access-sanity-check.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_create@create-ext-set-pat:
    - shard-rkl:          [SKIP][327] ([i915#14544] / [i915#8562]) -> [SKIP][328] ([i915#8562])
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_create@create-ext-set-pat.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-rkl:          [SKIP][329] ([i915#14544] / [i915#280]) -> [SKIP][330] ([i915#280]) +1 other test skip
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_ctx_sseu@invalid-sseu.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_exec_balancer@parallel:
    - shard-rkl:          [SKIP][331] ([i915#4525]) -> [SKIP][332] ([i915#14544] / [i915#4525]) +1 other test skip
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@gem_exec_balancer@parallel.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-rkl:          [SKIP][333] ([i915#14544] / [i915#4525]) -> [SKIP][334] ([i915#4525])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_exec_balancer@parallel-out-fence.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-rkl:          [SKIP][335] ([i915#6334]) -> [SKIP][336] ([i915#14544] / [i915#6334]) +1 other test skip
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@gem_exec_capture@capture-invisible@smem0.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - shard-rkl:          [SKIP][337] ([i915#3281]) -> [SKIP][338] ([i915#14544] / [i915#3281]) +6 other tests skip
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@gem_exec_reloc@basic-write-read-active.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - shard-rkl:          [SKIP][339] ([i915#14544] / [i915#3281]) -> [SKIP][340] ([i915#3281]) +8 other tests skip
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_exec_reloc@basic-write-read-noreloc.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_huc_copy@huc-copy:
    - shard-rkl:          [SKIP][341] ([i915#2190]) -> [SKIP][342] ([i915#14544] / [i915#2190])
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@gem_huc_copy@huc-copy.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-rkl:          [SKIP][343] ([i915#14544] / [i915#4613]) -> [SKIP][344] ([i915#4613]) +2 other tests skip
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-rkl:          [SKIP][345] ([i915#4613]) -> [SKIP][346] ([i915#14544] / [i915#4613]) +4 other tests skip
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-rkl:          [SKIP][347] ([i915#14544] / [i915#3282]) -> [SKIP][348] ([i915#3282]) +2 other tests skip
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_partial_pwrite_pread@reads-uncached.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_pxp@create-valid-protected-context:
    - shard-rkl:          [TIMEOUT][349] ([i915#12964]) -> [SKIP][350] ([i915#14544] / [i915#4270])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@gem_pxp@create-valid-protected-context.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_pxp@create-valid-protected-context.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-rkl:          [SKIP][351] ([i915#13717]) -> [TIMEOUT][352] ([i915#12917] / [i915#12964])
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@gem_pxp@hw-rejects-pxp-context.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
    - shard-rkl:          [TIMEOUT][353] ([i915#12917] / [i915#12964]) -> [SKIP][354] ([i915#4270])
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - shard-rkl:          [TIMEOUT][355] ([i915#12917] / [i915#12964]) -> [SKIP][356] ([i915#14544] / [i915#4270])
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@gem_pxp@reject-modify-context-protection-off-1.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_pxp@reject-modify-context-protection-off-1.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-rkl:          [SKIP][357] ([i915#14544] / [i915#8411]) -> [SKIP][358] ([i915#8411])
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_set_tiling_vs_pwrite:
    - shard-rkl:          [SKIP][359] ([i915#3282]) -> [SKIP][360] ([i915#14544] / [i915#3282]) +4 other tests skip
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@gem_set_tiling_vs_pwrite.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-rkl:          [SKIP][361] ([i915#3297]) -> [SKIP][362] ([i915#14544] / [i915#3297])
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@gem_userptr_blits@dmabuf-unsync.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@forbidden-operations:
    - shard-rkl:          [SKIP][363] ([i915#14544] / [i915#3282] / [i915#3297]) -> [SKIP][364] ([i915#3282] / [i915#3297])
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_userptr_blits@forbidden-operations.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@gem_userptr_blits@forbidden-operations.html

  * igt@gem_userptr_blits@relocations:
    - shard-rkl:          [SKIP][365] ([i915#3281] / [i915#3297]) -> [SKIP][366] ([i915#14544] / [i915#3281] / [i915#3297])
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@gem_userptr_blits@relocations.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gem_userptr_blits@relocations.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-rkl:          [SKIP][367] ([i915#14544] / [i915#3297]) -> [SKIP][368] ([i915#3297]) +2 other tests skip
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gem_userptr_blits@unsync-overlap.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-rkl:          [SKIP][369] ([i915#14544] / [i915#2527]) -> [SKIP][370] ([i915#2527]) +1 other test skip
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@gen9_exec_parse@bb-oversize.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-rkl:          [SKIP][371] ([i915#2527]) -> [SKIP][372] ([i915#14544] / [i915#2527]) +3 other tests skip
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@gen9_exec_parse@valid-registers.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_module_load@resize-bar:
    - shard-rkl:          [SKIP][373] ([i915#6412]) -> [SKIP][374] ([i915#14544] / [i915#6412])
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@i915_module_load@resize-bar.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-rkl:          [SKIP][375] ([i915#14498] / [i915#14544]) -> [SKIP][376] ([i915#14498])
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@i915_pm_rc6_residency@rc6-idle.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_query@hwconfig_table:
    - shard-rkl:          [SKIP][377] ([i915#14544] / [i915#6245]) -> [SKIP][378] ([i915#6245])
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@i915_query@hwconfig_table.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@i915_query@hwconfig_table.html

  * igt@intel_hwmon@hwmon-read:
    - shard-rkl:          [SKIP][379] ([i915#7707]) -> [SKIP][380] ([i915#14544] / [i915#7707])
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@intel_hwmon@hwmon-read.html
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-rkl:          [SKIP][381] ([i915#14544]) -> [SKIP][382] ([i915#9531])
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-rkl:          [SKIP][383] ([i915#14544]) -> [SKIP][384] ([i915#1769] / [i915#3555])
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-rkl:          [SKIP][385] ([i915#1769] / [i915#3555]) -> [SKIP][386] ([i915#14544])
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-rkl:          [SKIP][387] ([i915#5286]) -> [SKIP][388] ([i915#14544]) +5 other tests skip
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_big_fb@4-tiled-addfb.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          [SKIP][389] ([i915#14544]) -> [SKIP][390] ([i915#5286]) +4 other tests skip
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-rkl:          [SKIP][391] ([i915#14544]) -> [SKIP][392] ([i915#3638]) +2 other tests skip
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_big_fb@linear-32bpp-rotate-90.html
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-rkl:          [SKIP][393] ([i915#3638]) -> [SKIP][394] ([i915#14544]) +3 other tests skip
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][395] ([i915#14098] / [i915#6095]) -> [SKIP][396] ([i915#6095]) +1 other test skip
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-5/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][397] ([i915#14544]) -> [SKIP][398] ([i915#12313]) +1 other test skip
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs:
    - shard-dg1:          [SKIP][399] ([i915#6095]) -> [SKIP][400] ([i915#4423] / [i915#6095])
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg1-15/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs.html
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg1-12/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][401] ([i915#14544]) -> [SKIP][402] ([i915#12805])
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-rkl:          [SKIP][403] ([i915#14098] / [i915#6095]) -> [SKIP][404] ([i915#14544]) +16 other tests skip
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][405] ([i915#6095]) -> [SKIP][406] ([i915#14098] / [i915#6095]) +1 other test skip
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-b-hdmi-a-2.html
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-rkl:          [SKIP][407] ([i915#14544]) -> [SKIP][408] ([i915#14098] / [i915#6095]) +11 other tests skip
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-rkl:          [SKIP][409] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][410] ([i915#11151] / [i915#7828]) +7 other tests skip
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_chamelium_edid@hdmi-edid-read.html
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-rkl:          [SKIP][411] ([i915#11151] / [i915#7828]) -> [SKIP][412] ([i915#11151] / [i915#14544] / [i915#7828]) +5 other tests skip
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_chamelium_frames@dp-crc-fast.html
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
    - shard-dg1:          [SKIP][413] ([i915#11151] / [i915#7828]) -> [SKIP][414] ([i915#11151] / [i915#4423] / [i915#7828])
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg1-14/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg1-17/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          [SKIP][415] ([i915#7118] / [i915#9424]) -> [SKIP][416] ([i915#14544])
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_content_protection@atomic-dpms.html
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-rkl:          [SKIP][417] ([i915#3116]) -> [SKIP][418] ([i915#14544]) +1 other test skip
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_content_protection@dp-mst-lic-type-1.html
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-rkl:          [SKIP][419] ([i915#14544]) -> [SKIP][420] ([i915#3116])
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_content_protection@dp-mst-type-0.html
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-rkl:          [SKIP][421] ([i915#13049]) -> [SKIP][422] ([i915#14544]) +1 other test skip
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_cursor_crc@cursor-offscreen-512x512.html
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-128x42:
    - shard-rkl:          [SKIP][423] ([i915#14544]) -> [FAIL][424] ([i915#13566]) +1 other test fail
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_cursor_crc@cursor-random-128x42.html
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_cursor_crc@cursor-random-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-128x42:
    - shard-rkl:          [FAIL][425] ([i915#13566]) -> [SKIP][426] ([i915#14544]) +1 other test skip
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-128x42.html
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-128x42.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-rkl:          [SKIP][427] ([i915#4103]) -> [SKIP][428] ([i915#11190] / [i915#14544])
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-rkl:          [SKIP][429] ([i915#14544]) -> [SKIP][430] ([i915#4103]) +1 other test skip
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
    - shard-rkl:          [SKIP][431] ([i915#14544]) -> [SKIP][432] +11 other tests skip
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-rkl:          [SKIP][433] -> [SKIP][434] ([i915#14544]) +14 other tests skip
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-rkl:          [SKIP][435] ([i915#9067]) -> [SKIP][436] ([i915#14544])
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          [SKIP][437] ([i915#3555] / [i915#3804]) -> [SKIP][438] ([i915#14544])
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-rkl:          [SKIP][439] ([i915#13749]) -> [SKIP][440] ([i915#14544])
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_dp_link_training@non-uhbr-mst.html
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-rkl:          [SKIP][441] ([i915#14544]) -> [SKIP][442] ([i915#13749])
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_dp_link_training@non-uhbr-sst.html
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          [SKIP][443] ([i915#13707]) -> [SKIP][444] ([i915#14544])
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          [SKIP][445] ([i915#14544]) -> [SKIP][446] ([i915#3555] / [i915#3840])
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_dsc@dsc-with-output-formats.html
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_feature_discovery@display-3x:
    - shard-rkl:          [SKIP][447] ([i915#1839]) -> [SKIP][448] ([i915#14544] / [i915#1839])
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_feature_discovery@display-3x.html
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@psr2:
    - shard-rkl:          [SKIP][449] ([i915#658]) -> [SKIP][450] ([i915#14544] / [i915#658])
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_feature_discovery@psr2.html
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-rkl:          [SKIP][451] ([i915#14544] / [i915#9934]) -> [SKIP][452] ([i915#9934]) +7 other tests skip
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-plain-flip:
    - shard-rkl:          [SKIP][453] ([i915#9934]) -> [SKIP][454] ([i915#14544] / [i915#9934]) +8 other tests skip
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_flip@2x-plain-flip.html
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-glk:          [INCOMPLETE][455] ([i915#12745] / [i915#4839] / [i915#6113]) -> [INCOMPLETE][456] ([i915#12745] / [i915#4839])
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-glk1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-glk6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-rkl:          [SKIP][457] ([i915#2672] / [i915#3555]) -> [SKIP][458] ([i915#14544] / [i915#3555]) +1 other test skip
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-rkl:          [SKIP][459] ([i915#14544] / [i915#3555]) -> [SKIP][460] ([i915#2672] / [i915#3555]) +2 other tests skip
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][461] ([i915#14544]) -> [SKIP][462] ([i915#15102]) +2 other tests skip
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render:
    - shard-rkl:          [SKIP][463] ([i915#15102]) -> [SKIP][464] ([i915#14544]) +2 other tests skip
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render.html
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt:
    - shard-rkl:          [SKIP][465] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][466]
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
    - shard-rkl:          [SKIP][467] ([i915#1825]) -> [SKIP][468] ([i915#14544] / [i915#1849] / [i915#5354]) +32 other tests skip
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][469] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][470] ([i915#1825]) +25 other tests skip
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
    - shard-dg2:          [SKIP][471] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][472] ([i915#15102] / [i915#3458]) +1 other test skip
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
   [472]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-rkl:          [SKIP][473] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][474] ([i915#15102] / [i915#3023]) +17 other tests skip
   [473]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
   [474]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
    - shard-rkl:          [SKIP][475] ([i915#15102] / [i915#3023]) -> [SKIP][476] ([i915#14544] / [i915#1849] / [i915#5354]) +15 other tests skip
   [475]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
   [476]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu:
    - shard-dg2:          [SKIP][477] ([i915#15102] / [i915#3458]) -> [SKIP][478] ([i915#10433] / [i915#15102] / [i915#3458]) +1 other test skip
   [477]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html
   [478]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-rkl:          [SKIP][479] ([i915#3555] / [i915#8228]) -> [SKIP][480] ([i915#14544]) +1 other test skip
   [479]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_hdr@invalid-metadata-sizes.html
   [480]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-rkl:          [SKIP][481] ([i915#10656]) -> [SKIP][482] ([i915#10656] / [i915#14544])
   [481]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_joiner@invalid-modeset-big-joiner.html
   [482]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          [SKIP][483] ([i915#6301]) -> [SKIP][484] ([i915#14544])
   [483]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_panel_fitting@legacy.html
   [484]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-rkl:          [SKIP][485] ([i915#14544]) -> [SKIP][486] ([i915#3555]) +3 other tests skip
   [485]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_plane_lowres@tiling-yf.html
   [486]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-rkl:          [SKIP][487] ([i915#13958]) -> [SKIP][488] ([i915#14544])
   [487]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_plane_multiple@2x-tiling-x.html
   [488]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@tiling-4:
    - shard-rkl:          [SKIP][489] ([i915#14544]) -> [SKIP][490] ([i915#14259])
   [489]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_plane_multiple@tiling-4.html
   [490]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_plane_multiple@tiling-4.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-rkl:          [SKIP][491] -> [SKIP][492] ([i915#14544] / [i915#8152])
   [491]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
   [492]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a:
    - shard-rkl:          [SKIP][493] ([i915#12247] / [i915#14544]) -> [SKIP][494] ([i915#12247])
   [493]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a.html
   [494]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b:
    - shard-rkl:          [SKIP][495] ([i915#12247] / [i915#14544] / [i915#8152]) -> [SKIP][496] ([i915#12247]) +1 other test skip
   [495]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b.html
   [496]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-rkl:          [SKIP][497] ([i915#5354]) -> [SKIP][498] ([i915#14544] / [i915#5354]) +1 other test skip
   [497]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_pm_backlight@bad-brightness.html
   [498]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          [SKIP][499] ([i915#14544] / [i915#5354]) -> [SKIP][500] ([i915#5354])
   [499]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_pm_backlight@basic-brightness.html
   [500]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-rkl:          [SKIP][501] ([i915#14544] / [i915#9685]) -> [SKIP][502] ([i915#9685]) +1 other test skip
   [501]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [502]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          [FAIL][503] ([i915#9295]) -> [SKIP][504] ([i915#3361])
   [503]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_pm_dc@dc6-dpms.html
   [504]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         [SKIP][505] ([i915#4281]) -> [SKIP][506] ([i915#15128])
   [505]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-tglu-9/igt@kms_pm_dc@dc9-dpms.html
   [506]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-tglu-6/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [DMESG-WARN][507] ([i915#12964]) -> [SKIP][508] ([i915#14544] / [i915#15073])
   [507]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_pm_rpm@dpms-lpsp.html
   [508]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@fences-dpms:
    - shard-rkl:          [DMESG-WARN][509] ([i915#12964]) -> [SKIP][510] ([i915#14544] / [i915#1849])
   [509]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_pm_rpm@fences-dpms.html
   [510]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_pm_rpm@fences-dpms.html

  * igt@kms_pm_rpm@i2c:
    - shard-rkl:          [SKIP][511] ([i915#14544]) -> [DMESG-WARN][512] ([i915#12964])
   [511]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_pm_rpm@i2c.html
   [512]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@kms_pm_rpm@i2c.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-rkl:          [SKIP][513] ([i915#15073]) -> [SKIP][514] ([i915#14544] / [i915#15073]) +1 other test skip
   [513]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [514]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-rkl:          [SKIP][515] ([i915#14544]) -> [ABORT][516] ([i915#15132])
   [515]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_pm_rpm@system-suspend-modeset.html
   [516]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@kms_prime@d3hot:
    - shard-rkl:          [SKIP][517] ([i915#14544] / [i915#6524]) -> [SKIP][518] ([i915#6524])
   [517]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_prime@d3hot.html
   [518]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area:
    - shard-dg1:          [SKIP][519] ([i915#11520]) -> [SKIP][520] ([i915#11520] / [i915#4423])
   [519]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-dg1-14/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html
   [520]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-dg1-17/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][521] ([i915#11520] / [i915#14544]) -> [SKIP][522] ([i915#11520]) +6 other tests skip
   [521]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
   [522]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-rkl:          [SKIP][523] ([i915#11520]) -> [SKIP][524] ([i915#11520] / [i915#14544]) +7 other tests skip
   [523]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
   [524]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-rkl:          [SKIP][525] ([i915#9683]) -> [SKIP][526] ([i915#14544] / [i915#9683]) +1 other test skip
   [525]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_psr2_su@page_flip-xrgb8888.html
   [526]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-rkl:          [SKIP][527] ([i915#1072] / [i915#9732]) -> [SKIP][528] ([i915#1072] / [i915#14544] / [i915#9732]) +17 other tests skip
   [527]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@kms_psr@fbc-psr2-sprite-render.html
   [528]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@psr-sprite-plane-move:
    - shard-rkl:          [SKIP][529] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][530] ([i915#1072] / [i915#9732]) +18 other tests skip
   [529]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_psr@psr-sprite-plane-move.html
   [530]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-5/igt@kms_psr@psr-sprite-plane-move.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-rkl:          [SKIP][531] ([i915#9685]) -> [SKIP][532] ([i915#14544] / [i915#9685]) +1 other test skip
   [531]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [532]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-rkl:          [SKIP][533] ([i915#5289]) -> [SKIP][534] ([i915#14544])
   [533]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
   [534]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-rkl:          [DMESG-WARN][535] ([i915#12964]) -> [SKIP][536] ([i915#14544])
   [535]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
   [536]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-rkl:          [SKIP][537] ([i915#3555]) -> [SKIP][538] ([i915#14544] / [i915#3555])
   [537]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-7/igt@kms_setmode@basic-clone-single-crtc.html
   [538]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_vblank@ts-continuation-dpms-rpm:
    - shard-rkl:          [DMESG-WARN][539] ([i915#12917] / [i915#12964]) -> [SKIP][540] ([i915#14544])
   [539]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_vblank@ts-continuation-dpms-rpm.html
   [540]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_vblank@ts-continuation-dpms-rpm.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-rkl:          [SKIP][541] ([i915#14544]) -> [SKIP][542] ([i915#9906])
   [541]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_vrr@flip-basic-fastset.html
   [542]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-4/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@flip-dpms:
    - shard-rkl:          [SKIP][543] ([i915#3555]) -> [SKIP][544] ([i915#14544]) +2 other tests skip
   [543]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_vrr@flip-dpms.html
   [544]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_vrr@flip-dpms.html

  * igt@kms_vrr@lobf:
    - shard-rkl:          [SKIP][545] ([i915#14544]) -> [SKIP][546] ([i915#11920])
   [545]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@kms_vrr@lobf.html
   [546]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-8/igt@kms_vrr@lobf.html

  * igt@kms_vrr@max-min:
    - shard-rkl:          [SKIP][547] ([i915#9906]) -> [SKIP][548] ([i915#14544])
   [547]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@kms_vrr@max-min.html
   [548]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@kms_vrr@max-min.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-rkl:          [SKIP][549] ([i915#2435]) -> [SKIP][550] ([i915#14544] / [i915#2435])
   [549]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-8/igt@perf@per-context-mode-unprivileged.html
   [550]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@perf@per-context-mode-unprivileged.html

  * igt@perf@unprivileged-single-ctx-counters:
    - shard-rkl:          [SKIP][551] ([i915#2433]) -> [SKIP][552] ([i915#14544] / [i915#2433])
   [551]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@perf@unprivileged-single-ctx-counters.html
   [552]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@perf@unprivileged-single-ctx-counters.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-rkl:          [SKIP][553] ([i915#14544] / [i915#8516]) -> [SKIP][554] ([i915#8516])
   [553]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@perf_pmu@rc6-all-gts.html
   [554]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_vgem@coherency-gtt:
    - shard-rkl:          [SKIP][555] ([i915#3708]) -> [SKIP][556] ([i915#14544] / [i915#3708])
   [555]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-2/igt@prime_vgem@coherency-gtt.html
   [556]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-6/igt@prime_vgem@coherency-gtt.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-rkl:          [SKIP][557] ([i915#14544] / [i915#3708]) -> [SKIP][558] ([i915#3708]) +1 other test skip
   [557]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17479/shard-rkl-6/igt@prime_vgem@fence-flip-hang.html
   [558]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/shard-rkl-2/igt@prime_vgem@fence-flip-hang.html

  
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10538
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10826
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11190
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11521]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11521
  [i915#11713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11713
  [i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12358]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12358
  [i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
  [i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12796]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12796
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
  [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13441]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13441
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14152
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14412
  [i915#14433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14433
  [i915#14498]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14498
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
  [i915#14553]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14553
  [i915#14561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14561
  [i915#14600]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14600
  [i915#14702]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14702
  [i915#14785]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14785
  [i915#14888]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14888
  [i915#15066]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15066
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15095
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15128]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15128
  [i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#15140]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15140
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
  [i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4391]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7294]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7294
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7882
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8152
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8825
  [i915#8826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8826
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_17479 -> Patchwork_155952v3

  CI-20190529: 20190529
  CI_DRM_17479: 0c721eb082329d9ba1ef257e3cdfa8109ae9de32 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8605: 8605
  Patchwork_155952v3: 0c721eb082329d9ba1ef257e3cdfa8109ae9de32 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v3/index.html

[-- Attachment #2: Type: text/html, Size: 175409 bytes --]

Re: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD

[Gustavo Sousa]

Quoting Gustavo Sousa (2025-11-03 14:17:51-03:00)
>This series adds initial support for Xe3p_LPD, Intel's display
>architecture with IP version 35.
>
>This series contains basic enabling patches and does not provide
>complete support for the display IP yet. More involved features, like
>the new PHY implementation and ALPM are implemented as separate patch
>series.
>
>Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>---
>Changes in v3:
>- Reshuffled patches so that most of the ones already containing a r-b
>  are placed at the start.
>- Dropped "drm/i915/xe3p_lpd: Wait for AUX channel power status", as a
>  similar patch was already applied from a patch series dedicated to LT
>  PHY
>  (https://lore.kernel.org/all/20251101032513.4171255-25-suraj.kandpal@intel.com/).
>- Dropped patches related to UINT16 plane formats, as they were
>  incomplete and were not specific to Xe3p_LPD.
>- Dropped FBC related patches, as Vinod is handling them as a separated
>  series
>  (https://lore.kernel.org/intel-gfx/20251027134001.325064-1-vinod.govindapillai@intel.com/)
>- Dropped "drm/i915/xe3p_lpd: PSR SU minimum lines is 4", since that
>  change is not valid according to Bspec.
>- Incorporated review feedback on the other patches. Please check the
>  changelog in the individual patches for details.
>- Link to v2: https://lore.kernel.org/r/20251021-xe3p_lpd-basic-enabling-v2-0-10eae6d655b8@intel.com
>
>Changes in v2:
>- Incorporated review feedback. Please check the changelog in the
>  patches for details.
>- Link to v1: https://lore.kernel.org/r/20251015-xe3p_lpd-basic-enabling-v1-0-d2d1e26520aa@intel.com
>
>---
>Ankit Nautiyal (1):
>      drm/i915/xe3p_lpd: Drop support for interlace mode
>
>Gustavo Sousa (16):
>      drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()
>      drm/i915/xe3p_lpd: Add CDCLK table
>      drm/i915/xe3p_lpd: Load DMC firmware
>      drm/i915/xe3p_lpd: Extend Wa_16025573575
>      drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D
>      drm/i915/dram: Add field ecc_impacting_de_bw
>      drm/i915/xe3p_lpd: Log FBC-related debug info for PIPE underrun
>      drm/i915/wm: Do not make latency values monotonic on Xe3 onward
>      drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency
>      drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc
>      drm/i915/power: Use intel_encoder_is_tc()
>      drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()
>      drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation
>      drm/i915/display: Use platform check in HAS_LT_PHY()
>      drm/i915/display: Move HAS_LT_PHY() to intel_display_device.h
>      drm/i915/display: Use HAS_LT_PHY() for LT PHY AUX power
>
>Juha-pekka Heikkila (1):
>      drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format
>
>Luca Coelho (1):
>      drm/i915/wm: don't use method1 in Xe3p_LPD onwards
>
>Matt Atwood (1):
>      drm/i915/xe3p_lpd: Update bandwidth parameters
>
>Matt Roper (1):
>      drm/i915/xe3p_lpd: Drop north display reset option programming
>
>Ravi Kumar Vodapalli (1):
>      drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers
>
>Sai Teja Pottumuttu (6):
>      drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features
>      drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields
>      drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces
>      drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks
>      drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints
>      drm/i915/nvls: Add NVL-S display support
>
>Vinod Govindapillai (1):
>      drm/i915/xe3p_lpd: Enable system caching for FBC
>

I pushed the following patches after verifying CI results via [1]:

  - drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features
  - drm/i915/xe3p_lpd: Drop north display reset option programming
  - drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()
  - drm/i915/xe3p_lpd: Update bandwidth parameters
  - drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields
  - drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces
  - drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks
  - drm/i915/xe3p_lpd: Add CDCLK table
  - drm/i915/xe3p_lpd: Load DMC firmware
  - drm/i915/xe3p_lpd: Drop support for interlace mode
  - drm/i915/xe3p_lpd: Extend Wa_16025573575
  - drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format
  - drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D
  - drm/i915/wm: don't use method1 in Xe3p_LPD onwards
  - drm/i915/dram: Add field ecc_impacting_de_bw
  - drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency
  - drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers

The v4 of this series will skip those.

[1] https://lore.kernel.org/all/20251105140651.71713-19-gustavo.sousa@intel.com/

--
Gustavo Sousa