From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F1CECCF9F8 for ; Mon, 3 Nov 2025 17:19:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B19110E205; Mon, 3 Nov 2025 17:19:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="YPnsk3/r"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id E6BA110E457; Mon, 3 Nov 2025 17:19:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1762190382; x=1793726382; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=oBexbJM+yIIE5WiCFUxZSfq+WUY8dvtAOEpyRS/Lq7I=; b=YPnsk3/rgbjTUfM8cGocWUihg0JuGMT4yWbHMR/C305Z9Prsh1o1pL/n dbX4YDrTKl4euZ8ETJveOjELE2Zqlf+z7PBuNEkt4xaUzke9paQ3+aGID nbRFU7jE2ZXZss3J9QZc6C7oMseuT6o2vAvZf2mY38INIwmcvSyr1MHwB +6XskKV6fn9bzJKqiPoyq4WVr/0ML5vXmrgfLZgP8hN/UarRjoWfH+a43 jx8xcrXDqmFQdxaFQ24EhkfQQnSA9DzM/4ewrsJKZuJaKc3o6V2MgV/vz aWglWGJrQAK4f8ti+3ljfXqMLIFXbsvjCfb7CA+P2u4VbEwqjSM4HOpAK g==; X-CSE-ConnectionGUID: 5M4qGtWUSDiKVRqmiCo0TA== X-CSE-MsgGUID: JUQP1PD6SrS+5NM3dplYYw== X-IronPort-AV: E=McAfee;i="6800,10657,11602"; a="64309961" X-IronPort-AV: E=Sophos;i="6.19,276,1754982000"; d="scan'208";a="64309961" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2025 09:19:41 -0800 X-CSE-ConnectionGUID: RtQF2az/T2eXi6k5Amqq5w== X-CSE-MsgGUID: j8j2X7gwS/CSOA8I0VI0Wg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,276,1754982000"; d="scan'208";a="186606210" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO [192.168.1.16]) ([10.124.220.223]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2025 09:19:38 -0800 From: Gustavo Sousa Date: Mon, 03 Nov 2025 14:17:53 -0300 Subject: [PATCH v3 02/29] drm/i915/xe3p_lpd: Drop north display reset option programming MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251103-xe3p_lpd-basic-enabling-v3-2-00e87b510ae7@intel.com> References: <20251103-xe3p_lpd-basic-enabling-v3-0-00e87b510ae7@intel.com> In-Reply-To: <20251103-xe3p_lpd-basic-enabling-v3-0-00e87b510ae7@intel.com> To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal , Dnyaneshwar Bhadane , Gustavo Sousa , =?utf-8?q?Jouni_H=C3=B6gander?= , Juha-pekka Heikkila , Luca Coelho , Lucas De Marchi , Matt Atwood , Matt Roper , Ravi Kumar Vodapalli , Shekhar Chauhan , Vinod Govindapillai X-Mailer: b4 0.15-dev X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper The NDE_RSTWRN_OPT has been removed on Xe3p platforms and reset option programming is no longer necessary during display init. Bspec: 68846, 69137 Signed-off-by: Matt Roper Reviewed-by: Matt Atwood Signed-off-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index fbfa823b6dce..74fcd9cfe911 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1438,6 +1438,9 @@ static void intel_pch_reset_handshake(struct intel_display *display, i915_reg_t reg; u32 reset_bits; + if (DISPLAY_VER(display) >= 35) + return; + if (display->platform.ivybridge) { reg = GEN7_MSG_CTL; reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK; -- 2.51.0