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From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org,
	mitulkumar.ajitkumar.golani@intel.com,
	ankit.k.nautiyal@intel.com, uma.shankar@intel.com,
	ville.syrjala@linux.intel.com
Subject: [RESEND, 09/22] drm/i915/vrr: Increment DC balance flip count on every flip
Date: Mon,  3 Nov 2025 10:59:49 +0530	[thread overview]
Message-ID: <20251103053002.3002695-10-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20251103053002.3002695-1-mitulkumar.ajitkumar.golani@intel.com>

Increment DC Balance Flip count before every send push to indicate
DMC firmware about new flip occurrence. This is tracked separately
from legacy FLIP_COUNT register.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c   |  1 +
 drivers/gpu/drm/i915/display/intel_display.c |  1 +
 drivers/gpu/drm/i915/display/intel_vrr.c     | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h     |  3 +++
 4 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 1e97020e7304..47a732ae2448 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -2012,6 +2012,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
 	display->funcs.color->load_luts(crtc_state);
 
 	if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) {
+		intel_vrr_dcb_increment_flip_count(crtc_state, crtc);
 		intel_vrr_send_push(crtc_state->dsb_color, crtc_state);
 		intel_dsb_wait_for_delayed_vblank(state, crtc_state->dsb_color);
 		intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a00625f882e8..1a3e7a6e4ab7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7366,6 +7366,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) {
 		intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1);
 
+		intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
 		intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
 		intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit);
 		intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 2948abc90c69..87bd722aa32d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -14,6 +14,7 @@
 #include "intel_psr.h"
 #include "intel_vrr.h"
 #include "intel_vrr_regs.h"
+#include "intel_dmc_regs.h"
 #include "skl_prefill.h"
 #include "skl_watermark.h"
 
@@ -612,6 +613,20 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
 }
 
+void
+intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
+				   struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum pipe pipe = crtc->pipe;
+
+	if (!crtc_state->vrr.dc_balance.enable)
+		return;
+
+	intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe),
+		       ++crtc->dc_balance.flip_count);
+}
+
 void intel_vrr_send_push(struct intel_dsb *dsb,
 			 const struct intel_crtc_state *crtc_state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 66fb9ad846f2..eebc7be309db 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -14,6 +14,7 @@ struct intel_connector;
 struct intel_crtc_state;
 struct intel_dsb;
 struct intel_display;
+struct intel_crtc;
 
 bool intel_vrr_is_capable(struct intel_connector *connector);
 bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh);
@@ -39,6 +40,8 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
+void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
+					struct intel_crtc *crtc);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
-- 
2.48.1


  parent reply	other threads:[~2025-11-03  5:30 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-03  5:29 [RESEND, 00/22] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-11-03  5:29 ` [RESEND, 01/22] drm/i915/display: Add source param for dc balance Mitul Golani
2025-11-03  5:29 ` [RESEND, 02/22] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-11-05  4:15   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 03/22] drm/i915/vrr: Add VRR DC balance registers Mitul Golani
2025-11-03  9:59   ` Jani Nikula
2025-11-05  4:19   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 04/22] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-11-03  5:29 ` [RESEND, 05/22] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-11-05  4:24   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 06/22] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-11-05  4:25   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 07/22] drm/i915/vrr: Add compute config " Mitul Golani
2025-11-05  4:27   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 08/22] drm/i915/display: Add DC Balance flip counter in crtc Mitul Golani
2025-11-05  4:28   ` Nautiyal, Ankit K
2025-11-03  5:29 ` Mitul Golani [this message]
2025-11-03 10:01   ` [RESEND, 09/22] drm/i915/vrr: Increment DC balance flip count on every flip Jani Nikula
2025-11-05  4:51   ` Nautiyal, Ankit K
2025-11-05  6:15   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 10/22] drm/i915/vrr: Add function to reset DC Balance flip count Mitul Golani
2025-11-05  4:52   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 11/22] drm/i915/vrr: Add function reset DC balance accumulated params Mitul Golani
2025-11-05  4:54   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 12/22] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-11-05  4:56   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 13/22] drm/i915/vrr: Configure DC balance flipline adjustment Mitul Golani
2025-11-05  4:57   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 14/22] drm/i915/vblank: Extract vrr_vblank_start() Mitul Golani
2025-11-03  5:29 ` [RESEND, 15/22] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-11-03  5:29 ` [RESEND, 16/22] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
2025-11-05  5:59   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 17/22] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-11-03 10:02   ` Jani Nikula
2025-11-03  5:29 ` [RESEND, 18/22] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-11-03  5:29 ` [RESEND, 19/22] drm/i915/display: Add function to configure event for dc balance Mitul Golani
2025-11-05  6:18   ` Nautiyal, Ankit K
2025-11-03  5:30 ` [RESEND, 20/22] drm/i915/vrr: Enable Adaptive sync counter bit Mitul Golani
2025-11-05  6:02   ` Nautiyal, Ankit K
2025-11-03  5:30 ` [RESEND, 21/22] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-11-03  5:30 ` [RESEND, 22/22] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-11-05  6:04   ` Nautiyal, Ankit K
2025-11-03  6:05 ` ✗ Fi.CI.BUILD: failure for Enable/Disable DC balance along with VRR DSB Patchwork

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