From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org,
mitulkumar.ajitkumar.golani@intel.com,
ankit.k.nautiyal@intel.com, uma.shankar@intel.com,
ville.syrjala@linux.intel.com
Subject: [RESEND, 15/22] drm/i915/vrr: Implement vblank evasion with DC balancing
Date: Mon, 3 Nov 2025 10:59:55 +0530 [thread overview]
Message-ID: <20251103053002.3002695-16-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20251103053002.3002695-1-mitulkumar.ajitkumar.golani@intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add vblank evasion logic when vrr is already enabled along with
dc balance is computed.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 31 ++++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_vblank.c | 26 +++++++++++++++--
2 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 4ad4efbf9253..83130bb74aa9 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -704,7 +704,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
if (crtc_state->has_psr)
intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
- if (pre_commit_is_vrr_active(state, crtc)) {
+ if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
+ int vblank_delay = crtc_state->set_context_latency;
+ int vmin_vblank_start, vmax_vblank_start;
+
+ vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+
+ if (vmin_vblank_start >= 0) {
+ end = vmin_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ }
+
+ vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+ if (vmax_vblank_start >= 0) {
+ end = vmax_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ }
+
+ vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+ end = vmin_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+
+ vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+ end = vmax_vblank_start;
+ start = end - vblank_delay - latency;
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+ } else if (pre_commit_is_vrr_active(state, crtc)) {
int vblank_delay = crtc_state->set_context_latency;
end = intel_vrr_vmin_vblank_start(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index de20baeb9d99..df5879489963 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -654,10 +654,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
{
- if (intel_vrr_is_push_sent(crtc_state))
- return intel_vrr_vmin_vblank_start(crtc_state);
+ bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
+ int vblank_start;
+
+ if (!crtc_state->vrr.dc_balance.enable) {
+ if (is_push_sent)
+ return intel_vrr_vmin_vblank_start(crtc_state);
+ else
+ return intel_vrr_vmax_vblank_start(crtc_state);
+ }
+
+ if (is_push_sent)
+ vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
else
- return intel_vrr_vmax_vblank_start(crtc_state);
+ vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+ if (vblank_start >= 0)
+ return vblank_start;
+
+ if (is_push_sent)
+ vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+ else
+ vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+
+ return vblank_start;
}
void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
--
2.48.1
next prev parent reply other threads:[~2025-11-03 5:30 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 5:29 [RESEND, 00/22] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-11-03 5:29 ` [RESEND, 01/22] drm/i915/display: Add source param for dc balance Mitul Golani
2025-11-03 5:29 ` [RESEND, 02/22] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-11-05 4:15 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 03/22] drm/i915/vrr: Add VRR DC balance registers Mitul Golani
2025-11-03 9:59 ` Jani Nikula
2025-11-05 4:19 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 04/22] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-11-03 5:29 ` [RESEND, 05/22] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-11-05 4:24 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 06/22] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-11-05 4:25 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 07/22] drm/i915/vrr: Add compute config " Mitul Golani
2025-11-05 4:27 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 08/22] drm/i915/display: Add DC Balance flip counter in crtc Mitul Golani
2025-11-05 4:28 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 09/22] drm/i915/vrr: Increment DC balance flip count on every flip Mitul Golani
2025-11-03 10:01 ` Jani Nikula
2025-11-05 4:51 ` Nautiyal, Ankit K
2025-11-05 6:15 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 10/22] drm/i915/vrr: Add function to reset DC Balance flip count Mitul Golani
2025-11-05 4:52 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 11/22] drm/i915/vrr: Add function reset DC balance accumulated params Mitul Golani
2025-11-05 4:54 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 12/22] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-11-05 4:56 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 13/22] drm/i915/vrr: Configure DC balance flipline adjustment Mitul Golani
2025-11-05 4:57 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 14/22] drm/i915/vblank: Extract vrr_vblank_start() Mitul Golani
2025-11-03 5:29 ` Mitul Golani [this message]
2025-11-03 5:29 ` [RESEND, 16/22] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
2025-11-05 5:59 ` Nautiyal, Ankit K
2025-11-03 5:29 ` [RESEND, 17/22] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-11-03 10:02 ` Jani Nikula
2025-11-03 5:29 ` [RESEND, 18/22] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-11-03 5:29 ` [RESEND, 19/22] drm/i915/display: Add function to configure event for dc balance Mitul Golani
2025-11-05 6:18 ` Nautiyal, Ankit K
2025-11-03 5:30 ` [RESEND, 20/22] drm/i915/vrr: Enable Adaptive sync counter bit Mitul Golani
2025-11-05 6:02 ` Nautiyal, Ankit K
2025-11-03 5:30 ` [RESEND, 21/22] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-11-03 5:30 ` [RESEND, 22/22] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-11-05 6:04 ` Nautiyal, Ankit K
2025-11-03 6:05 ` ✗ Fi.CI.BUILD: failure for Enable/Disable DC balance along with VRR DSB Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251103053002.3002695-16-mitulkumar.ajitkumar.golani@intel.com \
--to=mitulkumar.ajitkumar.golani@intel.com \
--cc=ankit.k.nautiyal@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=uma.shankar@intel.com \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).