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From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org,
	mitulkumar.ajitkumar.golani@intel.com,
	ankit.k.nautiyal@intel.com, uma.shankar@intel.com,
	ville.syrjala@linux.intel.com
Subject: [RESEND, 04/22] drm/i915/vrr: Add functions to read out vmin/vmax stuff
Date: Mon,  3 Nov 2025 10:59:44 +0530	[thread overview]
Message-ID: <20251103053002.3002695-5-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20251103053002.3002695-1-mitulkumar.ajitkumar.golani@intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.

--v2:
- Correct Author details.

--v3:
- Separate register details from this  patch.

--v4:
- Add mask macros.

--v5:
- As live prefix params indicate timings for current frame,
read just _live prefix values instead of next frame timings as
done previously.
- Squash Refactor vrr params patch.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 56 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  5 +++
 2 files changed, 61 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 00cbc126fb36..68dde96583c0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -261,6 +261,12 @@ static int intel_vrr_hw_value(const struct intel_crtc_state *crtc_state,
 		return value - crtc_state->set_context_latency;
 }
 
+static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
+				  int vmin_vmax)
+{
+	return intel_vrr_hw_value(crtc_state, vmin_vmax) - crtc_state->vrr.guardband;
+}
+
 /*
  * For fixed refresh rate mode Vmin, Vmax and Flipline all are set to
  * Vtotal value.
@@ -898,3 +904,53 @@ int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state)
 	return intel_vrr_vmin_vblank_start(crtc_state) -
 	       crtc_state->set_context_latency;
 }
+
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_ADJ_VMAX(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_FLIPLINE(tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp = 0;
+
+	tmp = intel_de_read(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index bc9044621635..66fb9ad846f2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -43,4 +43,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
 
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_VRR_H__ */
-- 
2.48.1


  parent reply	other threads:[~2025-11-03  5:30 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-03  5:29 [RESEND, 00/22] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-11-03  5:29 ` [RESEND, 01/22] drm/i915/display: Add source param for dc balance Mitul Golani
2025-11-03  5:29 ` [RESEND, 02/22] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-11-05  4:15   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 03/22] drm/i915/vrr: Add VRR DC balance registers Mitul Golani
2025-11-03  9:59   ` Jani Nikula
2025-11-05  4:19   ` Nautiyal, Ankit K
2025-11-03  5:29 ` Mitul Golani [this message]
2025-11-03  5:29 ` [RESEND, 05/22] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-11-05  4:24   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 06/22] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-11-05  4:25   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 07/22] drm/i915/vrr: Add compute config " Mitul Golani
2025-11-05  4:27   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 08/22] drm/i915/display: Add DC Balance flip counter in crtc Mitul Golani
2025-11-05  4:28   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 09/22] drm/i915/vrr: Increment DC balance flip count on every flip Mitul Golani
2025-11-03 10:01   ` Jani Nikula
2025-11-05  4:51   ` Nautiyal, Ankit K
2025-11-05  6:15   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 10/22] drm/i915/vrr: Add function to reset DC Balance flip count Mitul Golani
2025-11-05  4:52   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 11/22] drm/i915/vrr: Add function reset DC balance accumulated params Mitul Golani
2025-11-05  4:54   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 12/22] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-11-05  4:56   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 13/22] drm/i915/vrr: Configure DC balance flipline adjustment Mitul Golani
2025-11-05  4:57   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 14/22] drm/i915/vblank: Extract vrr_vblank_start() Mitul Golani
2025-11-03  5:29 ` [RESEND, 15/22] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-11-03  5:29 ` [RESEND, 16/22] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
2025-11-05  5:59   ` Nautiyal, Ankit K
2025-11-03  5:29 ` [RESEND, 17/22] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-11-03 10:02   ` Jani Nikula
2025-11-03  5:29 ` [RESEND, 18/22] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-11-03  5:29 ` [RESEND, 19/22] drm/i915/display: Add function to configure event for dc balance Mitul Golani
2025-11-05  6:18   ` Nautiyal, Ankit K
2025-11-03  5:30 ` [RESEND, 20/22] drm/i915/vrr: Enable Adaptive sync counter bit Mitul Golani
2025-11-05  6:02   ` Nautiyal, Ankit K
2025-11-03  5:30 ` [RESEND, 21/22] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-11-03  5:30 ` [RESEND, 22/22] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-11-05  6:04   ` Nautiyal, Ankit K
2025-11-03  6:05 ` ✗ Fi.CI.BUILD: failure for Enable/Disable DC balance along with VRR DSB Patchwork

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