From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C9AFC88E64 for ; Mon, 26 Jan 2026 08:00:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A96CF10E3AE; Mon, 26 Jan 2026 08:00:44 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mJP21deg"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id E7A5810E3AC; Mon, 26 Jan 2026 08:00:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769414443; x=1800950443; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=U+CMUr4WBwXzkT7DERlsl/hYT+TNmE3og55EcFUYgEI=; b=mJP21deg1SXNtagq8/FkHToKAIjgCctxZMeaPiOZa4WxIQyA+Z5WvKW8 nFOw5XgMurjY7576llz4IPMeyu8ENneQ2OEeSCoFw0mwOFbTPR/+CY4PE 1u6EaWGBgmpWYA8KDlDsguIGxaLeoAZkgeio5CPYJoZ11gT+Oh/Vy4bhK QtP0l9Ya/uZYgHB/n9i0z55kZ2U8qjyx03pR85giRw2uCcvfnOuibSVZi 7Z6xNOc2nvmfQiPo6++gOx3CGfKzsXqZiNleekZZAVVjXA9rZxrtCPQ58 qJuwBzmhTGo39GEPWcJTMT0AbvpMTJWhVy+3TpobDClpZSREnRrbA654R g==; X-CSE-ConnectionGUID: vxSuhTB9TnexvBMDt9Tiog== X-CSE-MsgGUID: KaR7anJjS7aFzaFUprK3gg== X-IronPort-AV: E=McAfee;i="6800,10657,11682"; a="70682856" X-IronPort-AV: E=Sophos;i="6.21,254,1763452800"; d="scan'208";a="70682856" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2026 00:00:43 -0800 X-CSE-ConnectionGUID: agUx2+5gQgCEkZ9zvZwLsA== X-CSE-MsgGUID: JsgdWeMZTV6UI7dsPb7OmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,254,1763452800"; d="scan'208";a="207867689" Received: from krybak-mobl1.ger.corp.intel.com (HELO jhogande-mobl3.intel.com) ([10.245.246.56]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jan 2026 00:00:41 -0800 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= Subject: [PATCH v10 06/10] drm/i915/display: Wait for vblank in case of PSR is using trans push Date: Mon, 26 Jan 2026 09:59:55 +0200 Message-ID: <20260126075959.925413-7-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260126075959.925413-1-jouni.hogander@intel.com> References: <20260126075959.925413-1-jouni.hogander@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In case PSR uses trans push as a "frame change" event and we need to wait vblank after triggering PSR "frame change" event. Otherwise we may miss selective updates. DSB skips all waits while PSR is active. Check push send is skipped as well because trans push send bit is not clearn by the HW if VRR is not enabled -> we may start configuring new selective update while previous is not complete. Avoid this by waiting for vblank after sending trans push. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_display.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7491e00e3858..b47c9d3d0d85 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7390,9 +7390,27 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, new_crtc_state->dsb_color); if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) { - intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); + /* + * Dsb wait vblank may or may not skip. Let's remove it for PSR + * trans push case to ensure we are not waiting two vblanks + */ + if (!intel_psr_use_trans_push(new_crtc_state)) + intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); + + /* + * In case PSR uses trans push as a "frame change" event and + * VRR is not in use we need to wait vblank. Othervise we may + * miss selective updates. DSB skips all waits while PSR is + * active. Check push send is skipped as well because trans push + * send bit is not clearn by the HW if VRR is not enabled -> we + * may start configuring new selective update while previous is + * not complete. + */ + if (intel_psr_use_trans_push(new_crtc_state)) + intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); + intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit); intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state); -- 2.43.0