[PATCH 002/108] drm/i915/dp: Clamp max lane count to max common lane count

Imre Deak
2026-04-28T12:52:56Z

Clamp the maximum lane count after sink capability updates, matching
the earlier max link rate clamping done when updating common rates.

This prepares for detecting supported link capability changes in one
place in follow-up changes.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c6a961d02a4bc..cb81a9864d8c4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4856,9 +4856,15 @@ intel_dp_has_sink_count(struct intel_dp *intel_dp)

void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
{
+ int current_max_common_lane_count;
+
intel_dp_set_sink_rates(intel_dp);
intel_dp_set_max_sink_lane_count(intel_dp);
intel_dp_set_common_rates(intel_dp);
+
+ current_max_common_lane_count = intel_dp_max_common_lane_count(intel_dp);
+ intel_dp->link.max_lane_count = min(intel_dp->link.max_lane_count,
+ current_max_common_lane_count);
}

static bool
--
2.49.1