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This removes an unnecessary indirection, makes the max_limits query uniform across modeset, mode validation, TBT BW calculation and link state checking, and allows unexporting the intel_dp_max_link_rate()/intel_dp_max_lane_count() helpers. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++---- drivers/gpu/drm/i915/display/intel_dp.h | 2 -- drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 ++++++++++++++++---- 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9be3b767fb54c..875e835848c39 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -352,7 +352,7 @@ static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) return min3(source_max, sink_max, lane_max); } -int intel_dp_max_lane_count(struct intel_dp *intel_dp) +static int intel_dp_max_lane_count(struct intel_dp *intel_dp) { struct intel_dp_link_caps *link_caps = intel_dp->link.caps; struct intel_dp_link_config max_link_limits; @@ -1322,6 +1322,7 @@ intel_dp_mode_valid_format(struct intel_connector *connector, struct intel_dp *intel_dp = intel_attached_dp(connector); enum intel_output_format output_format; int max_rate, mode_rate, max_lanes, max_link_clock; + struct intel_dp_link_config max_link_limits; u16 dsc_max_compressed_bpp = 0; enum drm_mode_status status; bool dsc = false; @@ -1334,8 +1335,13 @@ intel_dp_mode_valid_format(struct intel_connector *connector, output_format = intel_dp_output_format(connector, sink_format); - max_link_clock = intel_dp_max_link_rate(intel_dp); - max_lanes = intel_dp_max_lane_count(intel_dp); + /* + * TODO: Compute BW from the maximum-BW configuration; max limits are + * independent bounds over all configs and may not form a valid config. + */ + intel_dp_link_caps_get_max_limits(intel_dp->link.caps, &max_link_limits); + max_link_clock = max_link_limits.rate; + max_lanes = max_link_limits.lane_count; max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); @@ -1539,7 +1545,7 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp) drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s)); } -int +static int intel_dp_max_link_rate(struct intel_dp *intel_dp) { struct intel_dp_link_caps *link_caps = intel_dp->link.caps; diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 6abce846b8e7e..6d6bb9e23ff26 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -99,8 +99,6 @@ void intel_dp_mst_suspend(struct intel_display *display); void intel_dp_mst_resume(struct intel_display *display); int intel_dp_rate_limit_len(const int *rates, int len, int max_rate); int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port); -int intel_dp_max_link_rate(struct intel_dp *intel_dp); -int intel_dp_max_lane_count(struct intel_dp *intel_dp); int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); int intel_dp_rate_index(const int *rates, int len, int rate); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 832a43ebe00f7..4736bfeb25e06 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -47,6 +47,7 @@ #include "intel_display_wa.h" #include "intel_dp.h" #include "intel_dp_hdcp.h" +#include "intel_dp_link_caps.h" #include "intel_dp_link_training.h" #include "intel_dp_mst.h" #include "intel_dp_test.h" @@ -1473,6 +1474,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, unsigned long bw_overhead_flags = DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK; int min_link_bpp_x16 = fxp_q4_from_int(18); + struct intel_dp_link_config max_link_limits; static bool supports_dsc; int ret; bool dsc = false; @@ -1505,8 +1507,13 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, min_link_bpp_x16 = intel_dp_compute_min_compressed_bpp_x16(connector, INTEL_OUTPUT_FORMAT_RGB); - max_link_clock = intel_dp_max_link_rate(intel_dp); - max_lanes = intel_dp_max_lane_count(intel_dp); + /* + * TODO: Compute BW from the maximum-BW configuration; max limits are + * independent bounds over all configs and may not form a valid config. + */ + intel_dp_link_caps_get_max_limits(intel_dp->link.caps, &max_link_limits); + max_link_clock = max_link_limits.rate; + max_lanes = max_link_limits.lane_count; max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); @@ -2132,14 +2139,19 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state, */ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp) { - int link_rate = intel_dp_max_link_rate(intel_dp); - int lane_count = intel_dp_max_lane_count(intel_dp); + struct intel_dp_link_config max_link_limits; + int link_rate; + int lane_count; u8 rate_select; u8 link_bw; if (intel_dp->link.active) return; + intel_dp_link_caps_get_max_limits(intel_dp->link.caps, &max_link_limits); + link_rate = max_link_limits.rate; + lane_count = max_link_limits.lane_count; + if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count)) return; -- 2.49.1