From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17F50CD37BE for ; Mon, 11 May 2026 21:41:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AD1DB10E8E0; Mon, 11 May 2026 21:41:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="H1cR1Wek"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 300DE10E8E0; Mon, 11 May 2026 21:41:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778535711; x=1810071711; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ugkyY10UWLSfjQxLpg7TiOy5dhP4DfXOnZotqoPsfT0=; b=H1cR1Wek7/tIFqLnAR4Rfdt2TltFTlWhQEKMR5fog0/Wxm3xM7M4VaD/ YVjQejle8tjLXI3WZ3wuT7vPsDdiPg3iv0bIbj9vHX4IYoZEP7Ky8QrRo Rv5gGFeO7R5YFZr8jaMrTaZCRrjILoPhLiu/4ENChadBoW3mTPssLDCGr kxMYlrqhB8iOp85bw2jtDktpUeW8PAaAgkCJmHT02U77+nQruIQWqNVPD flHt1FzrCFO8UuiABkspGX5A+Mr/NrkGbtMk8N/6/euuejJqGcFPNxMoI DBXVSXUdYckqT5ghnCRwKYW+b5SCcxhyjjZuJ6zRSRYq+rPYpfMyLHo6z A==; X-CSE-ConnectionGUID: nExNvHgDQuqMNKN6CVo0PA== X-CSE-MsgGUID: biNAsIFBTiqa4aHUCs4A7w== X-IronPort-AV: E=McAfee;i="6800,10657,11783"; a="79618496" X-IronPort-AV: E=Sophos;i="6.23,229,1770624000"; d="scan'208";a="79618496" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 14:41:51 -0700 X-CSE-ConnectionGUID: gS6uvOeURemtu1CHeqYeMA== X-CSE-MsgGUID: sPtL0pS2RxGUNZc+cBXgAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,229,1770624000"; d="scan'208";a="233097298" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.245.104]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2026 14:41:50 -0700 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 06/14] drm/xe: Do the initial FB size alignment earlier Date: Tue, 12 May 2026 00:41:14 +0300 Message-ID: <20260511214122.8468-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260511214122.8468-1-ville.syrjala@linux.intel.com> References: <20260511214122.8468-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland Content-Transfer-Encoding: 8bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä For some reason we've split the alignment of 'base' vs. 'size' to live on separate sides of the xe initial plane PTE readout. There's no reason for this split, so make things less confusing by aligning both at the same time. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/xe/display/xe_initial_plane.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_initial_plane.c b/drivers/gpu/drm/xe/display/xe_initial_plane.c index 37cfc8a55031..584ce82b2564 100644 --- a/drivers/gpu/drm/xe/display/xe_initial_plane.c +++ b/drivers/gpu/drm/xe/display/xe_initial_plane.c @@ -36,6 +36,10 @@ initial_plane_bo(struct xe_device *xe, flags = XE_BO_FLAG_FORCE_WC | XE_BO_FLAG_GGTT; base = round_down(plane_config->base, page_size); + size = round_up(plane_config->base + plane_config->size, + page_size); + size -= base; + if (IS_DGFX(xe)) { u64 pte = xe_ggtt_read_pte(tile0->mem.ggtt, base); @@ -71,10 +75,6 @@ initial_plane_bo(struct xe_device *xe, flags |= XE_BO_FLAG_STOLEN; } - size = round_up(plane_config->base + plane_config->size, - page_size); - size -= base; - bo = xe_bo_create_pin_map_at_novm(xe, tile0, size, phys_base, ttm_bo_type_kernel, flags, 0, false); if (IS_ERR(bo)) { -- 2.52.0