From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99295CD4F3C for ; Tue, 19 May 2026 05:14:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3912B10EA3D; Tue, 19 May 2026 05:14:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="FgpFnoTn"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id E609110EA39 for ; Tue, 19 May 2026 05:14:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1779167663; x=1810703663; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M9i76wPfoJPsPJ3mKpHTbICzBPWrdqj3EBjj8BWGbQI=; b=FgpFnoTnzWT2j6XBtI92m7/myPV8BCPOknA9G+GuLZp8Blgw2u3MLgD4 TG9OWNuVo6OvtrP4EdGXozmKs/XjZIBzju29z9JEH5//vR/YhqcK7r+Q9 YKr3W1hc2yBGh1hb8YnX6JBuP+JyrSOvBqrOly9RUVZ+QCYUw1H5TX17K ISxhgWJd0zf7Cx5xGRFVWeV5Vekfxi6WHEwOtaLC2xJhr5LL1XL9pR05x EMuqOnsT9cn4l9mHlv9/NI3wZrNEXXfbSWR+QDqPL/uAi6IFzWYBE368j cYRHG/BGN16WF9ViI2xOMFnV2gawta4K15h4T4fJGqwBMb8dpcUva5PhW g==; X-CSE-ConnectionGUID: SNg+F72iQfCsCDKuVG+3ww== X-CSE-MsgGUID: fmIWY6z7R52QB0i29Z0lHg== X-IronPort-AV: E=McAfee;i="6800,10657,11790"; a="97603538" X-IronPort-AV: E=Sophos;i="6.23,243,1770624000"; d="scan'208";a="97603538" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2026 22:14:23 -0700 X-CSE-ConnectionGUID: S1oHc7R5Q0iWvOfCf9rVnQ== X-CSE-MsgGUID: uqUFtKTHTnGP16O89yTdjQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,243,1770624000"; d="scan'208";a="243635798" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa003.jf.intel.com with ESMTP; 18 May 2026 22:14:21 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: mitulkumar.ajitkumar.golani@intel.com, ankit.k.nautiyal@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH v1 2/8] drm/i915/vrr: Move CMRR register writes to fix refresh rate path Date: Tue, 19 May 2026 10:33:16 +0530 Message-ID: <20260519050322.3677451-3-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20260519050322.3677451-1-mitulkumar.ajitkumar.golani@intel.com> References: <20260519050322.3677451-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Write CMRR related M/N registers to fix rate path for its better alignment as fix refresh rate use-case. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index a5bd87c2912a..87d52b206bdb 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -328,6 +328,17 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state) if (!intel_vrr_possible(crtc_state)) return; + if (crtc_state->vrr.cmrr.enable) { + intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), + upper_32_bits(crtc_state->vrr.cmrr.cmrr_m)); + intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), + lower_32_bits(crtc_state->vrr.cmrr.cmrr_m)); + intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), + upper_32_bits(crtc_state->vrr.cmrr.cmrr_n)); + intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), + lower_32_bits(crtc_state->vrr.cmrr.cmrr_n)); + } + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1); intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), @@ -636,17 +647,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) return; } - if (crtc_state->vrr.cmrr.enable) { - intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), - upper_32_bits(crtc_state->vrr.cmrr.cmrr_m)); - intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), - lower_32_bits(crtc_state->vrr.cmrr.cmrr_m)); - intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), - upper_32_bits(crtc_state->vrr.cmrr.cmrr_n)); - intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), - lower_32_bits(crtc_state->vrr.cmrr.cmrr_n)); - } - intel_vrr_set_fixed_rr_timings(crtc_state); if (!intel_vrr_always_use_vrr_tg(display)) -- 2.48.1