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d="scan'208";a="262108427" Received: from dut-2a59.iind.intel.com ([10.190.239.113]) by orviesa009.jf.intel.com with ESMTP; 04 Aug 2026 05:55:13 -0700 From: Chaitanya Kumar Borah To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Pranay Samala , Chaitanya Kumar Borah , Uma Shankar Subject: [v6 8/9] drm/i915/color: Program Plane Post CSC registers for SDR planes Date: Tue, 4 Aug 2026 18:01:06 +0530 Message-ID: <20260804123107.2256124-9-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260804123107.2256124-1-chaitanya.kumar.borah@intel.com> References: <20260804123107.2256124-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Pranay Samala Implement plane post-CSC LUT support for SDR planes. v2: - Restructure loop to match HDR function pattern Assisted-by: Claude:claude-opus-4.6 Signed-off-by: Pranay Samala Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 36c8688ed28e..f1df0f9ba762 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -4030,6 +4030,45 @@ xelpd_load_hdr_post_csc_lut(struct intel_display *display, intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); } +static void +xelpd_load_sdr_post_csc_lut(struct intel_display *display, + struct intel_dsb *dsb, + enum pipe pipe, + enum plane_id plane, + const struct drm_color_lut32 *post_csc_lut) +{ + int i, lut_size = 32; + u32 lut_val; + + /* + * First 3 planes are HDR, so reduce by 3 to get to the right + * SDR plane offset + */ + plane = plane - 3; + + intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX(pipe, plane, 0), + PLANE_PAL_PREC_AUTO_INCREMENT); + + for (i = 0; i < lut_size + 3; i++) { + if (post_csc_lut) { + if (i < lut_size) + lut_val = drm_color_lut32_extract(post_csc_lut[i].green, 16); + /* else duplicate last lut_val */ + } else { + if (i < lut_size) + lut_val = (i * ((1 << 16) - 1)) / (lut_size - 1); + else + lut_val = 1 << 16; + } + + intel_de_write_dsb(display, dsb, + PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), + lut_val); + } + + intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX(pipe, plane, 0), 0); +} + static void xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, const struct intel_plane_state *plane_state) @@ -4043,6 +4082,8 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, if (icl_is_hdr_plane(display, plane)) xelpd_load_hdr_post_csc_lut(display, dsb, pipe, plane, post_csc_lut); + else + xelpd_load_sdr_post_csc_lut(display, dsb, pipe, plane, post_csc_lut); } static void -- 2.50.1