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Fri, 3 Jun 2022 03:29:21 -0700 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Fri, 3 Jun 2022 03:29:20 -0700 Received: from fmsmsx612.amr.corp.intel.com ([10.18.126.92]) by fmsmsx612.amr.corp.intel.com ([10.18.126.92]) with mapi id 15.01.2308.027; Fri, 3 Jun 2022 03:29:20 -0700 From: "Manna, Animesh" To: "Nikula, Jani" , "intel-gfx@lists.freedesktop.org" Thread-Topic: [RFC PATCH 5/5] drm/i915/display/tgl+: Use PPS index from vbt Thread-Index: AQHYdovybfn4bUDfmU6Ozpf5+axAi608tDYAgAC7oyA= Date: Fri, 3 Jun 2022 10:29:20 +0000 Message-ID: <20b989211c3848868adbf339f6d80aa0@intel.com> References: <20220602141850.21301-1-animesh.manna@intel.com> <20220602141850.21301-6-animesh.manna@intel.com> <874k13ozcd.fsf@intel.com> In-Reply-To: <874k13ozcd.fsf@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.6.500.17 dlp-product: dlpe-windows dlp-reaction: no-action x-originating-ip: [10.223.10.1] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Intel-gfx] [RFC PATCH 5/5] drm/i915/display/tgl+: Use PPS index from vbt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Varide, Nischal" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Nikula, Jani > Sent: Thursday, June 2, 2022 9:03 PM > To: Manna, Animesh ; intel- > gfx@lists.freedesktop.org > Cc: ville.syrjala@linux.intel.com; Shankar, Uma ; > Varide, Nischal ; Manna, Animesh > > Subject: Re: [RFC PATCH 5/5] drm/i915/display/tgl+: Use PPS index from vb= t >=20 > On Thu, 02 Jun 2022, Animesh Manna wrote: > > From: Nischal Varide > > > > Tigerlake and newer has two instances of PPS, to support up to two eDP > > panels. > > > > Signed-off-by: Nischal Varide > > Signed-off-by: Animesh Manna > > --- > > drivers/gpu/drm/i915/display/intel_pps.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c > > b/drivers/gpu/drm/i915/display/intel_pps.c > > index 1b21a341962f..52cb5be4e901 100644 > > --- a/drivers/gpu/drm/i915/display/intel_pps.c > > +++ b/drivers/gpu/drm/i915/display/intel_pps.c > > @@ -365,7 +365,8 @@ static void intel_pps_get_registers(struct > > intel_dp *intel_dp, > > > > memset(regs, 0, sizeof(*regs)); > > > > - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > > + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || > > + DISPLAY_VER(dev_priv) >=3D 12) > > pps_idx =3D bxt_power_sequencer_idx(intel_dp); >=20 > There are two things that need to be checked, but I don't have the time r= ight > now: >=20 > - We'll probably need this *before* we've parsed the panel specific info > from VBT. Ville has looked into this somewhat with the PNPID panel > type stuff. Currently intel_pps_init() get called before intel_bios_init_panel() where = panel specific info in parsed from VBT. >=20 > - bxt_power_sequencer_idx() does pps_init_registers() which has always > struck me as a really odd place to do it. As if we don't know when the > first time we do it is, so we do it there just in case. Will try to check on this. Regards, Animesh=20 >=20 > BR, > Jani. >=20 >=20 >=20 > > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > pps_idx =3D vlv_power_sequencer_pipe(intel_dp); >=20 > -- > Jani Nikula, Intel Open Source Graphics Center