Re: [Intel-gfx] [PATCH v3 5/9] drm/i915/reg: add stream splitter configuration definitions

Jani Nikula
2021-02-22T16:31:39Z

On Mon, 22 Feb 2021, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani Nikula
>> Sent: Thursday, February 11, 2021 8:22 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Varide, Nischal <nischal.varide@intel.com>
>> Subject: [Intel-gfx] [PATCH v3 5/9] drm/i915/reg: add stream splitter configuration
>> definitions
>>
>> The splitter configuration is required for eDP MSO.
>
> Looks Good to me.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>

Thanks for the review, pushed up to and including this patch.

BR,
Jani.

>
>> Bspec: 50174
>> Cc: Nischal Varide <nischal.varide@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 224ad897af34..e5dd0203991b 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -11448,6 +11448,9 @@ enum skl_power_gate {
>> #define BIG_JOINER_ENABLE (1 << 29)
>> #define MASTER_BIG_JOINER_ENABLE (1 << 28)
>> #define VGA_CENTERING_ENABLE (1 << 27)
>> +#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
>> +#define SPLITTER_CONFIGURATION_2_SEGMENT
>> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>> +#define SPLITTER_CONFIGURATION_4_SEGMENT
>> REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
>>
>> #define _ICL_PIPE_DSS_CTL2_PB 0x78204
>> #define _ICL_PIPE_DSS_CTL2_PC 0x78404
>> --
>> 2.20.1
>>
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--
Jani Nikula, Intel Open Source Graphics Center