[Intel-gfx] [PATCH v3 0/9] drm/i915/edp: enable eDP Multi-SST Operation (MSO)

Jani Nikula
2021-02-11T14:52:31Z

This series enables eDP Multi-SST Operation (MSO) on TGL+.

MSO splits the full panel into 2 or 4 segments horizontally. The EDID contains
timings for one segment, and we'll need to use them for transcoder timings as
well as data M/N calculation. We shove the segment timings to
adjusted_mode->crtc_*. Otherwise, we'll need to use full panel timings.

There's a bunch of back and forth conversion to transparently present the full
mode to userspace. Not sure if there's a better way as different places require
conversion of different fields. Otherwise the splitter configuration is trivial.

The segments may include 0-8 pixels overlap. The overlap is defined in DisplayID
2.0 for which we don't have parsing. Hopefully we can insert the overlap in one
place if required, however this has not been tested as the panel at hand does
not use overlap.

BR,
Jani.

Jani Nikula (9):
drm/dp: add MSO related DPCD registers
drm/i915/edp: reject modes with dimensions other than fixed mode
drm/i915/edp: always add fixed mode to probed modes in ->get_modes()
drm/i915/edp: read sink MSO configuration for eDP 1.4+
drm/i915/reg: add stream splitter configuration definitions
drm/i915/mso: add splitter state readout for platforms that support it
drm/i915/mso: add splitter state check
drm/i915/edp: modify fixed and downclock modes for MSO
drm/i915/edp: enable eDP MSO during link training

drivers/gpu/drm/i915/display/intel_ddi.c | 74 ++++++++++++
drivers/gpu/drm/i915/display/intel_display.c | 48 +++++++-
.../drm/i915/display/intel_display_types.h | 9 ++
drivers/gpu/drm/i915/display/intel_dp.c | 112 ++++++++++++++++--
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 3 +
include/drm/drm_dp_helper.h | 5 +
7 files changed, 242 insertions(+), 11 deletions(-)

--
2.20.1