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d="scan'208";a="209927579" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.205]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2026 04:06:05 -0800 From: Jani Nikula To: Uma Shankar , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: ville.syrjala@linux.intel.com, Uma Shankar Subject: Re: [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c In-Reply-To: <20260129211358.1240283-7-uma.shankar@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland References: <20260129211358.1240283-1-uma.shankar@intel.com> <20260129211358.1240283-7-uma.shankar@intel.com> Date: Tue, 03 Feb 2026 14:06:02 +0200 Message-ID: <242e99f8cff36a711e74fa2abaca49af09c64255@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 30 Jan 2026, Uma Shankar wrote: > Move GU_CNTL_PROTECTED and GMD_ID_DISPLAY to common header, > this helps intel_display_device.c free from i915_reg.h dependency. > > v2: Move GMD_ID_DISPLAY to display header instead of common (Jani) > > Signed-off-by: Uma Shankar > --- > drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++---- > drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++ > drivers/gpu/drm/i915/i915_reg.h | 4 ---- > 3 files changed, 11 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c > index 471f236c9ddf..d449528bfc7f 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -10,7 +10,6 @@ > #include > #include > > -#include "i915_reg.h" > #include "intel_cx0_phy_regs.h" > #include "intel_de.h" > #include "intel_display.h" > @@ -1539,9 +1538,9 @@ probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver * > return NULL; > } > > - gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); > - gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); > - gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val); > + gmd_id.ver = REG_FIELD_GET(GMD_ID_DISPLAY_ARCH_MASK, val); > + gmd_id.rel = REG_FIELD_GET(GMD_ID_DISPLAY_RELEASE_MASK, val); > + gmd_id.step = REG_FIELD_GET(GMD_ID_DISPLAY_STEP, val); > > for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) { > if (gmd_id.ver == gmdid_display_map[i].ver && > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h > index f90d52f7e5be..0d7788db4a7f 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -6,6 +6,9 @@ > > #include "intel_display_reg_defs.h" > > +#define GU_CNTL_PROTECTED _MMIO(0x10100C) > +#define DEPRESENT REG_BIT(9) > + > #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 > #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 > #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) > @@ -1626,6 +1629,11 @@ > #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) > #define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3) > > +#define GMD_ID_DISPLAY _MMIO(0x510a0) > +#define GMD_ID_DISPLAY_ARCH_MASK REG_GENMASK(31, 22) > +#define GMD_ID_DISPLAY_RELEASE_MASK REG_GENMASK(21, 14) > +#define GMD_ID_DISPLAY_STEP REG_GENMASK(5, 0) > + > #define XE2LPD_DE_CAP _MMIO(0x41100) > #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30) > #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c7361e82a0c6..4341308c3b2b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -117,9 +117,6 @@ > * #define GEN8_BAR _MMIO(0xb888) > */ > > -#define GU_CNTL_PROTECTED _MMIO(0x10100C) > -#define DEPRESENT REG_BIT(9) > - > #define GU_CNTL _MMIO(0x101010) > #define LMEM_INIT REG_BIT(7) > #define DRIVERFLR REG_BIT(31) > @@ -926,7 +923,6 @@ > #define MASK_WAKEMEM REG_BIT(13) > #define DDI_CLOCK_REG_ACCESS REG_BIT(7) > > -#define GMD_ID_DISPLAY _MMIO(0x510a0) > #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) > #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) > #define GMD_ID_STEP REG_GENMASK(5, 0) I guess these could now go next to #define GMD_ID_GRAPHICS _MMIO(0xd8c) #define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE + 0xd8c) in gt/intel_gt_regs.h, but can be a follow-up too. Reviewed-by: Jani Nikula -- Jani Nikula, Intel