Hi Ankit,

Tested on the NVL platform using the AORUS FO32U2P panel and a BizLink (DP to HDMI2.1) dongle.

With your patches, I am now able to achieve 3840x2160 @ 240Hz, which was previously being

rejected with a CLOCK_HIGH error without the patches.

Tested-by: Swati Sharma <swati2.sharma@intel.com>

On 11-08-2026 10:12 am, Ankit Nautiyal wrote:

The PCON mode_valid path currently does not fully account for the bandwidth
limitations of the PCON <-> HDMI link. The DSC capability between the
PCON and the HDMI sink also needs to be taken into account, which currently
isn't. Furthermore, the compressed bpp chosen needs to fit the
FRL configuration, which is also missing.

This series:
 - reworks the HDMI DSC helpers so they can be reused across the
   mode_valid, compute_config and FRL bandwidth check paths
 - fixes the FRL/TMDS downstream bandwidth checks, and allows
   PCON DSC modes through the FRL check
 - Clamps the programmed DSC bpp to the FRL link bandwidth.

Rev2:
 - Rebase and address comments from Suraj.
 - Drop drm/i915/dp: Use FRL pair check for the DFP dotclock limit as no
   longer required.

Ankit Nautiyal (8):
  drm/i915/hdmi: Split the intel_hdmi_dsc_get_bpp()
  drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
  drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints
  drm/i915/dp: Use the common downstream bw check in compute_bpc
  drm/i915/hdmi: Expose DSC min/max bpp helpers
  drm/i915/hdmi: Add helper to check if DSC chunksize fits the sink
    limits
  drm/i915/dp: Allow PCON DSC modes through FRL bw check
  drm/i915/dp: Clamp PCON DSC bpp to the FRL link bandwidth

 drivers/gpu/drm/i915/display/intel_dp.c   | 144 ++++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_hdmi.c | 124 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_hdmi.h |   7 +-
 3 files changed, 218 insertions(+), 57 deletions(-)