From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: drop buggy write to FDI_RX_CHICKEN register Date: Thu, 15 Nov 2012 10:42:02 +0000 Message-ID: <275ffc$7dta74@fmsmga002.fm.intel.com> References: <1352911659-11757-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 634189EFCE for ; Thu, 15 Nov 2012 02:42:06 -0800 (PST) In-Reply-To: <1352911659-11757-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Jani Nikula , Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Wed, 14 Nov 2012 17:47:39 +0100, Daniel Vetter wrote: > Jani Nikula noticed that the parentheses are wrong and we & the bit > with the register address instead of the read-back value. He sent a > patch to correct that. > > On second look, we write the same register in the previous line, and > the w/a seems to be to set FDI_RX_PHASE_SYNC_POINTER_OVR to enable the > logic, then keep always set FDI_RX_PHASE_SYNC_POINTER_OVR and toggle > ~FDI_RX_PHASE_SYNC_POINTER_EN before/after enabling the pc transcoder. > > So the right things seems to be to simply kill the 2nd write. > > Cc: Jani Nikula > Signed-off-by: Daniel Vetter Looks sane(r). Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre