From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75A61C433FE for ; Thu, 26 May 2022 09:27:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B3A5C10EF25; Thu, 26 May 2022 09:27:38 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 796AE10F1AF for ; Thu, 26 May 2022 09:27:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653557257; x=1685093257; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=wVuOGmvUwTqzRIBaAjDx2KA+eTw7wSLKG7NPAn+b2lE=; b=RkHrGgFCp4GUPd4prsV9iur7lAAhOXT9Kw0Oo2zapGbg55rGOfQVhTqF 0nQdTqZZSuxGp5DrFtn91XW7guIwBVuHVaBHXGWLmw4KKGFzdqxCHvRBL +Ik7YvMYsyCz7cUoOsSsmnkQZdYNqCMFuIzj80IZ52VQHNvD5BmQExcI1 gP//sSy1HfcJkJhUnPfa5kANN9Ve+lT+VXjwTNlCyKt91SkDGwJ0agbNQ H/TlzXxMUaEX6e+Muk4Tw7MRLB8QdEZZC+33l2WeXk5tutklsYne4IspN 17hL4fEDN31kdGiMagZuGx4+7twdEmv7dluChSrleZXcfe1Ry0TJNAM2X g==; X-IronPort-AV: E=McAfee;i="6400,9594,10358"; a="254595894" X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="254595894" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2022 02:27:36 -0700 X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="664852653" Received: from tursulin-mobl.ger.corp.intel.com (HELO [10.252.4.248]) ([10.252.4.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2022 02:27:35 -0700 Message-ID: <2c138486-fa2e-867c-33ac-3e7837a8481a@intel.com> Date: Thu, 26 May 2022 10:27:33 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Firefox/91.0 Thunderbird/91.9.0 Content-Language: en-GB To: Nirmoy Das , intel-gfx@lists.freedesktop.org References: <20220525095955.15371-1-nirmoy.das@intel.com> From: Matthew Auld In-Reply-To: <20220525095955.15371-1-nirmoy.das@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Intel-gfx] [PATCH v6] drm/i915: Individualize fences before adding to dma_resv obj X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thomas.hellstrom@intel.com, chris.p.wilson@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 25/05/2022 10:59, Nirmoy Das wrote: > _i915_vma_move_to_active() can receive > 1 fences for > multiple batch buffers submission. Because dma_resv_add_fence() > can only accept one fence at a time, change _i915_vma_move_to_active() > to be aware of multiple fences so that it can add individual > fences to the dma resv object. > > v6: fix multi-line comment. > v5: remove double fence reservation for batch VMAs. > v4: Reserve fences for composite_fence on multi-batch contexts and > also reserve fence slots to composite_fence for each VMAs. > v3: dma_resv_reserve_fences is not cumulative so pass num_fences. > v2: make sure to reserve enough fence slots before adding. > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5614 > Signed-off-by: Nirmoy Das Reviewed-by: Matthew Auld Do we need Fixes: ? > --- > .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +- > drivers/gpu/drm/i915/i915_vma.c | 48 +++++++++++-------- > 2 files changed, 30 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > index b279588c0672..8880d38d36b6 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c > @@ -1010,7 +1010,8 @@ static int eb_validate_vmas(struct i915_execbuffer *eb) > } > } > > - err = dma_resv_reserve_fences(vma->obj->base.resv, 1); > + /* Reserve enough slots to accommodate composite fences */ > + err = dma_resv_reserve_fences(vma->obj->base.resv, eb->num_batches); > if (err) > return err; > > diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c > index 4f6db539571a..0bffb70b3c5f 100644 > --- a/drivers/gpu/drm/i915/i915_vma.c > +++ b/drivers/gpu/drm/i915/i915_vma.c > @@ -23,6 +23,7 @@ > */ > > #include > +#include > #include > > #include "display/intel_frontbuffer.h" > @@ -1823,6 +1824,21 @@ int _i915_vma_move_to_active(struct i915_vma *vma, > if (unlikely(err)) > return err; > > + /* > + * Reserve fences slot early to prevent an allocation after preparing > + * the workload and associating fences with dma_resv. > + */ > + if (fence && !(flags & __EXEC_OBJECT_NO_RESERVE)) { > + struct dma_fence *curr; > + int idx; > + > + dma_fence_array_for_each(curr, idx, fence) > + ; > + err = dma_resv_reserve_fences(vma->obj->base.resv, idx); > + if (unlikely(err)) > + return err; > + } > + > if (flags & EXEC_OBJECT_WRITE) { > struct intel_frontbuffer *front; > > @@ -1832,31 +1848,23 @@ int _i915_vma_move_to_active(struct i915_vma *vma, > i915_active_add_request(&front->write, rq); > intel_frontbuffer_put(front); > } > + } > > - if (!(flags & __EXEC_OBJECT_NO_RESERVE)) { > - err = dma_resv_reserve_fences(vma->obj->base.resv, 1); > - if (unlikely(err)) > - return err; > - } > + if (fence) { > + struct dma_fence *curr; > + enum dma_resv_usage usage; > + int idx; > > - if (fence) { > - dma_resv_add_fence(vma->obj->base.resv, fence, > - DMA_RESV_USAGE_WRITE); > + obj->read_domains = 0; > + if (flags & EXEC_OBJECT_WRITE) { > + usage = DMA_RESV_USAGE_WRITE; > obj->write_domain = I915_GEM_DOMAIN_RENDER; > - obj->read_domains = 0; > - } > - } else { > - if (!(flags & __EXEC_OBJECT_NO_RESERVE)) { > - err = dma_resv_reserve_fences(vma->obj->base.resv, 1); > - if (unlikely(err)) > - return err; > + } else { > + usage = DMA_RESV_USAGE_READ; > } > > - if (fence) { > - dma_resv_add_fence(vma->obj->base.resv, fence, > - DMA_RESV_USAGE_READ); > - obj->write_domain = 0; > - } > + dma_fence_array_for_each(curr, idx, fence) > + dma_resv_add_fence(vma->obj->base.resv, curr, usage); > } > > if (flags & EXEC_OBJECT_NEEDS_FENCE && vma->fence)