From mboxrd@z Thu Jan 1 00:00:00 1970 From: shuang.he@intel.com Subject: Re: [PATCH] drm/i915: Fix modeset state confusion in the load detect code Date: 04 Mar 2015 04:41:54 -0800 Message-ID: <2d8c1b$k3n84u@fmsmga001.fm.intel.com> References: <1425400281-1555-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 83B5E6E2E3 for ; Wed, 4 Mar 2015 04:41:56 -0800 (PST) In-Reply-To: <1425400281-1555-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: shuang.he@intel.com, ethan.gao@intel.com, intel-gfx@lists.freedesktop.org, daniel.vetter@ffwll.ch List-Id: intel-gfx@lists.freedesktop.org VGVzdGVkLUJ5OiBQUkMgUUEgUFJUUyAoUGF0Y2ggUmVncmVzc2lvbiBUZXN0IFN5c3RlbSBDb250 YWN0OiBzaHVhbmcuaGVAaW50ZWwuY29tKQpUYXNrIGlkOiA1ODc5Ci0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS1TdW1tYXJ5LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLQpQbGF0Zm9ybSAgICAgICAgICBEZWx0YSAgICAgICAgICBkcm0taW50ZWwtbmlnaHRs eSAgICAgICAgICBTZXJpZXMgQXBwbGllZApQTlYgICAgICAgICAgICAgICAgIC02ICAgICAgICAg ICAgICAyNzgvMjc4ICAgICAgICAgICAgICAyNzIvMjc4CklMSyAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAzMDgvMzA4ICAgICAgICAgICAgICAzMDgvMzA4ClNOQiAgICAgICAgICAg ICAgICAgLTEgICAgICAgICAgICAgIDI4NC8yODQgICAgICAgICAgICAgIDI4My8yODQKSVZCICAg ICAgICAgICAgICAgICAtMSAgICAgICAgICAgICAgMzgwLzM4MCAgICAgICAgICAgICAgMzc5LzM4 MApCWVQgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgMjk0LzI5NCAgICAgICAgICAg ICAgMjk0LzI5NApIU1cgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgMzg3LzM4NyAg ICAgICAgICAgICAgMzg3LzM4NwpCRFcgICAgICAgICAgICAgICAgIC0xICAgICAgICAgICAgICAz MTYvMzE2ICAgICAgICAgICAgICAzMTUvMzE2Ci0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS1EZXRhaWxlZC0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KUGxh dGZvcm0gIFRlc3QgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGRybS1pbnRlbC1uaWdo dGx5ICAgICAgICAgIFNlcmllcyBBcHBsaWVkCiBQTlYgIGlndF9nZW1fdXNlcnB0cl9ibGl0c19j b2hlcmVuY3ktc3luYyAgICAgIE5PX1JFU1VMVCgxKUNSQVNIKDgpTlJVTigxKVBBU1MoOCkgICAg ICBDUkFTSCgxKU5SVU4oMSkKIFBOViAgaWd0X2dlbV91c2VycHRyX2JsaXRzX2NvaGVyZW5jeS11 bnN5bmMgICAgICBGQUlMKDEpTk9fUkVTVUxUKDEpQ1JBU0goNilQQVNTKDcpICAgICAgQ1JBU0go MSlQQVNTKDEpCiBQTlYgIGlndF9nZW1fdXNlcnB0cl9ibGl0c19taW5vci11bnN5bmMtaW50ZXJy dXB0aWJsZSAgICAgIERNRVNHX1dBUk4oMSlQQVNTKDUpICAgICAgRE1FU0dfV0FSTigxKVBBU1Mo MSkKIFBOViAgaWd0X2dlbjNfcmVuZGVyX2xpbmVhcl9ibGl0cyAgICAgIEZBSUwoNilOUlVOKDEp RE1FU0dfV0FSTigxKVBBU1MoOSkgICAgICBGQUlMKDIpCiBQTlYgIGlndF9nZW4zX3JlbmRlcl9t aXhlZF9ibGl0cyAgICAgIEZBSUwoOSlQQVNTKDkpICAgICAgRkFJTCgyKQogUE5WICBpZ3RfZ2Vt X2ZlbmNlX3RocmFzaF9iby13cml0ZS12ZXJpZnktdGhyZWFkZWQtbm9uZSAgICAgIEZBSUwoMilD UkFTSCg0KVBBU1MoNykgICAgICBDUkFTSCgyKQoqU05CICBpZ3RfZ2VtX2ZlbmNlX3RocmFzaF9i by13cml0ZS12ZXJpZnkteSAgICAgIFBBU1MoNSkgICAgICBETUVTR19XQVJOKDEpUEFTUygxKQoq SVZCICBpZ3RfZ2VtX3N0b3JlZHdfYmF0Y2hlc19sb29wX3NlY3VyZS1kaXNwYXRjaCAgICAgIFBB U1MoMykgICAgICBETUVTR19XQVJOKDEpUEFTUygxKQoqQkRXICBpZ3RfZ2VtX2d0dF9ob2cgICAg ICBQQVNTKDE5KSAgICAgIERNRVNHX1dBUk4oMSlQQVNTKDEpCk5vdGU6IFlvdSBuZWVkIHRvIHBh eSBtb3JlIGF0dGVudGlvbiB0byBsaW5lIHN0YXJ0IHdpdGggJyonCl9fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50 ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3Jn L21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg==