From mboxrd@z Thu Jan 1 00:00:00 1970 From: shuang.he@intel.com Subject: Re: [PATCH 2/2] drm/i915: move clearing of RPS interrupt bits from disable to reset time Date: 24 Mar 2015 13:39:52 -0700 Message-ID: <2d8c1b$kd9b5m@fmsmga001.fm.intel.com> References: <1427130695-5705-2-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 35EDC6E76E for ; Tue, 24 Mar 2015 13:39:53 -0700 (PDT) In-Reply-To: <1427130695-5705-2-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: shuang.he@intel.com, ethan.gao@intel.com, intel-gfx@lists.freedesktop.org, imre.deak@intel.com List-Id: intel-gfx@lists.freedesktop.org VGVzdGVkLUJ5OiBQUkMgUUEgUFJUUyAoUGF0Y2ggUmVncmVzc2lvbiBUZXN0IFN5c3RlbSBDb250 YWN0OiBzaHVhbmcuaGVAaW50ZWwuY29tKQpUYXNrIGlkOiA2MDMwCi0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS1TdW1tYXJ5LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLQpQbGF0Zm9ybSAgICAgICAgICBEZWx0YSAgICAgICAgICBkcm0taW50ZWwtbmlnaHRs eSAgICAgICAgICBTZXJpZXMgQXBwbGllZApQTlYgICAgICAgICAgICAgICAgIC0xICAgICAgICAg ICAgICAyNzUvMjc1ICAgICAgICAgICAgICAyNzQvMjc1CklMSyAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAzMDMvMzAzICAgICAgICAgICAgICAzMDMvMzAzClNOQiAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAzMDQvMzA0ICAgICAgICAgICAgICAzMDQvMzA0CklWQiAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAzMzkvMzM5ICAgICAgICAgICAgICAzMzkv MzM5CkJZVCAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAyODcvMjg3ICAgICAgICAg ICAgICAyODcvMjg3CkhTVyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAzNjEvMzYx ICAgICAgICAgICAgICAzNjEvMzYxCkJEVyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAzMTAvMzEwICAgICAgICAgICAgICAzMTAvMzEwCi0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS1EZXRhaWxlZC0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0K UGxhdGZvcm0gIFRlc3QgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGRybS1pbnRlbC1u aWdodGx5ICAgICAgICAgIFNlcmllcyBBcHBsaWVkCipQTlYgIGlndEBnZW1fdXNlcnB0cl9ibGl0 c0BtaW5vci1zeW5jLWludGVycnVwdGlibGUgICAgICBQQVNTKDIpICAgICAgRE1FU0dfV0FSTigx KVBBU1MoMSkKTm90ZTogWW91IG5lZWQgdG8gcGF5IG1vcmUgYXR0ZW50aW9uIHRvIGxpbmUgc3Rh cnQgd2l0aCAnKicKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK