Re: [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

Kumar, Mahesh
2018-02-08T08:42:53Z

Hi,

On 2/8/2018 2:01 PM, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 2/6/2018 6:28 PM, Vidya Srinivas wrote:
>> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>>
>> Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
>> Hardware sometimes fails to wake memory from pkg C states fetching the
>> last few lines of planar YUV 420 (NV12) planes. This causes
>> intermittent underflow and corruption.
>> WA: Disable package C states or do not enable latency levels 1 through 7
>> (WM1 - WM7) on NV12 planes.
>>
>> v2: Addressed review comments by Maarten.
>>
>> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index d9801bf..c37d014 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -4654,6 +4654,17 @@ static int skl_compute_plane_wm(const struct
>> drm_i915_private *dev_priv,
>>           }
>>       }
>>   +    /*
>> +     * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
>> +     * disable wm level 1-7 on NV12 planes
>> +     */
>> +    if (wp->is_nv12 && (level >= 1) &&
>> +        (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
>> +         IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
> Seeing that this WAR is applicable for all GEN9 and CNL some rev ids,
> Is this applicable for GLK too ?
Not really for all GEN-9, it's valid for SKL/BXT-ALL & CNL some id, so
it doesn't seems to be applicable for GLK.

-Mahesh
> - Shashank
>> +        result->plane_en = false;
>> +        return 0;
>> +    }
>> +
>>       result->plane_res_b = res_blocks;
>>       result->plane_res_l = res_lines;
>>       result->plane_en = true;