Re: [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

Sharma, Shashank
2018-02-07T16:22:07Z

Regards

Shashank

On 2/6/2018 6:28 PM, Vidya Srinivas wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> NV12 formats have two registers for DDB. Verify both the registers for
> NV12 during verify_wm_state.
The commit message can add a little more details about how we are
planning to program. You can pick the direct line from Bspec definition
about how the UV buffer allocation should happen and how the Y buffer
allocation.
>
> v2: Addressed review comments by Maarten.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 50 ++++++++++++++++++++++++++++--------
> 3 files changed, 42 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e3a6a7f..5fc9255 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2621,7 +2621,7 @@ static int i9xx_format_to_fourcc(int format)
> }
> }
>
> -static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> +int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> {
> switch (format) {
> case PLANE_CTL_FORMAT_RGB_565:
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 35ee715..ed33840 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1595,6 +1595,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
> int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state);
> int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> +int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
>
> /* intel_csr.c */
> void intel_csr_ucode_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5bff004..4c9a811 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3828,6 +3828,43 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
> entry->end += 1;
> }
>
> +static void
> +skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> + const enum pipe pipe,
> + const enum plane_id plane_id,
> + struct skl_ddb_allocation *ddb /* out */)
Is it me, or each of the input variables need one more space for
alignment ?
> +{
> + u32 val, val2 = 0;
> + int fourcc, pixel_format;
> +
> + /* Cursor doesn't support NV12, so no extra calculation needed */
> + if (plane_id == PLANE_CURSOR) {
> + val = I915_READ(CUR_BUF_CFG(pipe));
> + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> + return;
> + }
> +
> + val = I915_READ(PLANE_CTL(pipe, plane_id));
> +
> + /* No DDB allocated for disabled planes */
> + if (!(val & PLANE_CTL_ENABLE))
> + return;
> +
> + pixel_format = val & PLANE_CTL_FORMAT_MASK;
> + fourcc = skl_format_to_fourcc(pixel_format,
> + val & PLANE_CTL_ORDER_RGBX,
> + val & PLANE_CTL_ALPHA_MASK);
> +
> + val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> + val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
> +
> + if (fourcc == DRM_FORMAT_NV12) {
> + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
> + skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
> + } else
please continue the curly brace for else case too
- Shashank
> + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> +}
> +
> void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> struct skl_ddb_allocation *ddb /* out */)
> {
> @@ -3844,16 +3881,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> continue;
>
> - for_each_plane_id_on_crtc(crtc, plane_id) {
> - u32 val;
> -
> - if (plane_id != PLANE_CURSOR)
> - val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> - else
> - val = I915_READ(CUR_BUF_CFG(pipe));
> -
> - skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> - }
> + for_each_plane_id_on_crtc(crtc, plane_id)
> + skl_ddb_get_hw_plane_state(dev_priv, pipe,
> + plane_id, ddb);
>
> intel_display_power_put(dev_priv, power_domain);
> }