* [Intel-gfx] [PATCH v2 2/6] drm/i915/display/psr: Use plane damage clips to calculate damaged area
2020-10-27 23:45 [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers José Roberto de Souza
@ 2020-10-27 23:45 ` José Roberto de Souza
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/display/psr: Consider other planes to damaged area calculation José Roberto de Souza
` (6 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2020-10-27 23:45 UTC (permalink / raw)
To: intel-gfx
Now using plane damage clips property to calcualte the damaged area.
Selective fetch only supports one region to be fetched so software
needs to calculate a bounding box around all damage clips.
v2:
- do not shifthing new_plane_state->uapi.dst only src is in 16.16 format
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 54 +++++++++++++++++++++---
1 file changed, 49 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 6dead51d7a81..1c3330e096c7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1287,6 +1287,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
new_plane_state, i) {
struct drm_rect *sel_fetch_area, temp;
+ struct drm_mode_rect *damaged_clips;
+ u32 num_clips;
+ int j;
if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
continue;
@@ -1305,13 +1308,54 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
if (!new_plane_state->uapi.visible)
continue;
+ sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
+ sel_fetch_area->y1 = -1;
+
+ damaged_clips = drm_plane_get_damage_clips(&new_plane_state->uapi);
+ num_clips = drm_plane_get_damage_clips_count(&new_plane_state->uapi);
+
/*
- * For now doing a selective fetch in the whole plane area,
- * optimizations will come in the future.
+ * If plane moved, mark the whole plane area as damaged as it
+ * needs to be complete redraw in the new position.
*/
- sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
- sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16;
- sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >> 16;
+ if (!drm_rect_equals(&new_plane_state->uapi.dst,
+ &old_plane_state->uapi.dst)) {
+ num_clips = 0;
+ sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16;
+ sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >> 16;
+ } else if (!num_clips && new_plane_state->uapi.fb !=
+ old_plane_state->uapi.fb) {
+ /*
+ * If the plane don't have damage areas but the
+ * framebuffer changed, mark the whole plane area as
+ * damaged.
+ */
+ sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >> 16;
+ sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >> 16;
+ }
+
+ for (j = 0; j < num_clips; j++) {
+ struct drm_rect damage_area;
+
+ damage_area.y1 = damaged_clips[j].y1;
+ damage_area.y2 = damaged_clips[j].y2;
+ clip_area_update(sel_fetch_area, &damage_area);
+ }
+
+ /*
+ * No page flip, no plane movement or no damage areas, so don't
+ * fetch any pixel from memory for this plane
+ */
+ if (sel_fetch_area->y1 == -1) {
+ sel_fetch_area->y1 = 0;
+ sel_fetch_area->y2 = 0;
+ }
+
+ /* Don't need to redraw plane damaged areas outside of screen */
+ j = sel_fetch_area->y2 + new_plane_state->uapi.dst.y1;
+ j = crtc_state->uapi.adjusted_mode.crtc_vdisplay - j;
+ if (j < 0)
+ sel_fetch_area->y2 += j;
temp = *sel_fetch_area;
temp.y1 += new_plane_state->uapi.dst.y1;
--
2.29.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH v2 3/6] drm/i915/display/psr: Consider other planes to damaged area calculation
2020-10-27 23:45 [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers José Roberto de Souza
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 2/6] drm/i915/display/psr: Use plane damage clips to calculate damaged area José Roberto de Souza
@ 2020-10-27 23:45 ` José Roberto de Souza
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Split and export main surface calculation from skl_check_main_surface() José Roberto de Souza
` (5 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2020-10-27 23:45 UTC (permalink / raw)
To: intel-gfx
Planes can individually have transparent, move or have visibility
changed if any of those happens, planes bellow it will be visible or
have more pixels of it visible than before.
This patch is taking care of this case for selective fetch by adding
to each plane damaged area all the intersections of planes above it
that matches with the characteristics described above.
There still some room from improvements here but at least this initial
version will take care of display what is expected saving some memory
reads.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 62 ++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1c3330e096c7..96ee51484dd6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1267,11 +1267,38 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
overlap_damage_area->y2 = damage_area->y2;
}
+/* Update plane damage area if planes above moved or have alpha */
+static void pipe_dirty_areas_set(struct intel_plane_state *plane_state,
+ struct intel_plane *plane,
+ const struct drm_rect *pipe_dirty_areas,
+ struct drm_rect *sel_fetch_area)
+{
+ enum plane_id i;
+
+ for (i = PLANE_CURSOR; i > plane->id; i--) {
+ int j;
+
+ for (j = 0; j < 2; j++) {
+ struct drm_rect r = pipe_dirty_areas[i * 2 + j];
+
+ if (!drm_rect_width(&r))
+ continue;
+ if (!drm_rect_intersect(&r, &plane_state->uapi.dst))
+ continue;
+
+ r.y1 -= plane_state->uapi.dst.y1;
+ r.y2 -= plane_state->uapi.dst.y1;
+ clip_area_update(sel_fetch_area, &r);
+ }
+ }
+}
+
int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
struct intel_plane_state *new_plane_state, *old_plane_state;
+ struct drm_rect pipe_dirty_areas[I915_MAX_PLANES * 2] = {};
struct drm_rect pipe_clip = { .y1 = -1 };
struct intel_plane *plane;
bool full_update = false;
@@ -1284,6 +1311,38 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
if (ret)
return ret;
+ /*
+ * Mark all the areas where there is a plane that matches one of this:
+ * - transparent
+ * - moved
+ * - visibility changed
+ * In all those cases, planes bellow it will need to be redraw.
+ */
+ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
+ new_plane_state, i) {
+ bool alpha, flip, dirty;
+
+ if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
+ continue;
+
+ alpha = new_plane_state->uapi.alpha != DRM_BLEND_ALPHA_OPAQUE;
+ alpha |= old_plane_state->uapi.alpha != DRM_BLEND_ALPHA_OPAQUE;
+ flip = new_plane_state->uapi.fb != old_plane_state->uapi.fb;
+ dirty = alpha && flip;
+
+ dirty |= !drm_rect_equals(&new_plane_state->uapi.dst,
+ &old_plane_state->uapi.dst);
+ dirty |= new_plane_state->uapi.visible !=
+ old_plane_state->uapi.visible;
+ if (!dirty)
+ continue;
+
+ if (old_plane_state->uapi.visible)
+ pipe_dirty_areas[plane->id * 2] = old_plane_state->uapi.dst;
+ if (new_plane_state->uapi.visible)
+ pipe_dirty_areas[plane->id * 2 + 1] = new_plane_state->uapi.dst;
+ }
+
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
new_plane_state, i) {
struct drm_rect *sel_fetch_area, temp;
@@ -1351,6 +1410,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
sel_fetch_area->y2 = 0;
}
+ pipe_dirty_areas_set(new_plane_state, plane, pipe_dirty_areas,
+ sel_fetch_area);
+
/* Don't need to redraw plane damaged areas outside of screen */
j = sel_fetch_area->y2 + new_plane_state->uapi.dst.y1;
j = crtc_state->uapi.adjusted_mode.crtc_vdisplay - j;
--
2.29.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
2020-10-27 23:45 [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers José Roberto de Souza
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 2/6] drm/i915/display/psr: Use plane damage clips to calculate damaged area José Roberto de Souza
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 3/6] drm/i915/display/psr: Consider other planes to damaged area calculation José Roberto de Souza
@ 2020-10-27 23:45 ` José Roberto de Souza
2020-11-27 10:14 ` Mun, Gwan-gyeong
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 5/6] RFC/WIP: drm/i915/display/psr: Consider tiling when doing the plane offset calculation José Roberto de Souza
` (4 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: José Roberto de Souza @ 2020-10-27 23:45 UTC (permalink / raw)
To: intel-gfx
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 95 ++++++++++++--------
drivers/gpu/drm/i915/display/intel_display.h | 2 +
2 files changed, 59 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f41b6f8b5618..460f9c17eea3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3897,6 +3897,56 @@ intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
return y;
}
+int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
+ int *x, int *y, u32 *offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const int aux_plane = intel_main_to_aux_plane(fb, 0);
+ const u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+ const u32 alignment = intel_surf_alignment(fb, 0);
+ const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
+
+ intel_add_fb_offsets(x, y, plane_state, 0);
+ *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
+ if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
+ return -EINVAL;
+
+ /*
+ * AUX surface offset is specified as the distance from the
+ * main surface offset, and it must be non-negative. Make
+ * sure that is what we will get.
+ */
+ if (aux_plane && *offset > aux_offset)
+ *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
+ *offset,
+ aux_offset & ~(alignment - 1));
+
+ /*
+ * When using an X-tiled surface, the plane blows up
+ * if the x offset + width exceed the stride.
+ *
+ * TODO: linear and Y-tiled seem fine, Yf untested,
+ */
+ if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
+ int cpp = fb->format->cpp[0];
+
+ while ((*x + w) * cpp > plane_state->color_plane[0].stride) {
+ if (*offset == 0) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Unable to find suitable display surface offset due to X-tiling\n");
+ return -EINVAL;
+ }
+
+ *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
+ *offset,
+ *offset - alignment);
+ }
+ }
+
+ return 0;
+}
+
static int skl_check_main_surface(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);
@@ -3907,9 +3957,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
int w = drm_rect_width(&plane_state->uapi.src) >> 16;
int h = drm_rect_height(&plane_state->uapi.src) >> 16;
int max_width, min_width, max_height;
- u32 alignment, offset;
- int aux_plane = intel_main_to_aux_plane(fb, 0);
- u32 aux_offset = plane_state->color_plane[aux_plane].offset;
+ const int aux_plane = intel_main_to_aux_plane(fb, 0);
+ const u32 alignment = intel_surf_alignment(fb, 0);
+ u32 offset;
+ int ret;
if (INTEL_GEN(dev_priv) >= 11) {
max_width = icl_max_plane_width(fb, 0, rotation);
@@ -3934,41 +3985,9 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
return -EINVAL;
}
- intel_add_fb_offsets(&x, &y, plane_state, 0);
- offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
- alignment = intel_surf_alignment(fb, 0);
- if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
- return -EINVAL;
-
- /*
- * AUX surface offset is specified as the distance from the
- * main surface offset, and it must be non-negative. Make
- * sure that is what we will get.
- */
- if (aux_plane && offset > aux_offset)
- offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
- offset, aux_offset & ~(alignment - 1));
-
- /*
- * When using an X-tiled surface, the plane blows up
- * if the x offset + width exceed the stride.
- *
- * TODO: linear and Y-tiled seem fine, Yf untested,
- */
- if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
- int cpp = fb->format->cpp[0];
-
- while ((x + w) * cpp > plane_state->color_plane[0].stride) {
- if (offset == 0) {
- drm_dbg_kms(&dev_priv->drm,
- "Unable to find suitable display surface offset due to X-tiling\n");
- return -EINVAL;
- }
-
- offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
- offset, offset - alignment);
- }
- }
+ ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
+ if (ret)
+ return ret;
/*
* CCS AUX surface doesn't have its own x/y offsets, we must make sure
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 1b946209e06b..228ede8788d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -613,6 +613,8 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
u32 skl_plane_stride(const struct intel_plane_state *plane_state,
int plane);
int skl_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
+ int *x, int *y, u32 *offset);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
--
2.29.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Split and export main surface calculation from skl_check_main_surface() José Roberto de Souza
@ 2020-11-27 10:14 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 14+ messages in thread
From: Mun, Gwan-gyeong @ 2020-11-27 10:14 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Souza, Jose
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On Tue, 2020-10-27 at 16:45 -0700, José Roberto de Souza wrote:
> The calculation the offsets of the main surface will be needed by
> PSR2
> selective fetch code so here splitting and exporting it.
> No functional changes were done here.
>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 95 ++++++++++++----
> ----
> drivers/gpu/drm/i915/display/intel_display.h | 2 +
> 2 files changed, 59 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f41b6f8b5618..460f9c17eea3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3897,6 +3897,56 @@ intel_plane_fence_y_offset(const struct
> intel_plane_state *plane_state)
> return y;
> }
>
> +int skl_calc_main_surface_offset(const struct intel_plane_state
> *plane_state,
> + int *x, int *y, u32 *offset)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane_state-
> >uapi.plane->dev);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + const int aux_plane = intel_main_to_aux_plane(fb, 0);
> + const u32 aux_offset = plane_state-
> >color_plane[aux_plane].offset;
> + const u32 alignment = intel_surf_alignment(fb, 0);
> + const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
> +
> + intel_add_fb_offsets(x, y, plane_state, 0);
> + *offset = intel_plane_compute_aligned_offset(x, y, plane_state,
> 0);
> + if (drm_WARN_ON(&dev_priv->drm, alignment &&
> !is_power_of_2(alignment)))
> + return -EINVAL;
> +
> + /*
> + * AUX surface offset is specified as the distance from the
> + * main surface offset, and it must be non-negative. Make
> + * sure that is what we will get.
> + */
> + if (aux_plane && *offset > aux_offset)
> + *offset = intel_plane_adjust_aligned_offset(x, y,
> plane_state, 0,
> + *offset,
> + aux_offset
> & ~(alignment - 1));
> +
> + /*
> + * When using an X-tiled surface, the plane blows up
> + * if the x offset + width exceed the stride.
> + *
> + * TODO: linear and Y-tiled seem fine, Yf untested,
> + */
> + if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
> + int cpp = fb->format->cpp[0];
> +
> + while ((*x + w) * cpp > plane_state-
> >color_plane[0].stride) {
> + if (*offset == 0) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Unable to find suitable
> display surface offset due to X-tiling\n");
> + return -EINVAL;
> + }
> +
> + *offset = intel_plane_adjust_aligned_offset(x,
> y, plane_state, 0,
> + *of
> fset,
> + *of
> fset - alignment);
> + }
> + }
> +
> + return 0;
> +}
> +
> static int skl_check_main_surface(struct intel_plane_state
> *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane_state-
> >uapi.plane->dev);
> @@ -3907,9 +3957,10 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
> int w = drm_rect_width(&plane_state->uapi.src) >> 16;
> int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> int max_width, min_width, max_height;
> - u32 alignment, offset;
> - int aux_plane = intel_main_to_aux_plane(fb, 0);
> - u32 aux_offset = plane_state->color_plane[aux_plane].offset;
> + const int aux_plane = intel_main_to_aux_plane(fb, 0);
> + const u32 alignment = intel_surf_alignment(fb, 0);
> + u32 offset;
> + int ret;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> max_width = icl_max_plane_width(fb, 0, rotation);
> @@ -3934,41 +3985,9 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
> return -EINVAL;
> }
>
> - intel_add_fb_offsets(&x, &y, plane_state, 0);
> - offset = intel_plane_compute_aligned_offset(&x, &y,
> plane_state, 0);
> - alignment = intel_surf_alignment(fb, 0);
> - if (drm_WARN_ON(&dev_priv->drm, alignment &&
> !is_power_of_2(alignment)))
> - return -EINVAL;
> -
> - /*
> - * AUX surface offset is specified as the distance from the
> - * main surface offset, and it must be non-negative. Make
> - * sure that is what we will get.
> - */
> - if (aux_plane && offset > aux_offset)
> - offset = intel_plane_adjust_aligned_offset(&x, &y,
> plane_state, 0,
> - offset,
> aux_offset & ~(alignment - 1));
> -
> - /*
> - * When using an X-tiled surface, the plane blows up
> - * if the x offset + width exceed the stride.
> - *
> - * TODO: linear and Y-tiled seem fine, Yf untested,
> - */
> - if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
> - int cpp = fb->format->cpp[0];
> -
> - while ((x + w) * cpp > plane_state-
> >color_plane[0].stride) {
> - if (offset == 0) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Unable to find suitable
> display surface offset due to X-tiling\n");
> - return -EINVAL;
> - }
> -
> - offset = intel_plane_adjust_aligned_offset(&x,
> &y, plane_state, 0,
> - offs
> et, offset - alignment);
> - }
> - }
> + ret = skl_calc_main_surface_offset(plane_state, &x, &y,
> &offset);
> + if (ret)
> + return ret;
>
> /*
> * CCS AUX surface doesn't have its own x/y offsets, we must
> make sure
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 1b946209e06b..228ede8788d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -613,6 +613,8 @@ u32 skl_plane_ctl_crtc(const struct
> intel_crtc_state *crtc_state);
> u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> int plane);
> int skl_check_plane_surface(struct intel_plane_state *plane_state);
> +int skl_calc_main_surface_offset(const struct intel_plane_state
> *plane_state,
> + int *x, int *y, u32 *offset);
> int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
> unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH v2 5/6] RFC/WIP: drm/i915/display/psr: Consider tiling when doing the plane offset calculation
2020-10-27 23:45 [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers José Roberto de Souza
` (2 preceding siblings ...)
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 4/6] drm/i915/display: Split and export main surface calculation from skl_check_main_surface() José Roberto de Souza
@ 2020-10-27 23:45 ` José Roberto de Souza
2020-11-27 10:19 ` Mun, Gwan-gyeong
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 6/6] HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing José Roberto de Souza
` (3 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: José Roberto de Souza @ 2020-10-27 23:45 UTC (permalink / raw)
To: intel-gfx
Do the calculation of x and y offsets using
skl_calc_main_surface_offset().
RFC/WIP: This causes the value of the calculated x to be different than
plane_state->color_plane[color_plane].x, not sure if that is expected.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 96ee51484dd6..00c76ea82f92 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1188,7 +1188,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
const struct drm_rect *clip;
- u32 val;
+ u32 val, offset;
+ int ret, x, y;
if (!crtc_state->enable_psr2_sel_fetch)
return;
@@ -1205,9 +1206,14 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
val |= plane_state->uapi.dst.x1;
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
- /* TODO: consider tiling and auxiliary surfaces */
- val = (clip->y1 + plane_state->color_plane[color_plane].y) << 16;
- val |= plane_state->color_plane[color_plane].x;
+ /* TODO: consider auxiliary surfaces */
+ x = plane_state->uapi.src.x1 >> 16;
+ y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
+ ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
+ if (ret)
+ drm_warn_once(&dev_priv->drm, "skl_calc_main_surface_offset() returned %i\n",
+ ret);
+ val = y << 16 | x;
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
val);
--
2.29.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH v2 5/6] RFC/WIP: drm/i915/display/psr: Consider tiling when doing the plane offset calculation
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 5/6] RFC/WIP: drm/i915/display/psr: Consider tiling when doing the plane offset calculation José Roberto de Souza
@ 2020-11-27 10:19 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 14+ messages in thread
From: Mun, Gwan-gyeong @ 2020-11-27 10:19 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Souza, Jose
It works properly on a normal rgba plane.
In order to apply this patch, the commit messaged need to be polished.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On Tue, 2020-10-27 at 16:45 -0700, José Roberto de Souza wrote:
> Do the calculation of x and y offsets using
> skl_calc_main_surface_offset().
>
> RFC/WIP: This causes the value of the calculated x to be different
> than
> plane_state->color_plane[color_plane].x, not sure if that is
> expected.
>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 96ee51484dd6..00c76ea82f92 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1188,7 +1188,8 @@ void intel_psr2_program_plane_sel_fetch(struct
> intel_plane *plane,
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> const struct drm_rect *clip;
> - u32 val;
> + u32 val, offset;
> + int ret, x, y;
>
> if (!crtc_state->enable_psr2_sel_fetch)
> return;
> @@ -1205,9 +1206,14 @@ void intel_psr2_program_plane_sel_fetch(struct
> intel_plane *plane,
> val |= plane_state->uapi.dst.x1;
> intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> >id), val);
>
> - /* TODO: consider tiling and auxiliary surfaces */
> - val = (clip->y1 + plane_state->color_plane[color_plane].y) <<
> 16;
> - val |= plane_state->color_plane[color_plane].x;
> + /* TODO: consider auxiliary surfaces */
> + x = plane_state->uapi.src.x1 >> 16;
> + y = (plane_state->uapi.src.y1 >> 16) + clip->y1;
> + ret = skl_calc_main_surface_offset(plane_state, &x, &y,
> &offset);
> + if (ret)
> + drm_warn_once(&dev_priv->drm,
> "skl_calc_main_surface_offset() returned %i\n",
> + ret);
> + val = y << 16 | x;
> intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> >id),
> val);
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH v2 6/6] HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing
2020-10-27 23:45 [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers José Roberto de Souza
` (3 preceding siblings ...)
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 5/6] RFC/WIP: drm/i915/display/psr: Consider tiling when doing the plane offset calculation José Roberto de Souza
@ 2020-10-27 23:45 ` José Roberto de Souza
2020-10-28 5:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/6] drm/i915/display/psr: Calculate selective fetch plane registers Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: José Roberto de Souza @ 2020-10-27 23:45 UTC (permalink / raw)
To: intel-gfx
Enabling it to check if it causes regressions in CI but the feature is
still not ready to be enabled by default.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 330c03e2b4f7..b8b19270c339 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
param(int, enable_fbc, -1, 0600) \
param(int, enable_psr, -1, 0600) \
param(bool, psr_safest_params, false, 0600) \
- param(bool, enable_psr2_sel_fetch, false, 0600) \
+ param(bool, enable_psr2_sel_fetch, true, 0600) \
param(int, disable_power_well, -1, 0400) \
param(int, enable_ips, 1, 0600) \
param(int, invert_brightness, 0, 0600) \
--
2.29.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/6] drm/i915/display/psr: Calculate selective fetch plane registers
2020-10-27 23:45 [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers José Roberto de Souza
` (4 preceding siblings ...)
2020-10-27 23:45 ` [Intel-gfx] [PATCH v2 6/6] HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing José Roberto de Souza
@ 2020-10-28 5:25 ` Patchwork
2020-10-28 5:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-10-29 21:37 ` [Intel-gfx] [PATCH v2 1/6] " Mun, Gwan-gyeong
7 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-10-28 5:25 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/display/psr: Calculate selective fetch plane registers
URL : https://patchwork.freedesktop.org/series/83119/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/6] drm/i915/display/psr: Calculate selective fetch plane registers
2020-10-27 23:45 [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers José Roberto de Souza
` (5 preceding siblings ...)
2020-10-28 5:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/6] drm/i915/display/psr: Calculate selective fetch plane registers Patchwork
@ 2020-10-28 5:54 ` Patchwork
2020-10-29 0:13 ` Souza, Jose
2020-10-29 21:37 ` [Intel-gfx] [PATCH v2 1/6] " Mun, Gwan-gyeong
7 siblings, 1 reply; 14+ messages in thread
From: Patchwork @ 2020-10-28 5:54 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 11413 bytes --]
== Series Details ==
Series: series starting with [v2,1/6] drm/i915/display/psr: Calculate selective fetch plane registers
URL : https://patchwork.freedesktop.org/series/83119/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18793
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18793 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18793, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18793:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-tgl-y: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
#### Warnings ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-y: [DMESG-WARN][5] ([i915#1982]) -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@runner@aborted:
- fi-cfl-8109u: [FAIL][7] ([k.org#202107] / [k.org#202109]) -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-cfl-8109u/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-cfl-8109u/igt@runner@aborted.html
New tests
---------
New tests have been introduced between CI_DRM_9206 and Patchwork_18793:
### New CI tests (1) ###
* boot:
- Statuses : 41 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18793 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-tgl-u2: [PASS][9] -> [DMESG-WARN][10] ([i915#402])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-u2/igt@debugfs_test@read_all_entries.html
* igt@gem_ctx_create@basic-files:
- fi-apl-guc: [PASS][11] -> [INCOMPLETE][12] ([i915#1635])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-apl-guc/igt@gem_ctx_create@basic-files.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-apl-guc/igt@gem_ctx_create@basic-files.html
* igt@i915_module_load@reload:
- fi-byt-j1900: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-byt-j1900/igt@i915_module_load@reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-byt-j1900/igt@i915_module_load@reload.html
* igt@kms_busy@basic@flip:
- fi-kbl-soraka: [PASS][15] -> [DMESG-WARN][16] ([i915#1982])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-soraka/igt@kms_busy@basic@flip.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-kbl-soraka/igt@kms_busy@basic@flip.html
- fi-tgl-y: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_busy@basic@flip.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][19] -> [INCOMPLETE][20] ([i915#2606])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-tgl-y: [PASS][21] -> [DMESG-WARN][22] ([i915#402]) +5 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- fi-tgl-y: [PASS][23] -> [DMESG-FAIL][24] ([i915#402]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html
* igt@kms_psr@primary_page_flip:
- fi-tgl-u2: [PASS][25] -> [SKIP][26] ([i915#668]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-u2/igt@kms_psr@primary_page_flip.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-u2/igt@kms_psr@primary_page_flip.html
- fi-kbl-soraka: [PASS][27] -> [INCOMPLETE][28] ([i915#2606])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-soraka/igt@kms_psr@primary_page_flip.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-kbl-soraka/igt@kms_psr@primary_page_flip.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [INCOMPLETE][29] ([i915#2540]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
* igt@debugfs_test@read_all_entries:
- {fi-kbl-7560u}: [INCOMPLETE][31] ([i915#2417]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s3:
- fi-byt-j1900: [DMESG-WARN][33] ([i915#1982]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-byt-j1900/igt@gem_exec_suspend@basic-s3.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-byt-j1900/igt@gem_exec_suspend@basic-s3.html
* igt@i915_module_load@reload:
- {fi-ehl-1}: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-ehl-1/igt@i915_module_load@reload.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-ehl-1/igt@i915_module_load@reload.html
- fi-skl-lmem: [DMESG-WARN][37] ([i915#2605]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-skl-lmem/igt@i915_module_load@reload.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-skl-lmem/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_psr@sprite_plane_onoff:
- fi-tgl-y: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_psr@sprite_plane_onoff.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_psr@sprite_plane_onoff.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [DMESG-WARN][43] ([i915#402]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@prime_vgem@basic-read.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@prime_vgem@basic-read.html
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-tgl-y: [DMESG-WARN][45] ([i915#2411]) -> [DMESG-WARN][46] ([i915#1982] / [i915#2411])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1784]: https://gitlab.freedesktop.org/drm/intel/issues/1784
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2417]: https://gitlab.freedesktop.org/drm/intel/issues/2417
[i915#2540]: https://gitlab.freedesktop.org/drm/intel/issues/2540
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#2606]: https://gitlab.freedesktop.org/drm/intel/issues/2606
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[k.org#202107]: https://bugzilla.kernel.org/show_bug.cgi?id=202107
[k.org#202109]: https://bugzilla.kernel.org/show_bug.cgi?id=202109
Participating hosts (43 -> 41)
------------------------------
Missing (2): fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9206 -> Patchwork_18793
CI-20190529: 20190529
CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18793: 524e59edd723db54e5dcc3282bed18a6b08d5b66 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
524e59edd723 HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing
4bb764e0fd8c RFC/WIP: drm/i915/display/psr: Consider tiling when doing the plane offset calculation
a542d2e2472d drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
8fc4928b3976 drm/i915/display/psr: Consider other planes to damaged area calculation
ed22efb12033 drm/i915/display/psr: Use plane damage clips to calculate damaged area
0a61bec54546 drm/i915/display/psr: Calculate selective fetch plane registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/index.html
[-- Attachment #1.2: Type: text/html, Size: 13327 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/6] drm/i915/display/psr: Calculate selective fetch plane registers
2020-10-28 5:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-10-29 0:13 ` Souza, Jose
0 siblings, 0 replies; 14+ messages in thread
From: Souza, Jose @ 2020-10-29 0:13 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org
[-- Attachment #1.1: Type: text/plain, Size: 11110 bytes --]
On Wed, 2020-10-28 at 05:54 +0000, Patchwork wrote:
Patch Details
Series: series starting with [v2,1/6] drm/i915/display/psr: Calculate selective fetch plane registers
URL: https://patchwork.freedesktop.org/series/83119/
State: failure
Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/index.html
CI Bug Log - changes from CI_DRM_9206 -> Patchwork_18793
Summary
FAILURE
Serious unknown changes coming with Patchwork_18793 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18793, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/index.html
Possible new issues
Here are the unknown changes that may have been introduced in Patchwork_18793:
IGT changes
Possible regressions
* igt@i915_selftest@live@gt_lrc:
* fi-bsw-n3050: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html> -> DMESG-FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html>
Unrelated.
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
* fi-tgl-y: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html> -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html>
This one will be a test that we need to fix, it is using legacy api that do not calls current PSR2 sel fetch functions.
But for the initial enabling of selective fetch when doing page flips it is out of scope.
Warnings
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
* fi-tgl-y: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html> (i915#1982<https://gitlab.freedesktop.org/drm/intel/issues/1982>) -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html>
* igt@runner@aborted:
* fi-cfl-8109u: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-cfl-8109u/igt@runner@aborted.html> (k.org#202107<https://bugzilla.kernel.org/show_bug.cgi?id=202107> / k.org#202109<https://bugzilla.kernel.org/show_bug.cgi?id=202109>) -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-cfl-8109u/igt@runner@aborted.html>
New tests
New tests have been introduced between CI_DRM_9206 and Patchwork_18793:
New CI tests (1)
* boot:
* Statuses : 41 pass(s)
* Exec time: [0.0] s
Known issues
Here are the changes found in Patchwork_18793 that come from known issues:
IGT changes
Issues hit
* igt@debugfs_test@read_all_entries:
* fi-tgl-u2: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-u2/igt@debugfs_test@read_all_entries.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-u2/igt@debugfs_test@read_all_entries.html> (i915#402<https://gitlab.freedesktop.org/drm/intel/issues/402>)
* igt@gem_ctx_create@basic-files:
* fi-apl-guc: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-apl-guc/igt@gem_ctx_create@basic-files.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-apl-guc/igt@gem_ctx_create@basic-files.html> (i915#1635<https://gitlab.freedesktop.org/drm/intel/issues/1635>)
* igt@i915_module_load@reload:
* fi-byt-j1900: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-byt-j1900/igt@i915_module_load@reload.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-byt-j1900/igt@i915_module_load@reload.html> (i915#1982<https://gitlab.freedesktop.org/drm/intel/issues/1982>)
* igt@kms_busy@basic@flip:
* fi-kbl-soraka: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-soraka/igt@kms_busy@basic@flip.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-kbl-soraka/igt@kms_busy@basic@flip.html> (i915#1982<https://gitlab.freedesktop.org/drm/intel/issues/1982>)
* fi-tgl-y: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_busy@basic@flip.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_busy@basic@flip.html> (i915#1982<https://gitlab.freedesktop.org/drm/intel/issues/1982>) +1 similar issue
* igt@kms_chamelium@dp-crc-fast:
* fi-cml-u2: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html> (i915#2606<https://gitlab.freedesktop.org/drm/intel/issues/2606>)
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
* fi-tgl-y: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html> (i915#402<https://gitlab.freedesktop.org/drm/intel/issues/402>) +5 similar issues
* igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
* fi-tgl-y: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html> -> DMESG-FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_cursor_legacy@basic-flip-before-cursor-legacy.html> (i915#402<https://gitlab.freedesktop.org/drm/intel/issues/402>) +1 similar issue
* igt@kms_psr@primary_page_flip:
* fi-tgl-u2: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-u2/igt@kms_psr@primary_page_flip.html> -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-u2/igt@kms_psr@primary_page_flip.html> (i915#668<https://gitlab.freedesktop.org/drm/intel/issues/668>) +1 similar issue
* fi-kbl-soraka: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-soraka/igt@kms_psr@primary_page_flip.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-kbl-soraka/igt@kms_psr@primary_page_flip.html> (i915#2606<https://gitlab.freedesktop.org/drm/intel/issues/2606>)
Possible fixes
* igt@core_hotunplug@unbind-rebind:
* fi-blb-e6850: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html> (i915#2540<https://gitlab.freedesktop.org/drm/intel/issues/2540>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html>
* igt@debugfs_test@read_all_entries:
* {fi-kbl-7560u}: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html> (i915#2417<https://gitlab.freedesktop.org/drm/intel/issues/2417>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-kbl-7560u/igt@debugfs_test@read_all_entries.html>
* igt@gem_exec_suspend@basic-s3:
* fi-byt-j1900: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-byt-j1900/igt@gem_exec_suspend@basic-s3.html> (i915#1982<https://gitlab.freedesktop.org/drm/intel/issues/1982>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-byt-j1900/igt@gem_exec_suspend@basic-s3.html>
* igt@i915_module_load@reload:
* {fi-ehl-1}: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-ehl-1/igt@i915_module_load@reload.html> (i915#1982<https://gitlab.freedesktop.org/drm/intel/issues/1982>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-ehl-1/igt@i915_module_load@reload.html>
* fi-skl-lmem: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-skl-lmem/igt@i915_module_load@reload.html> (i915#2605<https://gitlab.freedesktop.org/drm/intel/issues/2605>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-skl-lmem/igt@i915_module_load@reload.html>
* igt@i915_pm_rpm@basic-pci-d3-state:
* fi-bsw-kefka: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html> (i915#1982<https://gitlab.freedesktop.org/drm/intel/issues/1982>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html>
* igt@kms_psr@sprite_plane_onoff:
* fi-tgl-y: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@kms_psr@sprite_plane_onoff.html> (i915#1982<https://gitlab.freedesktop.org/drm/intel/issues/1982>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@kms_psr@sprite_plane_onoff.html>
* igt@prime_vgem@basic-read:
* fi-tgl-y: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@prime_vgem@basic-read.html> (i915#402<https://gitlab.freedesktop.org/drm/intel/issues/402>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@prime_vgem@basic-read.html> +1 similar issue
Warnings
* igt@i915_pm_rpm@module-reload:
* fi-tgl-y: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/fi-tgl-y/igt@i915_pm_rpm@module-reload.html> (i915#2411<https://gitlab.freedesktop.org/drm/intel/issues/2411>) -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18793/fi-tgl-y/igt@i915_pm_rpm@module-reload.html> (i915#1982<https://gitlab.freedesktop.org/drm/intel/issues/1982> / i915#2411<https://gitlab.freedesktop.org/drm/intel/issues/2411>)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Participating hosts (43 -> 41)
Missing (2): fi-bsw-cyan fi-bdw-samus
Build changes
* Linux: CI_DRM_9206 -> Patchwork_18793
CI-20190529: 20190529
CI_DRM_9206: 85ce674ff932ed7ca41aef52d8bb42c04fbe2171 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5827: 7fd7e3fb8b42eb4e62a4575f6edc5a048e5bec3d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18793: 524e59edd723db54e5dcc3282bed18a6b08d5b66 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
524e59edd723 HAX/DO_NOT_MERGE_IT: drm/i915/display: Enable PSR2 selective fetch for testing
4bb764e0fd8c RFC/WIP: drm/i915/display/psr: Consider tiling when doing the plane offset calculation
a542d2e2472d drm/i915/display: Split and export main surface calculation from skl_check_main_surface()
8fc4928b3976 drm/i915/display/psr: Consider other planes to damaged area calculation
ed22efb12033 drm/i915/display/psr: Use plane damage clips to calculate damaged area
0a61bec54546 drm/i915/display/psr: Calculate selective fetch plane registers
[-- Attachment #1.2: Type: text/html, Size: 14181 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers
2020-10-27 23:45 [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers José Roberto de Souza
` (6 preceding siblings ...)
2020-10-28 5:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-10-29 21:37 ` Mun, Gwan-gyeong
2020-11-02 19:18 ` Souza, Jose
7 siblings, 1 reply; 14+ messages in thread
From: Mun, Gwan-gyeong @ 2020-10-29 21:37 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Souza, Jose
On Tue, 2020-10-27 at 16:45 -0700, José Roberto de Souza wrote:
> Add the calculations to set plane selective fetch registers depending
> in the value of the area damaged.
> It is still using the whole plane area as damaged but that will
> change
> in next patches.
>
> v2:
> - fixed new_plane_state->uapi.dst.y2 typo in
> intel_psr2_sel_fetch_update()
> - do not shifthing new_plane_state->uapi.dst only src is in 16.16
> format
>
> BSpec: 55229
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 2 ++
> drivers/gpu/drm/i915/display/intel_psr.c | 22 ++++++++++++++---
> --
> 2 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6f0626649e0..3f2707d882cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -604,6 +604,8 @@ struct intel_plane_state {
> u32 planar_slave;
>
> struct drm_intel_sprite_colorkey ckey;
> +
> + struct drm_rect psr2_sel_fetch_area;
> };
>
> struct intel_initial_plane_config {
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b2544102e7b1..6dead51d7a81 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1187,6 +1187,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> intel_plane *plane,
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum pipe pipe = plane->pipe;
> + const struct drm_rect *clip;
> u32 val;
>
> if (!crtc_state->enable_psr2_sel_fetch)
> @@ -1198,16 +1199,20 @@ void
> intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> if (!val || plane->id == PLANE_CURSOR)
> return;
>
> - val = plane_state->uapi.dst.y1 << 16 | plane_state-
> >uapi.dst.x1;
> + clip = &plane_state->psr2_sel_fetch_area;
> +
> + val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
> + val |= plane_state->uapi.dst.x1;
> intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> >id), val);
>
> - val = plane_state->color_plane[color_plane].y << 16;
> + /* TODO: consider tiling and auxiliary surfaces */
> + val = (clip->y1 + plane_state->color_plane[color_plane].y) <<
> 16;
> val |= plane_state->color_plane[color_plane].x;
> intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> >id),
> val);
>
> /* Sizes are 0 based */
> - val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) <<
> 16;
> + val = (drm_rect_height(clip) - 1) << 16;
> val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> >id), val);
> }
> @@ -1281,7 +1286,7 @@ int intel_psr2_sel_fetch_update(struct
> intel_atomic_state *state,
>
> for_each_oldnew_intel_plane_in_state(state, plane,
> old_plane_state,
> new_plane_state, i) {
> - struct drm_rect temp;
> + struct drm_rect *sel_fetch_area, temp;
>
> if (new_plane_state->uapi.crtc != crtc_state-
> >uapi.crtc)
> continue;
> @@ -1304,8 +1309,13 @@ int intel_psr2_sel_fetch_update(struct
> intel_atomic_state *state,
> * For now doing a selective fetch in the whole plane
> area,
> * optimizations will come in the future.
> */
> - temp.y1 = new_plane_state->uapi.dst.y1;
> - temp.y2 = new_plane_state->uapi.dst.y2;
> + sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
> + sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >>
> 16;
> + sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >>
> 16;
> +
> + temp = *sel_fetch_area;
> + temp.y1 += new_plane_state->uapi.dst.y1;
> + temp.y2 += new_plane_state->uapi.dst.y2;
when the userspace call drmModeSetPlane(), src_y and crtc_y can be
differ.
(drm core uses drm_rect_translate_to() utility function for apply
coordinate traslate to dst from src. )
In my opinion, we can calculate like as,
int coord_trans = new_plane_state->uapi.dst.y1 - new_plane_state-
>uapi.src.y1 >> 16;
temp = *sel_fetch_area; // assunes that sel_fetch_area has damage area.
temp.y1 += coord_trans;
temp.y2 += coord_trans;
> clip_area_update(&pipe_clip, &temp);
As we don't check and calculate plane rotation and scale for dst
coordinates here.
so can you add checking of plane scale or rotation? and if the plane
has a scale factor or rotation, for now, we should not apply PSR SU.
(if plane scale or rotation are used, dst might differ. if we don't
apply PSR SU, we don't need to call clip_area_update() here. )
> }
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers
2020-10-29 21:37 ` [Intel-gfx] [PATCH v2 1/6] " Mun, Gwan-gyeong
@ 2020-11-02 19:18 ` Souza, Jose
2020-11-27 10:13 ` Mun, Gwan-gyeong
0 siblings, 1 reply; 14+ messages in thread
From: Souza, Jose @ 2020-11-02 19:18 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx@lists.freedesktop.org
On Thu, 2020-10-29 at 21:37 +0000, Mun, Gwan-gyeong wrote:
> On Tue, 2020-10-27 at 16:45 -0700, José Roberto de Souza wrote:
> > Add the calculations to set plane selective fetch registers depending
> > in the value of the area damaged.
> > It is still using the whole plane area as damaged but that will
> > change
> > in next patches.
> >
> > v2:
> > - fixed new_plane_state->uapi.dst.y2 typo in
> > intel_psr2_sel_fetch_update()
> > - do not shifthing new_plane_state->uapi.dst only src is in 16.16
> > format
> >
> > BSpec: 55229
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 2 ++
> > drivers/gpu/drm/i915/display/intel_psr.c | 22 ++++++++++++++---
> > --
> > 2 files changed, 18 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index f6f0626649e0..3f2707d882cc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -604,6 +604,8 @@ struct intel_plane_state {
> > u32 planar_slave;
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > struct drm_intel_sprite_colorkey ckey;
> > +
> > + struct drm_rect psr2_sel_fetch_area;
> > };
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > struct intel_initial_plane_config {
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index b2544102e7b1..6dead51d7a81 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1187,6 +1187,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> > intel_plane *plane,
> > {
> > struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > enum pipe pipe = plane->pipe;
> > + const struct drm_rect *clip;
> > u32 val;
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > if (!crtc_state->enable_psr2_sel_fetch)
> > @@ -1198,16 +1199,20 @@ void
> > intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > if (!val || plane->id == PLANE_CURSOR)
> > return;
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > - val = plane_state->uapi.dst.y1 << 16 | plane_state-
> > > uapi.dst.x1;
> > + clip = &plane_state->psr2_sel_fetch_area;
> > +
> > + val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
> > + val |= plane_state->uapi.dst.x1;
> > intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> > > id), val);
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > - val = plane_state->color_plane[color_plane].y << 16;
> > + /* TODO: consider tiling and auxiliary surfaces */
> > + val = (clip->y1 + plane_state->color_plane[color_plane].y) <<
> > 16;
> > val |= plane_state->color_plane[color_plane].x;
> > intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> > > id),
> > val);
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > /* Sizes are 0 based */
> > - val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) <<
> > 16;
> > + val = (drm_rect_height(clip) - 1) << 16;
> > val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> > intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> > > id), val);
> > }
> > @@ -1281,7 +1286,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > for_each_oldnew_intel_plane_in_state(state, plane,
> > old_plane_state,
> > new_plane_state, i) {
> > - struct drm_rect temp;
> > + struct drm_rect *sel_fetch_area, temp;
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > if (new_plane_state->uapi.crtc != crtc_state-
> > > uapi.crtc)
> > continue;
> > @@ -1304,8 +1309,13 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > * For now doing a selective fetch in the whole plane
> > area,
> > * optimizations will come in the future.
> > */
> > - temp.y1 = new_plane_state->uapi.dst.y1;
> > - temp.y2 = new_plane_state->uapi.dst.y2;
> > + sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
> > + sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >>
> > 16;
> > + sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >>
> > 16;
> > +
> > + temp = *sel_fetch_area;
> > + temp.y1 += new_plane_state->uapi.dst.y1;
> > + temp.y2 += new_plane_state->uapi.dst.y2;
> when the userspace call drmModeSetPlane(), src_y and crtc_y can be
> differ.
> (drm core uses drm_rect_translate_to() utility function for apply
> coordinate traslate to dst from src. )
Checking drm_atomic_helper_update_plane() it sets userspace values to plane_state->crtc_ and plane_state->src_, then atomic code will set the right
values back to uapi.dst and uapi.src.
>
> In my opinion, we can calculate like as,
> int coord_trans = new_plane_state->uapi.dst.y1 - new_plane_state-
> > uapi.src.y1 >> 16;
> temp = *sel_fetch_area; // assunes that sel_fetch_area has damage area.
> temp.y1 += coord_trans;
> temp.y2 += coord_trans;
uapi.dst.x1/y1 is the coordinates where plane should be placed in pipe to be combined with other planes(skl_program_plane()), that exactly what we
need to compute the damaged areas of the whole pipe.
>
> > clip_area_update(&pipe_clip, &temp);
>
> As we don't check and calculate plane rotation and scale for dst
> coordinates here.
> so can you add checking of plane scale or rotation? and if the plane
> has a scale factor or rotation, for now, we should not apply PSR SU.
> (if plane scale or rotation are used, dst might differ. if we don't
> apply PSR SU, we don't need to call clip_area_update() here. )
Rotation is not supported by selective fetch(intel_psr2_sel_fetch_config_valid()) about scale, the scaler HW will take care of adjust the original
size but I doubt that scale works with PSR panels.
> > }
> >
> >
> >
> >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/display/psr: Calculate selective fetch plane registers
2020-11-02 19:18 ` Souza, Jose
@ 2020-11-27 10:13 ` Mun, Gwan-gyeong
0 siblings, 0 replies; 14+ messages in thread
From: Mun, Gwan-gyeong @ 2020-11-27 10:13 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Souza, Jose
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On Mon, 2020-11-02 at 11:18 -0800, Souza, Jose wrote:
> On Thu, 2020-10-29 at 21:37 +0000, Mun, Gwan-gyeong wrote:
> > On Tue, 2020-10-27 at 16:45 -0700, José Roberto de Souza wrote:
> > > Add the calculations to set plane selective fetch registers
> > > depending
> > > in the value of the area damaged.
> > > It is still using the whole plane area as damaged but that will
> > > change
> > > in next patches.
> > >
> > > v2:
> > > - fixed new_plane_state->uapi.dst.y2 typo in
> > > intel_psr2_sel_fetch_update()
> > > - do not shifthing new_plane_state->uapi.dst only src is in 16.16
> > > format
> > >
> > > BSpec: 55229
> > > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 2 ++
> > > drivers/gpu/drm/i915/display/intel_psr.c | 22
> > > ++++++++++++++---
> > > --
> > > 2 files changed, 18 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index f6f0626649e0..3f2707d882cc 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -604,6 +604,8 @@ struct intel_plane_state {
> > > u32 planar_slave;
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > struct drm_intel_sprite_colorkey ckey;
> > > +
> > > + struct drm_rect psr2_sel_fetch_area;
> > > };
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > struct intel_initial_plane_config {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index b2544102e7b1..6dead51d7a81 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1187,6 +1187,7 @@ void
> > > intel_psr2_program_plane_sel_fetch(struct
> > > intel_plane *plane,
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > enum pipe pipe = plane->pipe;
> > > + const struct drm_rect *clip;
> > > u32 val;
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > if (!crtc_state->enable_psr2_sel_fetch)
> > > @@ -1198,16 +1199,20 @@ void
> > > intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > > if (!val || plane->id == PLANE_CURSOR)
> > > return;
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > - val = plane_state->uapi.dst.y1 << 16 | plane_state-
> > > > uapi.dst.x1;
> > > + clip = &plane_state->psr2_sel_fetch_area;
> > > +
> > > + val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
> > > + val |= plane_state->uapi.dst.x1;
> > > intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> > > > id), val);
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > - val = plane_state->color_plane[color_plane].y << 16;
> > > + /* TODO: consider tiling and auxiliary surfaces */
> > > + val = (clip->y1 + plane_state->color_plane[color_plane].y) <<
> > > 16;
> > > val |= plane_state->color_plane[color_plane].x;
> > > intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> > > > id),
> > > val);
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > /* Sizes are 0 based */
> > > - val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) <<
> > > 16;
> > > + val = (drm_rect_height(clip) - 1) << 16;
> > > val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> > > intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> > > > id), val);
> > > }
> > > @@ -1281,7 +1286,7 @@ int intel_psr2_sel_fetch_update(struct
> > > intel_atomic_state *state,
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > for_each_oldnew_intel_plane_in_state(state, plane,
> > > old_plane_state,
> > > new_plane_state, i) {
> > > - struct drm_rect temp;
> > > + struct drm_rect *sel_fetch_area, temp;
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > if (new_plane_state->uapi.crtc != crtc_state-
> > > > uapi.crtc)
> > > continue;
> > > @@ -1304,8 +1309,13 @@ int intel_psr2_sel_fetch_update(struct
> > > intel_atomic_state *state,
> > > * For now doing a selective fetch in the whole plane
> > > area,
> > > * optimizations will come in the future.
> > > */
> > > - temp.y1 = new_plane_state->uapi.dst.y1;
> > > - temp.y2 = new_plane_state->uapi.dst.y2;
> > > + sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
> > > + sel_fetch_area->y1 = new_plane_state->uapi.src.y1 >>
> > > 16;
> > > + sel_fetch_area->y2 = new_plane_state->uapi.src.y2 >>
> > > 16;
> > > +
> > > + temp = *sel_fetch_area;
> > > + temp.y1 += new_plane_state->uapi.dst.y1;
> > > + temp.y2 += new_plane_state->uapi.dst.y2;
> > when the userspace call drmModeSetPlane(), src_y and crtc_y can be
> > differ.
> > (drm core uses drm_rect_translate_to() utility function for apply
> > coordinate traslate to dst from src. )
>
> Checking drm_atomic_helper_update_plane() it sets userspace values to
> plane_state->crtc_ and plane_state->src_, then atomic code will set
> the right
> values back to uapi.dst and uapi.src.
>
> > In my opinion, we can calculate like as,
> > int coord_trans = new_plane_state->uapi.dst.y1 - new_plane_state-
> > > uapi.src.y1 >> 16;
> > temp = *sel_fetch_area; // assunes that sel_fetch_area has damage
> > area.
> > temp.y1 += coord_trans;
> > temp.y2 += coord_trans;
>
> uapi.dst.x1/y1 is the coordinates where plane should be placed in
> pipe to be combined with other planes(skl_program_plane()), that
> exactly what we
> need to compute the damaged areas of the whole pipe.
>
> > > clip_area_update(&pipe_clip, &temp);
> >
> > As we don't check and calculate plane rotation and scale for dst
> > coordinates here.
> > so can you add checking of plane scale or rotation? and if the
> > plane
> > has a scale factor or rotation, for now, we should not apply PSR
> > SU.
> > (if plane scale or rotation are used, dst might differ. if we don't
> > apply PSR SU, we don't need to call clip_area_update() here. )
>
> Rotation is not supported by selective
> fetch(intel_psr2_sel_fetch_config_valid()) about scale, the scaler HW
> will take care of adjust the original
> size but I doubt that scale works with PSR panels.
>
> > > }
> > >
> > >
> > >
> > >
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread