From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Kamble, Sagar A" Subject: Re: [PATCH v3] drm/i915/gen9: Update i915_drpc_info debugfs for coarse pg & forcewake info Date: Mon, 1 Aug 2016 23:18:15 +0530 Message-ID: <36070a9d-b19b-e918-b4b4-485d015b8086@intel.com> References: <1421431648-22904-5-git-send-email-damien.lespiau@intel.com> <1467038401-8283-1-git-send-email-akash.goel@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0391751321==" Return-path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id A7A916E156 for ; Mon, 1 Aug 2016 17:48:21 +0000 (UTC) In-Reply-To: <1467038401-8283-1-git-send-email-akash.goel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: akash.goel@intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org This is a multi-part message in MIME format. --===============0391751321== Content-Type: multipart/alternative; boundary="------------7453140A10623E7A6E0A2EAF" This is a multi-part message in MIME format. --------------7453140A10623E7A6E0A2EAF Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Reviewed-by: Sagar Arun Kamble > On 6/27/2016 8:10 PM, akash.goel@intel.com wrote: > From: Akash Goel > > Updated the i915_drpc_info debugfs with coarse power gating & forcewake > info for Gen9. > > v2: Change all IS_GEN9() by gen >= 9 (Damien) > > v3: Rebase > > Cc: Damien Lespiau > Signed-off-by: Akash Goel > --- > drivers/gpu/drm/i915/i915_debugfs.c | 21 ++++++++++++++++++++- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > 2 files changed, 23 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index f664884..5185e02 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1588,6 +1588,7 @@ static int gen6_drpc_info(struct seq_file *m) > struct drm_device *dev = node->minor->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; > + u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; > unsigned forcewake_count; > int count = 0, ret; > > @@ -1615,6 +1616,10 @@ static int gen6_drpc_info(struct seq_file *m) > > rpmodectl1 = I915_READ(GEN6_RP_CONTROL); > rcctl1 = I915_READ(GEN6_RC_CONTROL); > + if (INTEL_INFO(dev)->gen >= 9) { > + gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); > + gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); > + } > mutex_unlock(&dev->struct_mutex); > mutex_lock(&dev_priv->rps.hw_lock); > sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); > @@ -1633,6 +1638,12 @@ static int gen6_drpc_info(struct seq_file *m) > yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); > seq_printf(m, "RC6 Enabled: %s\n", > yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); > + if (INTEL_INFO(dev)->gen >= 9) { > + seq_printf(m, "Render Well Gating Enabled: %s\n", > + yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); > + seq_printf(m, "Media Well Gating Enabled: %s\n", > + yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); > + } > seq_printf(m, "Deep RC6 Enabled: %s\n", > yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); > seq_printf(m, "Deepest RC6 Enabled: %s\n", > @@ -1661,6 +1672,14 @@ static int gen6_drpc_info(struct seq_file *m) > > seq_printf(m, "Core Power Down: %s\n", > yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); > + if (INTEL_INFO(dev)->gen >= 9) { > + seq_printf(m, "Render Power Well: %s\n", > + (gen9_powergate_status & > + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); > + seq_printf(m, "Media Power Well: %s\n", > + (gen9_powergate_status & > + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); > + } > > /* Not exactly sure what this is */ > seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", > @@ -1678,7 +1697,7 @@ static int gen6_drpc_info(struct seq_file *m) > GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); > seq_printf(m, "RC6++ voltage: %dmV\n", > GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); > - return 0; > + return i915_forcewake_domains(m, NULL); > } > > static int i915_drpc_info(struct seq_file *m, void *unused) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c6bfbf8..1c8d029 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6955,6 +6955,9 @@ enum { > #define ECOBUS _MMIO(0xa180) > #define FORCEWAKE_MT_ENABLE (1<<5) > #define VLV_SPAREG2H _MMIO(0xA194) > +#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0) > +#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) > +#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) > > #define GTFIFODBG _MMIO(0x120000) > #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) --------------7453140A10623E7A6E0A2EAF Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 7bit

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>


On 6/27/2016 8:10 PM, akash.goel@intel.com wrote:
From: Akash Goel <akash.goel@intel.com>

Updated the i915_drpc_info debugfs with coarse power gating & forcewake
info for Gen9.

v2: Change all IS_GEN9() by gen >= 9 (Damien)

v3: Rebase

Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 21 ++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h     |  3 +++
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f664884..5185e02 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1588,6 +1588,7 @@ static int gen6_drpc_info(struct seq_file *m)
 	struct drm_device *dev = node->minor->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
+	u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
 	unsigned forcewake_count;
 	int count = 0, ret;
 
@@ -1615,6 +1616,10 @@ static int gen6_drpc_info(struct seq_file *m)
 
 	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
 	rcctl1 = I915_READ(GEN6_RC_CONTROL);
+	if (INTEL_INFO(dev)->gen >= 9) {
+		gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
+		gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
+	}
 	mutex_unlock(&dev->struct_mutex);
 	mutex_lock(&dev_priv->rps.hw_lock);
 	sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
@@ -1633,6 +1638,12 @@ static int gen6_drpc_info(struct seq_file *m)
 		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
 	seq_printf(m, "RC6 Enabled: %s\n",
 		   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+	if (INTEL_INFO(dev)->gen >= 9) {
+		seq_printf(m, "Render Well Gating Enabled: %s\n",
+			yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
+		seq_printf(m, "Media Well Gating Enabled: %s\n",
+			yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
+	}
 	seq_printf(m, "Deep RC6 Enabled: %s\n",
 		   yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
 	seq_printf(m, "Deepest RC6 Enabled: %s\n",
@@ -1661,6 +1672,14 @@ static int gen6_drpc_info(struct seq_file *m)
 
 	seq_printf(m, "Core Power Down: %s\n",
 		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
+	if (INTEL_INFO(dev)->gen >= 9) {
+		seq_printf(m, "Render Power Well: %s\n",
+			(gen9_powergate_status &
+			 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+		seq_printf(m, "Media Power Well: %s\n",
+			(gen9_powergate_status &
+			 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+	}
 
 	/* Not exactly sure what this is */
 	seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
@@ -1678,7 +1697,7 @@ static int gen6_drpc_info(struct seq_file *m)
 		   GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
 	seq_printf(m, "RC6++ voltage: %dmV\n",
 		   GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
-	return 0;
+	return i915_forcewake_domains(m, NULL);
 }
 
 static int i915_drpc_info(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c6bfbf8..1c8d029 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6955,6 +6955,9 @@ enum {
 #define  ECOBUS					_MMIO(0xa180)
 #define    FORCEWAKE_MT_ENABLE			(1<<5)
 #define  VLV_SPAREG2H				_MMIO(0xA194)
+#define  GEN9_PWRGT_DOMAIN_STATUS		_MMIO(0xA2A0)
+#define   GEN9_PWRGT_MEDIA_STATUS_MASK		(1 << 0)
+#define   GEN9_PWRGT_RENDER_STATUS_MASK		(1 << 1)
 
 #define  GTFIFODBG				_MMIO(0x120000)
 #define    GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV	(0x1f << 20)

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