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* [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.
@ 2017-10-04  0:41 Anusha Srivatsa
  2017-10-04  0:41 ` [PATCH 2/2] drm/i915/huc: Add HuC " Anusha Srivatsa
                   ` (3 more replies)
  0 siblings, 4 replies; 20+ messages in thread
From: Anusha Srivatsa @ 2017-10-04  0:41 UTC (permalink / raw)
  To: intel-gfx; +Cc: Sujaritha Sundaresan, Daniel Vetter

Calculate the time that GuC takes to load using
jiffies. This information could be very useful in
determining if GuC is taking unreasonably long time
to load in a certain platforms.

v2: Calculate time before logs are collected.
Move the guc_load_time variable as a part of
intel_uc_fw struct. Store only final result
which is to be exported to debugfs. (Michal)
Add the load time in the print message as well.

v3: Remove debugfs entry. Remove local variable
guc_finish_load. (Daniel, Tvrtko)

v4: Use ktime_get() instead of jiffies. Use DRM_NOTE
if time taken to load is more than the threshold. On
load times within acceptable range, use DRM_DEBUG_DRIVER
(Tvrtko)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko ursulin <tvrtko.ursulin@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 10 +++++++++-
 drivers/gpu/drm/i915/intel_uc.h         |  1 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index c9e25be..a0b562c 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -199,6 +199,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 	struct sg_table *sg = vma->pages;
 	u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
 	int i, ret = 0;
+	ktime_t start_load;
 
 	/* where RSA signature starts */
 	offset = guc_fw->rsa_offset;
@@ -225,6 +226,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 
 	/* Finally start the DMA */
+	start_load = ktime_get();
 	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 
 	/*
@@ -237,13 +239,17 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 	 */
 	ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
 
+	guc_fw->load_time = ktime_ms_delta(ktime_get(), start_load);
+
 	DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 			I915_READ(DMA_CTRL), status);
 
 	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 		DRM_ERROR("GuC firmware signature verification failed\n");
 		ret = -ENOEXEC;
-	}
+	} else if (guc_fw->load_time > 20)
+		DRM_NOTE("Time taken to load GuC is more than the acceptable \
+			 threshold\n");
 
 	DRM_DEBUG_DRIVER("returning %d\n", ret);
 
@@ -373,6 +379,8 @@ int intel_guc_init_hw(struct intel_guc *guc)
 		 guc->fw.path,
 		 guc->fw.major_ver_found, guc->fw.minor_ver_found);
 
+	DRM_DEBUG_DRIVER("GuC is loaded in: %lld ms\n",guc->fw.load_time);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 6966349..65b9674 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -136,6 +136,7 @@ struct intel_uc_fw {
 	uint32_t rsa_offset;
 	uint32_t ucode_size;
 	uint32_t ucode_offset;
+	unsigned long long load_time;
 };
 
 struct intel_guc_log {
-- 
2.7.4

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log.
@ 2017-11-01  0:11 Anusha Srivatsa
  2017-11-01 13:14 ` Michal Wajdeczko
  2017-11-01 13:38 ` David Weinehall
  0 siblings, 2 replies; 20+ messages in thread
From: Anusha Srivatsa @ 2017-11-01  0:11 UTC (permalink / raw)
  To: intel-gfx; +Cc: Sujaritha Sundaresan, Daniel Vetter

Calculate the time that GuC takes to load using
jiffies. This information could be very useful in
determining if GuC is taking unreasonably long time
to load in a certain platforms.

v2: Calculate time before logs are collected.
Move the guc_load_time variable as a part of
intel_uc_fw struct. Store only final result
which is to be exported to debugfs. (Michal)
Add the load time in the print message as well.

v3: Remove debugfs entry. Remove local variable
guc_finish_load. (Daniel, Tvrtko)

v4: Use ktime_get() instead of jiffies. Use DRM_NOTE
if time taken to load is more than the threshold. On
load times within acceptable range, use DRM_DEBUG_DRIVER
(Tvrtko)

v5: Rebased. Do not expose the load time variable in a global
struct (Tvrtko, Joonas)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index ef67a36..4ce9a30 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -133,7 +133,8 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 	unsigned long offset;
 	struct sg_table *sg = vma->pages;
 	u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT];
-	int i, ret = 0;
+	int i, ret = 0, load_time;
+	ktime_t start_load;
 
 	/* where RSA signature starts */
 	offset = guc_fw->rsa_offset;
@@ -160,6 +161,7 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 
 	/* Finally start the DMA */
+	start_load = ktime_get();
 	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
 
 	/*
@@ -172,13 +174,18 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv,
 	 */
 	ret = wait_for(guc_ucode_response(dev_priv, &status), 100);
 
+	load_time = ktime_ms_delta(ktime_get(), start_load);
+
 	DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
 			I915_READ(DMA_CTRL), status);
 
 	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
 		DRM_ERROR("GuC firmware signature verification failed\n");
 		ret = -ENOEXEC;
-	}
+	} else if (load_time > 20)
+		DRM_NOTE("GuC load takes more than acceptable threshold\n");
+	else
+		DRM_DEBUG_DRIVER("GuC loaded in %d ms\n", load_time);
 
 	DRM_DEBUG_DRIVER("returning %d\n", ret);
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 20+ messages in thread
[parent not found: <1505954668-2748-1-git-send-email-anusha.srivatsa@intel.com>]

end of thread, other threads:[~2017-11-02 20:33 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-10-04  0:41 [PATCH 1/2] drm/i915/guc: Add GuC Load time to dmesg log Anusha Srivatsa
2017-10-04  0:41 ` [PATCH 2/2] drm/i915/huc: Add HuC " Anusha Srivatsa
2017-10-04  1:05 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Add GuC " Patchwork
2017-10-04  3:02 ` ✓ Fi.CI.IGT: " Patchwork
2017-10-04  8:16 ` [PATCH 1/2] " Tvrtko Ursulin
2017-10-04 12:51   ` Joonas Lahtinen
2017-10-06  0:56     ` Srivatsa, Anusha
2017-10-06  6:29       ` Joonas Lahtinen
2017-10-09 17:24         ` Srivatsa, Anusha
2017-10-06  0:41   ` Srivatsa, Anusha
  -- strict thread matches above, loose matches on Subject: below --
2017-11-01  0:11 Anusha Srivatsa
2017-11-01 13:14 ` Michal Wajdeczko
2017-11-01 13:24   ` Chris Wilson
2017-11-02 20:28     ` Anusha Srivatsa
2017-11-02 20:33       ` Chris Wilson
2017-11-02 18:04   ` Anusha Srivatsa
2017-11-01 13:38 ` David Weinehall
2017-11-01 13:48   ` Chris Wilson
     [not found] <1505954668-2748-1-git-send-email-anusha.srivatsa@intel.com>
     [not found] ` <9108028B3EB68E4CA5158371AB76E601633C4616@IRSMSX106.ger.corp.intel.com>
2017-09-22 20:12   ` Srivatsa, Anusha
2017-09-25  8:31     ` Tvrtko Ursulin

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