From mboxrd@z Thu Jan  1 00:00:00 1970
From: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Subject: Re: [PATCH 1/2] rendercopy/bdw: Enable hw-generated
	binding tables
Date: Wed, 07 May 2014 23:59:23 +0300
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To: Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
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On Wednesday, May 07, 2014 02:49:31 PM Ville Syrj=E4l=E4 wrote:
> I quickly cobbled together a hsw version of this and gave it a whirl on
> one machine. Seems to work just fine here, and no lockups when switching
> between hw and sw binding tables. Did you get the lockups on hsw even
> with rendercopy?
> =

> Here's my hsw version:
> =

> =

> +static void
> +gen7_hw_binding_table(struct intel_batchbuffer *batch, bool enable)
> +{
> +	if (!enable) {
> +		OUT_BATCH(MI_RS_CONTROL | 0x0);
> +
> +		OUT_BATCH(HSW_3DSTATE_BINDING_TABLE_POOL_ALLOC | (3 - 2));
> +		/* binding table pool base address */

This bit I missed and the source of my troubles for the past few months.

> +		OUT_BATCH(3 << 5);

Yep, I confirm toggling on HSW does work quite well now. I'll now update th=
e =

patches to include HSW path on the kernel. I also take back my previous =

statement that RS is broken on HSW! :)

Thanks a lot Ville!


> +		/* Upper bound */
> +		OUT_BATCH(0);
> +
> +		OUT_BATCH(GEN7_PIPE_CONTROL | (4 - 2));
> +		OUT_BATCH(GEN7_PIPE_CONTROL_CS_STALL |
> GEN7_PIPE_CONTROL_STALL_AT_SCOREBOARD); +		OUT_BATCH(0);
> +		OUT_BATCH(0);
> +
> +		OUT_BATCH(GEN7_PIPE_CONTROL | (4 - 2));
> +		OUT_BATCH(GEN7_PIPE_CONTROL_SC_INVALIDATE);
> +		OUT_BATCH(0);
> +		OUT_BATCH(0);
> +
> +		return;
> +        }