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X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Feb 2024 06:27:31.5022 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2Jp7mTzn5uaq23yNPu8JKCYmygQulTzusii5z6Qs2XEvggZoWfhXjPn7skPGLx8talDUWMQ/O1FV2Gk7qNhewaoUCAo0u2RPKc1w97Nb/Ds= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR11MB5395 X-OriginatorOrg: intel.com X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 2/16/2024 7:50 PM, Mitul Golani wrote: > Compute vrr_vsync_start/end which sets the position > for hardware to send the Vsync at a fixed position > relative to the end of the Vblank. > > --v2: > - Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit) > - Update bit fields of VRR_VSYNC_START/END.(Ankit) > > Signed-off-by: Mitul Golani > --- > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_vrr.c | 7 +++++++ > drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ > 3 files changed, 19 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index a6991bc3f07b..015ed846b896 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1414,6 +1414,7 @@ struct intel_crtc_state { > bool enable, in_range; > u8 pipeline_full; > u16 flipline, vmin, vmax, guardband; > + u32 vsync_end, vsync_start; > } vrr; > > /* Stream Splitter for eDP MSO */ > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 5d905f932cb4..2fa0004d00c7 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -149,6 +149,13 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > > crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; > > + crtc_state->vrr.vsync_start = > + (crtc_state->hw.adjusted_mode.crtc_vtotal - > + VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start)); > + crtc_state->vrr.vsync_end = > + (crtc_state->hw.adjusted_mode.crtc_vtotal - > + (VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16)); > + > /* > * For XE_LPD+, we use guardband and pipeline override > * is deprecated. > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c02ea07af4c2..f73e95b18819 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1955,6 +1955,10 @@ > #define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) > #define VSYNC_START_MASK REG_GENMASK(15, 0) > #define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) > +#define VSYNC_END_MASK REG_GENMASK(31, 16) > +#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) > +#define VSYNC_START_MASK REG_GENMASK(15, 0) > +#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) I think this is typo, we really dont need to touch these. > #define _TRANS_EXITLINE_A 0x60018 > #define _PIPEASRC 0x6001c > #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) > @@ -2007,7 +2011,9 @@ > #define _TRANS_VRR_CTL_B 0x61420 > #define _TRANS_VRR_CTL_C 0x62420 > #define _TRANS_VRR_CTL_D 0x63420 > +#define _TRANS_VRR_VSYNC_A 0x60078 > #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) > +#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A) > #define VRR_CTL_VRR_ENABLE REG_BIT(31) > #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) > #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) > @@ -2087,6 +2093,11 @@ > #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) > #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) > > +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) > +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) > +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) > +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) Here too, we need to use the correct VRR_VSYNC_STAR/END_MASK Regards, Ankit > + > #define _TRANS_PUSH_A 0x60A70 > #define _TRANS_PUSH_B 0x61A70 > #define _TRANS_PUSH_C 0x62A70