From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75284C4708A for ; Thu, 27 May 2021 17:17:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2DE11610CC for ; Thu, 27 May 2021 17:17:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2DE11610CC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 537D76F487; Thu, 27 May 2021 17:17:23 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id E34A86F486; Thu, 27 May 2021 17:17:21 +0000 (UTC) IronPort-SDR: j7ovlxpTWyTLPyHfAjefAyJghB1i/QvMFuxFs4CDACBhRRkzj9T3oHN6YHJ4XldrC5BWw5PdoU 52LeLqtaGRNw== X-IronPort-AV: E=McAfee;i="6200,9189,9997"; a="202554796" X-IronPort-AV: E=Sophos;i="5.83,228,1616482800"; d="scan'208";a="202554796" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2021 10:17:21 -0700 IronPort-SDR: 4Yv2RyOYNqjU3JSMdAmNxHwzobo335NxT7cI0MmfEyBqZTy+/AWYlnZqpDWdyqoAxSdSOCQJNd SVryNUIamAyw== X-IronPort-AV: E=Sophos;i="5.83,228,1616482800"; d="scan'208";a="477577832" Received: from johnharr-mobl1.amr.corp.intel.com (HELO [10.209.116.237]) ([10.209.116.237]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2021 10:17:20 -0700 To: Matthew Brost , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org References: <20210526064237.77853-1-matthew.brost@intel.com> <20210526064237.77853-7-matthew.brost@intel.com> From: John Harrison Message-ID: <3b1eadf8-b043-365f-ada9-3a87901e8159@intel.com> Date: Thu, 27 May 2021 10:17:20 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.2 MIME-Version: 1.0 In-Reply-To: <20210526064237.77853-7-matthew.brost@intel.com> Content-Language: en-GB Subject: Re: [Intel-gfx] [PATCH 06/18] drm/i915/guc: Drop guc->interrupts.enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 5/25/2021 23:42, Matthew Brost wrote: > Drop the variable guc->interrupts.enabled as this variable is just > leading to bugs creeping into the code. > > e.g. A full GPU reset disables the GuC interrupts but forgot to clear > guc->interrupts.enabled, guc->interrupts.enabled being true suppresses > interrupts from getting re-enabled and now we are broken. > > It is harmless to enable interrupt while already enabled so let's just > delete this variable to avoid bugs like this going forward. Is it worth leaving the enabled flag in place but only using it to trip a WARN to catch such cases in a less catastrophic manner? Or are there valid reasons for calling enable when already enabled? Either way, it seems like a plausible change and CI is happy with it, so: Reviewed-by: John Harrison John. > Signed-off-by: Matthew Brost > --- > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 27 +++++++++----------------- > drivers/gpu/drm/i915/gt/uc/intel_guc.h | 1 - > 2 files changed, 9 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index ab2c8fe8cdfa..18da9ed15728 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -96,12 +96,9 @@ static void gen9_enable_guc_interrupts(struct intel_guc *guc) > assert_rpm_wakelock_held(>->i915->runtime_pm); > > spin_lock_irq(>->irq_lock); > - if (!guc->interrupts.enabled) { > - WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) & > - gt->pm_guc_events); > - guc->interrupts.enabled = true; > - gen6_gt_pm_enable_irq(gt, gt->pm_guc_events); > - } > + WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) & > + gt->pm_guc_events); > + gen6_gt_pm_enable_irq(gt, gt->pm_guc_events); > spin_unlock_irq(>->irq_lock); > } > > @@ -112,7 +109,6 @@ static void gen9_disable_guc_interrupts(struct intel_guc *guc) > assert_rpm_wakelock_held(>->i915->runtime_pm); > > spin_lock_irq(>->irq_lock); > - guc->interrupts.enabled = false; > > gen6_gt_pm_disable_irq(gt, gt->pm_guc_events); > > @@ -134,18 +130,14 @@ static void gen11_reset_guc_interrupts(struct intel_guc *guc) > static void gen11_enable_guc_interrupts(struct intel_guc *guc) > { > struct intel_gt *gt = guc_to_gt(guc); > + u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); > > spin_lock_irq(>->irq_lock); > - if (!guc->interrupts.enabled) { > - u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); > - > - WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC)); > - intel_uncore_write(gt->uncore, > - GEN11_GUC_SG_INTR_ENABLE, events); > - intel_uncore_write(gt->uncore, > - GEN11_GUC_SG_INTR_MASK, ~events); > - guc->interrupts.enabled = true; > - } > + WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC)); > + intel_uncore_write(gt->uncore, > + GEN11_GUC_SG_INTR_ENABLE, events); > + intel_uncore_write(gt->uncore, > + GEN11_GUC_SG_INTR_MASK, ~events); > spin_unlock_irq(>->irq_lock); > } > > @@ -154,7 +146,6 @@ static void gen11_disable_guc_interrupts(struct intel_guc *guc) > struct intel_gt *gt = guc_to_gt(guc); > > spin_lock_irq(>->irq_lock); > - guc->interrupts.enabled = false; > > intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0); > intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0); > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h > index c20f3839de12..4abc59f6f3cd 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h > @@ -33,7 +33,6 @@ struct intel_guc { > unsigned int msg_enabled_mask; > > struct { > - bool enabled; > void (*reset)(struct intel_guc *guc); > void (*enable)(struct intel_guc *guc); > void (*disable)(struct intel_guc *guc); _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx