[PATCH v4 0/3] drm/i915/display: Enable system cache support for FBC

[PATCH v4 0/3] drm/i915/display: Enable system cache support for FBC

[Vinod Govindapillai]

Use system cacheability configuration register to assign a reserved
area in system cache for FBC

v4: included the sys cache workaroung patch + review commets changes

Vinod Govindapillai (3):
  drm/i915/display: Use a sub-struct for fbc operations in intel_display
  drm/i915/xe3p_lpd: Enable display use of system cache for FBC
  drm/i915/fbc: Apply Wa_14025769978

 drivers/gpu/drm/i915/display/i9xx_plane.c     |  2 +-
 .../gpu/drm/i915/display/intel_display_core.h | 11 ++-
 .../drm/i915/display/intel_display_device.h   |  1 +
 .../gpu/drm/i915/display/intel_display_wa.c   |  2 +
 .../gpu/drm/i915/display/intel_display_wa.h   |  1 +
 drivers/gpu/drm/i915/display/intel_fbc.c      | 98 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
 .../drm/i915/display/skl_universal_plane.c    |  2 +-
 8 files changed, 121 insertions(+), 6 deletions(-)

-- 
2.43.0

[PATCH v4 1/3] drm/i915/display: Use a sub-struct for fbc operations in intel_display

[Vinod Govindapillai]

As FBC can utilize the system cache in xe3p_lpd onwards, we need
a provision to track which fbc instance is utilizing this cache.
A sub-struct at intel_display level to group all the fbc ops will
make fbc handling much easier. Introduce a fbc sub-struct and move
the fbc instance array into that.

v2: changes in commit message

Suggested-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_plane.c          | 2 +-
 drivers/gpu/drm/i915/display/intel_display_core.h  | 5 ++++-
 drivers/gpu/drm/i915/display/intel_fbc.c           | 6 +++---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
 4 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 51ccc6bd5f21..2c40bc632b3d 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -134,7 +134,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display,
 					enum i9xx_plane_id i9xx_plane)
 {
 	if (i9xx_plane_has_fbc(display, i9xx_plane))
-		return display->fbc[INTEL_FBC_A];
+		return display->fbc.instances[INTEL_FBC_A];
 	else
 		return NULL;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 9b36654b593d..58325f530670 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -398,6 +398,10 @@ struct intel_display {
 		const struct dram_info *info;
 	} dram;
 
+	struct {
+		struct intel_fbc *instances[I915_MAX_FBCS];
+	} fbc;
+
 	struct {
 		/* list of fbdev register on this device */
 		struct intel_fbdev *fbdev;
@@ -615,7 +619,6 @@ struct intel_display {
 	struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
 	struct intel_audio audio;
 	struct intel_dpll_global dpll;
-	struct intel_fbc *fbc[I915_MAX_FBCS];
 	struct intel_frontbuffer_tracking fb_tracking;
 	struct intel_hotplug hotplug;
 	struct intel_opregion *opregion;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d9cab25d414a..dcdfcff80de3 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -69,7 +69,7 @@
 
 #define for_each_intel_fbc(__display, __fbc, __fbc_id) \
 	for_each_fbc_id((__display), (__fbc_id)) \
-		for_each_if((__fbc) = (__display)->fbc[(__fbc_id)])
+		for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
 
 struct intel_fbc_funcs {
 	void (*activate)(struct intel_fbc *fbc);
@@ -2211,7 +2211,7 @@ void intel_fbc_init(struct intel_display *display)
 		    display->params.enable_fbc);
 
 	for_each_fbc_id(display, fbc_id)
-		display->fbc[fbc_id] = intel_fbc_create(display, fbc_id);
+		display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
 }
 
 /**
@@ -2330,7 +2330,7 @@ void intel_fbc_debugfs_register(struct intel_display *display)
 {
 	struct intel_fbc *fbc;
 
-	fbc = display->fbc[INTEL_FBC_A];
+	fbc = display->fbc.instances[INTEL_FBC_A];
 	if (fbc)
 		intel_fbc_debugfs_add(fbc, display->drm->debugfs_root);
 }
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 89c8003ccfe7..48af74963e74 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2444,7 +2444,7 @@ static struct intel_fbc *skl_plane_fbc(struct intel_display *display,
 	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
 
 	if (skl_plane_has_fbc(display, fbc_id, plane_id))
-		return display->fbc[fbc_id];
+		return display->fbc.instances[fbc_id];
 	else
 		return NULL;
 }
-- 
2.43.0

[PATCH v4 2/3] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Vinod Govindapillai]

One of the FBC instances can utilize the reserved area of SoC
level cache for the fbc transactions to benefit reduced memory
system power especially in idle scenarios. Reserved area of the
system cache can be assigned to an fbc instance by configuring
the cacheability configuration register with offset of the
compressed frame buffer in stolen memoty of that fbc. There is
a limit to this reserved area which is programmable and for
xe3p_lpd the limit is defined as 2MB.

v2: - better to track fbc sys cache usage from intel_display level,
      sanitize the cacheability config register on probe (Matt)
    - limit this for integrated graphics solutions, confirmed that
      no default value set for cache range by hw (Gustavo)

v3: - changes related to the use of fbc substruct in intel_display
    - use intel_de_write() instead of intel_rmw() by hardcoding the
      default value fields

v4: - protect sys cache config accesses, sys cache usage status in
      debugfs per fbc instance (Jani)

Bspec: 68881, 74722
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  6 ++
 .../drm/i915/display/intel_display_device.h   |  1 +
 drivers/gpu/drm/i915/display/intel_fbc.c      | 86 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 +++
 4 files changed, 103 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 58325f530670..3e4bde7fa205 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -400,6 +400,12 @@ struct intel_display {
 
 	struct {
 		struct intel_fbc *instances[I915_MAX_FBCS];
+
+		/* xe3p_lpd+: FBC instance utilizing the system cache */
+		struct sys_cache_cfg {
+			struct mutex lock;
+			enum intel_fbc_id id;
+		} sys_cache;
 	} fbc;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index b559ef43d547..b74cb69ccc85 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -173,6 +173,7 @@ struct intel_display_platforms {
 #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
 #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
 #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
+#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
 #define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
 #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >= 3)
 #define HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index dcdfcff80de3..85978196b607 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -71,6 +71,8 @@
 	for_each_fbc_id((__display), (__fbc_id)) \
 		for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
 
+#define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
+
 struct intel_fbc_funcs {
 	void (*activate)(struct intel_fbc *fbc);
 	void (*deactivate)(struct intel_fbc *fbc);
@@ -941,6 +943,69 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
 		fbc_compressor_clkgate_disable_wa(fbc, true);
 }
 
+static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg,
+					enum intel_fbc_id id)
+{
+	if (!HAS_FBC_SYS_CACHE(display))
+		return;
+
+	lockdep_assert_held(&display->fbc.sys_cache.lock);
+
+	/* Cache read enable is set by default */
+	reg |= FBC_SYS_CACHE_READ_ENABLE;
+
+	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg);
+
+	display->fbc.sys_cache.id = id;
+}
+
+static void fbc_sys_cache_disable(const struct intel_fbc *fbc)
+{
+	struct intel_display *display = fbc->display;
+	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
+
+	mutex_lock(&sys_cache->lock);
+	/* clear only if "fbc" reserved the cache */
+	if (sys_cache->id == fbc->id)
+		fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE);
+	mutex_unlock(&sys_cache->lock);
+}
+
+static int fbc_sys_cache_limit(struct intel_display *display)
+{
+	/* Default 2MB for xe3p_lpd */
+	if (DISPLAY_VER(display) == 35)
+		return 2 * 1024 * 1024;
+
+	return 0;
+}
+
+static void fbc_sys_cache_enable(const struct intel_fbc *fbc)
+{
+	struct intel_display *display = fbc->display;
+	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
+	int range, offset;
+	u32 cfg;
+
+	if (!HAS_FBC_SYS_CACHE(display))
+		return;
+
+	/* limit to be configured to the register in 64k byte chunks */
+	range = fbc_sys_cache_limit(display) / (64 * 1024);
+
+	/* offset to be configured to the register in 4K byte chunks */
+	offset = i915_gem_stolen_node_offset(fbc->compressed_fb) / (4 * 1024);
+
+	cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE | FBC_SYS_CACHEABLE_RANGE(range) |
+	      FBC_SYS_CACHE_START_BASE(offset);
+
+	mutex_lock(&sys_cache->lock);
+	/* update sys cache config only if sys cache is unassigned */
+	if (sys_cache->id == FBC_SYS_CACHE_ID_NONE)
+		fbc_sys_cache_update_config(display, cfg, fbc->id);
+	mutex_unlock(&sys_cache->lock);
+}
+
 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 {
 	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
@@ -967,6 +1032,11 @@ void intel_fbc_cleanup(struct intel_display *display)
 
 		kfree(fbc);
 	}
+
+	mutex_lock(&display->fbc.sys_cache.lock);
+	drm_WARN_ON(display->drm,
+		    display->fbc.sys_cache.id != FBC_SYS_CACHE_ID_NONE);
+	mutex_unlock(&display->fbc.sys_cache.lock);
 }
 
 static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
@@ -1780,6 +1850,8 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
 
 	__intel_fbc_cleanup_cfb(fbc);
 
+	fbc_sys_cache_disable(fbc);
+
 	/* wa_18038517565 Enable DPFC clock gating after FBC disable */
 	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
 		fbc_compressor_clkgate_disable_wa(fbc, false);
@@ -1972,6 +2044,8 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
 
 	intel_fbc_program_workarounds(fbc);
 	intel_fbc_program_cfb(fbc);
+
+	fbc_sys_cache_enable(fbc);
 }
 
 /**
@@ -2212,6 +2286,10 @@ void intel_fbc_init(struct intel_display *display)
 
 	for_each_fbc_id(display, fbc_id)
 		display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
+
+	mutex_lock(&display->fbc.sys_cache.lock);
+	display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE;
+	mutex_unlock(&display->fbc.sys_cache.lock);
 }
 
 /**
@@ -2231,6 +2309,9 @@ void intel_fbc_sanitize(struct intel_display *display)
 		if (intel_fbc_hw_is_active(fbc))
 			intel_fbc_hw_deactivate(fbc);
 	}
+
+	/* Ensure the sys cache usage config is clear as well */
+	fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE);
 }
 
 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
@@ -2249,6 +2330,11 @@ static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
 		seq_puts(m, "FBC enabled\n");
 		seq_printf(m, "Compressing: %s\n",
 			   str_yes_no(intel_fbc_is_compressing(fbc)));
+
+		mutex_lock(&display->fbc.sys_cache.lock);
+		seq_printf(m, "Using system cache: %s\n",
+			   str_yes_no(display->fbc.sys_cache.id == fbc->id));
+		mutex_unlock(&display->fbc.sys_cache.lock);
 	} else {
 		seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
index b1d0161a3196..d2d889fa4bed 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -126,4 +126,14 @@
 #define   FBC_REND_NUKE			REG_BIT(2)
 #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
 
+#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
+#define   FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
+#define   FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
+#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15, 4)
+#define   FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
+#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3, 2)
+#define   FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
+#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
+#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
+
 #endif /* __INTEL_FBC_REGS__ */
-- 
2.43.0

Re: [PATCH v4 2/3] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Govindapillai, Vinod]

Hi,

Ah.. :( Looks like I forgot to git add
drivers/gpu/drm/i915/display/intel_display_driver.c while commit this
patch. This patch now miss the mutex init part.

diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 7e000ba3e08b..4f82b267b086 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -184,6 +184,7 @@ void intel_display_driver_early_probe(struct
intel_display *display)
        mutex_init(&display->wm.wm_mutex);
        mutex_init(&display->pps.mutex);
        mutex_init(&display->hdcp.hdcp_mutex);
+       mutex_init(&display->fbc.sys_cache.lock);
 
        intel_display_irq_init(display);
        intel_dkl_phy_init(display);

Will wait for comments before I update this commit with the above
change. Sorry about that.

BR
Vinod



On Thu, 2025-11-27 at 13:53 +0200, Vinod Govindapillai wrote:
> One of the FBC instances can utilize the reserved area of SoC
> level cache for the fbc transactions to benefit reduced memory
> system power especially in idle scenarios. Reserved area of the
> system cache can be assigned to an fbc instance by configuring
> the cacheability configuration register with offset of the
> compressed frame buffer in stolen memoty of that fbc. There is
> a limit to this reserved area which is programmable and for
> xe3p_lpd the limit is defined as 2MB.
> 
> v2: - better to track fbc sys cache usage from intel_display level,
>       sanitize the cacheability config register on probe (Matt)
>     - limit this for integrated graphics solutions, confirmed that
>       no default value set for cache range by hw (Gustavo)
> 
> v3: - changes related to the use of fbc substruct in intel_display
>     - use intel_de_write() instead of intel_rmw() by hardcoding the
>       default value fields
> 
> v4: - protect sys cache config accesses, sys cache usage status in
>       debugfs per fbc instance (Jani)
> 
> Bspec: 68881, 74722
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  6 ++
>  .../drm/i915/display/intel_display_device.h   |  1 +
>  drivers/gpu/drm/i915/display/intel_fbc.c      | 86
> +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 +++
>  4 files changed, 103 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 58325f530670..3e4bde7fa205 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -400,6 +400,12 @@ struct intel_display {
>  
>  	struct {
>  		struct intel_fbc *instances[I915_MAX_FBCS];
> +
> +		/* xe3p_lpd+: FBC instance utilizing the system
> cache */
> +		struct sys_cache_cfg {
> +			struct mutex lock;
> +			enum intel_fbc_id id;
> +		} sys_cache;
>  	} fbc;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index b559ef43d547..b74cb69ccc85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -173,6 +173,7 @@ struct intel_display_platforms {
>  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >=
> 12 && HAS_DSC(__display))
>  #define
> HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >=
> 30)
> +#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >=
> 35 && !(__display)->platform.dgfx)
>  #define
> HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
>  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >=
> 3)
>  #define
> HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index dcdfcff80de3..85978196b607 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -71,6 +71,8 @@
>  	for_each_fbc_id((__display), (__fbc_id)) \
>  		for_each_if((__fbc) = (__display)-
> >fbc.instances[(__fbc_id)])
>  
> +#define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
> +
>  struct intel_fbc_funcs {
>  	void (*activate)(struct intel_fbc *fbc);
>  	void (*deactivate)(struct intel_fbc *fbc);
> @@ -941,6 +943,69 @@ static void intel_fbc_program_workarounds(struct
> intel_fbc *fbc)
>  		fbc_compressor_clkgate_disable_wa(fbc, true);
>  }
>  
> +static void fbc_sys_cache_update_config(struct intel_display
> *display, u32 reg,
> +					enum intel_fbc_id id)
> +{
> +	if (!HAS_FBC_SYS_CACHE(display))
> +		return;
> +
> +	lockdep_assert_held(&display->fbc.sys_cache.lock);
> +
> +	/* Cache read enable is set by default */
> +	reg |= FBC_SYS_CACHE_READ_ENABLE;
> +
> +	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG,
> reg);
> +
> +	display->fbc.sys_cache.id = id;
> +}
> +
> +static void fbc_sys_cache_disable(const struct intel_fbc *fbc)
> +{
> +	struct intel_display *display = fbc->display;
> +	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
> +
> +	mutex_lock(&sys_cache->lock);
> +	/* clear only if "fbc" reserved the cache */
> +	if (sys_cache->id == fbc->id)
> +		fbc_sys_cache_update_config(display, 0,
> FBC_SYS_CACHE_ID_NONE);
> +	mutex_unlock(&sys_cache->lock);
> +}
> +
> +static int fbc_sys_cache_limit(struct intel_display *display)
> +{
> +	/* Default 2MB for xe3p_lpd */
> +	if (DISPLAY_VER(display) == 35)
> +		return 2 * 1024 * 1024;
> +
> +	return 0;
> +}
> +
> +static void fbc_sys_cache_enable(const struct intel_fbc *fbc)
> +{
> +	struct intel_display *display = fbc->display;
> +	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
> +	int range, offset;
> +	u32 cfg;
> +
> +	if (!HAS_FBC_SYS_CACHE(display))
> +		return;
> +
> +	/* limit to be configured to the register in 64k byte chunks
> */
> +	range = fbc_sys_cache_limit(display) / (64 * 1024);
> +
> +	/* offset to be configured to the register in 4K byte chunks
> */
> +	offset = i915_gem_stolen_node_offset(fbc->compressed_fb) /
> (4 * 1024);
> +
> +	cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
> FBC_SYS_CACHEABLE_RANGE(range) |
> +	      FBC_SYS_CACHE_START_BASE(offset);
> +
> +	mutex_lock(&sys_cache->lock);
> +	/* update sys cache config only if sys cache is unassigned
> */
> +	if (sys_cache->id == FBC_SYS_CACHE_ID_NONE)
> +		fbc_sys_cache_update_config(display, cfg, fbc->id);
> +	mutex_unlock(&sys_cache->lock);
> +}
> +
>  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>  {
>  	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> @@ -967,6 +1032,11 @@ void intel_fbc_cleanup(struct intel_display
> *display)
>  
>  		kfree(fbc);
>  	}
> +
> +	mutex_lock(&display->fbc.sys_cache.lock);
> +	drm_WARN_ON(display->drm,
> +		    display->fbc.sys_cache.id !=
> FBC_SYS_CACHE_ID_NONE);
> +	mutex_unlock(&display->fbc.sys_cache.lock);
>  }
>  
>  static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state
> *plane_state)
> @@ -1780,6 +1850,8 @@ static void __intel_fbc_disable(struct
> intel_fbc *fbc)
>  
>  	__intel_fbc_cleanup_cfb(fbc);
>  
> +	fbc_sys_cache_disable(fbc);
> +
>  	/* wa_18038517565 Enable DPFC clock gating after FBC disable
> */
>  	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
>  		fbc_compressor_clkgate_disable_wa(fbc, false);
> @@ -1972,6 +2044,8 @@ static void __intel_fbc_enable(struct
> intel_atomic_state *state,
>  
>  	intel_fbc_program_workarounds(fbc);
>  	intel_fbc_program_cfb(fbc);
> +
> +	fbc_sys_cache_enable(fbc);
>  }
>  
>  /**
> @@ -2212,6 +2286,10 @@ void intel_fbc_init(struct intel_display
> *display)
>  
>  	for_each_fbc_id(display, fbc_id)
>  		display->fbc.instances[fbc_id] =
> intel_fbc_create(display, fbc_id);
> +
> +	mutex_lock(&display->fbc.sys_cache.lock);
> +	display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE;
> +	mutex_unlock(&display->fbc.sys_cache.lock);
>  }
>  
>  /**
> @@ -2231,6 +2309,9 @@ void intel_fbc_sanitize(struct intel_display
> *display)
>  		if (intel_fbc_hw_is_active(fbc))
>  			intel_fbc_hw_deactivate(fbc);
>  	}
> +
> +	/* Ensure the sys cache usage config is clear as well */
> +	fbc_sys_cache_update_config(display, 0,
> FBC_SYS_CACHE_ID_NONE);
>  }
>  
>  static int intel_fbc_debugfs_status_show(struct seq_file *m, void
> *unused)
> @@ -2249,6 +2330,11 @@ static int
> intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
>  		seq_puts(m, "FBC enabled\n");
>  		seq_printf(m, "Compressing: %s\n",
>  			  
> str_yes_no(intel_fbc_is_compressing(fbc)));
> +
> +		mutex_lock(&display->fbc.sys_cache.lock);
> +		seq_printf(m, "Using system cache: %s\n",
> +			   str_yes_no(display->fbc.sys_cache.id ==
> fbc->id));
> +		mutex_unlock(&display->fbc.sys_cache.lock);
>  	} else {
>  		seq_printf(m, "FBC disabled: %s\n", fbc-
> >no_fbc_reason);
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> index b1d0161a3196..d2d889fa4bed 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -126,4 +126,14 @@
>  #define   FBC_REND_NUKE			REG_BIT(2)
>  #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
>  
> +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
> +#define  
> FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
> +#define  
> FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK,(base))
> +#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15, 4)
> +#define  
> FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK,(range))
> +#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3, 2)
> +#define  
> FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
> +#define  
> FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,3)
> +#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
> +
>  #endif /* __INTEL_FBC_REGS__ */

Re: [PATCH v4 2/3] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Jani Nikula]

On Thu, 27 Nov 2025, "Govindapillai, Vinod" <vinod.govindapillai@intel.com> wrote:
> Hi,
>
> Ah.. :( Looks like I forgot to git add
> drivers/gpu/drm/i915/display/intel_display_driver.c while commit this
> patch. This patch now miss the mutex init part.

IMO the mutex init should be in intel_fbc_init() anyway.

BR,
Jani.

>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 7e000ba3e08b..4f82b267b086 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -184,6 +184,7 @@ void intel_display_driver_early_probe(struct
> intel_display *display)
>         mutex_init(&display->wm.wm_mutex);
>         mutex_init(&display->pps.mutex);
>         mutex_init(&display->hdcp.hdcp_mutex);
> +       mutex_init(&display->fbc.sys_cache.lock);
>  
>         intel_display_irq_init(display);
>         intel_dkl_phy_init(display);
>
> Will wait for comments before I update this commit with the above
> change. Sorry about that.
>
> BR
> Vinod
>
>
>
> On Thu, 2025-11-27 at 13:53 +0200, Vinod Govindapillai wrote:
>> One of the FBC instances can utilize the reserved area of SoC
>> level cache for the fbc transactions to benefit reduced memory
>> system power especially in idle scenarios. Reserved area of the
>> system cache can be assigned to an fbc instance by configuring
>> the cacheability configuration register with offset of the
>> compressed frame buffer in stolen memoty of that fbc. There is
>> a limit to this reserved area which is programmable and for
>> xe3p_lpd the limit is defined as 2MB.
>> 
>> v2: - better to track fbc sys cache usage from intel_display level,
>>       sanitize the cacheability config register on probe (Matt)
>>     - limit this for integrated graphics solutions, confirmed that
>>       no default value set for cache range by hw (Gustavo)
>> 
>> v3: - changes related to the use of fbc substruct in intel_display
>>     - use intel_de_write() instead of intel_rmw() by hardcoding the
>>       default value fields
>> 
>> v4: - protect sys cache config accesses, sys cache usage status in
>>       debugfs per fbc instance (Jani)
>> 
>> Bspec: 68881, 74722
>> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> ---
>>  .../gpu/drm/i915/display/intel_display_core.h |  6 ++
>>  .../drm/i915/display/intel_display_device.h   |  1 +
>>  drivers/gpu/drm/i915/display/intel_fbc.c      | 86
>> +++++++++++++++++++
>>  drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 +++
>>  4 files changed, 103 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 58325f530670..3e4bde7fa205 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -400,6 +400,12 @@ struct intel_display {
>>  
>>  	struct {
>>  		struct intel_fbc *instances[I915_MAX_FBCS];
>> +
>> +		/* xe3p_lpd+: FBC instance utilizing the system
>> cache */
>> +		struct sys_cache_cfg {
>> +			struct mutex lock;
>> +			enum intel_fbc_id id;
>> +		} sys_cache;
>>  	} fbc;
>>  
>>  	struct {
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
>> b/drivers/gpu/drm/i915/display/intel_display_device.h
>> index b559ef43d547..b74cb69ccc85 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>> @@ -173,6 +173,7 @@ struct intel_display_platforms {
>>  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >=
>> 12 && HAS_DSC(__display))
>>  #define
>> HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>>  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >=
>> 30)
>> +#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >=
>> 35 && !(__display)->platform.dgfx)
>>  #define
>> HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
>>  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >=
>> 3)
>>  #define
>> HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>> b/drivers/gpu/drm/i915/display/intel_fbc.c
>> index dcdfcff80de3..85978196b607 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> @@ -71,6 +71,8 @@
>>  	for_each_fbc_id((__display), (__fbc_id)) \
>>  		for_each_if((__fbc) = (__display)-
>> >fbc.instances[(__fbc_id)])
>>  
>> +#define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
>> +
>>  struct intel_fbc_funcs {
>>  	void (*activate)(struct intel_fbc *fbc);
>>  	void (*deactivate)(struct intel_fbc *fbc);
>> @@ -941,6 +943,69 @@ static void intel_fbc_program_workarounds(struct
>> intel_fbc *fbc)
>>  		fbc_compressor_clkgate_disable_wa(fbc, true);
>>  }
>>  
>> +static void fbc_sys_cache_update_config(struct intel_display
>> *display, u32 reg,
>> +					enum intel_fbc_id id)
>> +{
>> +	if (!HAS_FBC_SYS_CACHE(display))
>> +		return;
>> +
>> +	lockdep_assert_held(&display->fbc.sys_cache.lock);
>> +
>> +	/* Cache read enable is set by default */
>> +	reg |= FBC_SYS_CACHE_READ_ENABLE;
>> +
>> +	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG,
>> reg);
>> +
>> +	display->fbc.sys_cache.id = id;
>> +}
>> +
>> +static void fbc_sys_cache_disable(const struct intel_fbc *fbc)
>> +{
>> +	struct intel_display *display = fbc->display;
>> +	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
>> +
>> +	mutex_lock(&sys_cache->lock);
>> +	/* clear only if "fbc" reserved the cache */
>> +	if (sys_cache->id == fbc->id)
>> +		fbc_sys_cache_update_config(display, 0,
>> FBC_SYS_CACHE_ID_NONE);
>> +	mutex_unlock(&sys_cache->lock);
>> +}
>> +
>> +static int fbc_sys_cache_limit(struct intel_display *display)
>> +{
>> +	/* Default 2MB for xe3p_lpd */
>> +	if (DISPLAY_VER(display) == 35)
>> +		return 2 * 1024 * 1024;
>> +
>> +	return 0;
>> +}
>> +
>> +static void fbc_sys_cache_enable(const struct intel_fbc *fbc)
>> +{
>> +	struct intel_display *display = fbc->display;
>> +	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
>> +	int range, offset;
>> +	u32 cfg;
>> +
>> +	if (!HAS_FBC_SYS_CACHE(display))
>> +		return;
>> +
>> +	/* limit to be configured to the register in 64k byte chunks
>> */
>> +	range = fbc_sys_cache_limit(display) / (64 * 1024);
>> +
>> +	/* offset to be configured to the register in 4K byte chunks
>> */
>> +	offset = i915_gem_stolen_node_offset(fbc->compressed_fb) /
>> (4 * 1024);
>> +
>> +	cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
>> FBC_SYS_CACHEABLE_RANGE(range) |
>> +	      FBC_SYS_CACHE_START_BASE(offset);
>> +
>> +	mutex_lock(&sys_cache->lock);
>> +	/* update sys cache config only if sys cache is unassigned
>> */
>> +	if (sys_cache->id == FBC_SYS_CACHE_ID_NONE)
>> +		fbc_sys_cache_update_config(display, cfg, fbc->id);
>> +	mutex_unlock(&sys_cache->lock);
>> +}
>> +
>>  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>>  {
>>  	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
>> @@ -967,6 +1032,11 @@ void intel_fbc_cleanup(struct intel_display
>> *display)
>>  
>>  		kfree(fbc);
>>  	}
>> +
>> +	mutex_lock(&display->fbc.sys_cache.lock);
>> +	drm_WARN_ON(display->drm,
>> +		    display->fbc.sys_cache.id !=
>> FBC_SYS_CACHE_ID_NONE);
>> +	mutex_unlock(&display->fbc.sys_cache.lock);
>>  }
>>  
>>  static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state
>> *plane_state)
>> @@ -1780,6 +1850,8 @@ static void __intel_fbc_disable(struct
>> intel_fbc *fbc)
>>  
>>  	__intel_fbc_cleanup_cfb(fbc);
>>  
>> +	fbc_sys_cache_disable(fbc);
>> +
>>  	/* wa_18038517565 Enable DPFC clock gating after FBC disable
>> */
>>  	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
>>  		fbc_compressor_clkgate_disable_wa(fbc, false);
>> @@ -1972,6 +2044,8 @@ static void __intel_fbc_enable(struct
>> intel_atomic_state *state,
>>  
>>  	intel_fbc_program_workarounds(fbc);
>>  	intel_fbc_program_cfb(fbc);
>> +
>> +	fbc_sys_cache_enable(fbc);
>>  }
>>  
>>  /**
>> @@ -2212,6 +2286,10 @@ void intel_fbc_init(struct intel_display
>> *display)
>>  
>>  	for_each_fbc_id(display, fbc_id)
>>  		display->fbc.instances[fbc_id] =
>> intel_fbc_create(display, fbc_id);
>> +
>> +	mutex_lock(&display->fbc.sys_cache.lock);
>> +	display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE;
>> +	mutex_unlock(&display->fbc.sys_cache.lock);
>>  }
>>  
>>  /**
>> @@ -2231,6 +2309,9 @@ void intel_fbc_sanitize(struct intel_display
>> *display)
>>  		if (intel_fbc_hw_is_active(fbc))
>>  			intel_fbc_hw_deactivate(fbc);
>>  	}
>> +
>> +	/* Ensure the sys cache usage config is clear as well */
>> +	fbc_sys_cache_update_config(display, 0,
>> FBC_SYS_CACHE_ID_NONE);
>>  }
>>  
>>  static int intel_fbc_debugfs_status_show(struct seq_file *m, void
>> *unused)
>> @@ -2249,6 +2330,11 @@ static int
>> intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
>>  		seq_puts(m, "FBC enabled\n");
>>  		seq_printf(m, "Compressing: %s\n",
>>  			  
>> str_yes_no(intel_fbc_is_compressing(fbc)));
>> +
>> +		mutex_lock(&display->fbc.sys_cache.lock);
>> +		seq_printf(m, "Using system cache: %s\n",
>> +			   str_yes_no(display->fbc.sys_cache.id ==
>> fbc->id));
>> +		mutex_unlock(&display->fbc.sys_cache.lock);
>>  	} else {
>>  		seq_printf(m, "FBC disabled: %s\n", fbc-
>> >no_fbc_reason);
>>  	}
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> index b1d0161a3196..d2d889fa4bed 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> @@ -126,4 +126,14 @@
>>  #define   FBC_REND_NUKE			REG_BIT(2)
>>  #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
>>  
>> +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
>> +#define  
>> FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
>> +#define  
>> FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK,(base))
>> +#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15, 4)
>> +#define  
>> FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK,(range))
>> +#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3, 2)
>> +#define  
>> FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
>> +#define  
>> FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,3)
>> +#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
>> +
>>  #endif /* __INTEL_FBC_REGS__ */
>

-- 
Jani Nikula, Intel

Re: [PATCH v4 2/3] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Govindapillai, Vinod]

On Thu, 2025-11-27 at 15:49 +0200, Jani Nikula wrote:
> On Thu, 27 Nov 2025, "Govindapillai, Vinod"
> <vinod.govindapillai@intel.com> wrote:
> > Hi,
> > 
> > Ah.. :( Looks like I forgot to git add
> > drivers/gpu/drm/i915/display/intel_display_driver.c while commit
> > this
> > patch. This patch now miss the mutex init part.
> 
> IMO the mutex init should be in intel_fbc_init() anyway.

Okay. Thanks Jani. I will change that.

How about the rest of the changes. Are you ok with those?

BR
Vinod

> 
> BR,
> Jani.
> 
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > index 7e000ba3e08b..4f82b267b086 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > @@ -184,6 +184,7 @@ void intel_display_driver_early_probe(struct
> > intel_display *display)
> >         mutex_init(&display->wm.wm_mutex);
> >         mutex_init(&display->pps.mutex);
> >         mutex_init(&display->hdcp.hdcp_mutex);
> > +       mutex_init(&display->fbc.sys_cache.lock);
> >  
> >         intel_display_irq_init(display);
> >         intel_dkl_phy_init(display);
> > 
> > Will wait for comments before I update this commit with the above
> > change. Sorry about that.
> > 
> > BR
> > Vinod
> > 
> > 
> > 
> > On Thu, 2025-11-27 at 13:53 +0200, Vinod Govindapillai wrote:
> > > One of the FBC instances can utilize the reserved area of SoC
> > > level cache for the fbc transactions to benefit reduced memory
> > > system power especially in idle scenarios. Reserved area of the
> > > system cache can be assigned to an fbc instance by configuring
> > > the cacheability configuration register with offset of the
> > > compressed frame buffer in stolen memoty of that fbc. There is
> > > a limit to this reserved area which is programmable and for
> > > xe3p_lpd the limit is defined as 2MB.
> > > 
> > > v2: - better to track fbc sys cache usage from intel_display
> > > level,
> > >       sanitize the cacheability config register on probe (Matt)
> > >     - limit this for integrated graphics solutions, confirmed
> > > that
> > >       no default value set for cache range by hw (Gustavo)
> > > 
> > > v3: - changes related to the use of fbc substruct in
> > > intel_display
> > >     - use intel_de_write() instead of intel_rmw() by hardcoding
> > > the
> > >       default value fields
> > > 
> > > v4: - protect sys cache config accesses, sys cache usage status
> > > in
> > >       debugfs per fbc instance (Jani)
> > > 
> > > Bspec: 68881, 74722
> > > Signed-off-by: Vinod Govindapillai
> > > <vinod.govindapillai@intel.com>
> > > ---
> > >  .../gpu/drm/i915/display/intel_display_core.h |  6 ++
> > >  .../drm/i915/display/intel_display_device.h   |  1 +
> > >  drivers/gpu/drm/i915/display/intel_fbc.c      | 86
> > > +++++++++++++++++++
> > >  drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 +++
> > >  4 files changed, 103 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> > > b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > index 58325f530670..3e4bde7fa205 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > @@ -400,6 +400,12 @@ struct intel_display {
> > >  
> > >  	struct {
> > >  		struct intel_fbc *instances[I915_MAX_FBCS];
> > > +
> > > +		/* xe3p_lpd+: FBC instance utilizing the system
> > > cache */
> > > +		struct sys_cache_cfg {
> > > +			struct mutex lock;
> > > +			enum intel_fbc_id id;
> > > +		} sys_cache;
> > >  	} fbc;
> > >  
> > >  	struct {
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > > index b559ef43d547..b74cb69ccc85 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > > @@ -173,6 +173,7 @@ struct intel_display_platforms {
> > >  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display)
> > > >=
> > > 12 && HAS_DSC(__display))
> > >  #define
> > > HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)
> > > ->fbc_mask != 0)
> > >  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display)
> > > >=
> > > 30)
> > > +#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display)
> > > >=
> > > 35 && !(__display)->platform.dgfx)
> > >  #define
> > > HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)
> > > ->has_fpga_dbg)
> > >  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display)
> > > >=
> > > 3)
> > >  #define
> > > HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 ||
> > > (__display)->platform.kabylake)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index dcdfcff80de3..85978196b607 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -71,6 +71,8 @@
> > >  	for_each_fbc_id((__display), (__fbc_id)) \
> > >  		for_each_if((__fbc) = (__display)-
> > > > fbc.instances[(__fbc_id)])
> > >  
> > > +#define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
> > > +
> > >  struct intel_fbc_funcs {
> > >  	void (*activate)(struct intel_fbc *fbc);
> > >  	void (*deactivate)(struct intel_fbc *fbc);
> > > @@ -941,6 +943,69 @@ static void
> > > intel_fbc_program_workarounds(struct
> > > intel_fbc *fbc)
> > >  		fbc_compressor_clkgate_disable_wa(fbc, true);
> > >  }
> > >  
> > > +static void fbc_sys_cache_update_config(struct intel_display
> > > *display, u32 reg,
> > > +					enum intel_fbc_id id)
> > > +{
> > > +	if (!HAS_FBC_SYS_CACHE(display))
> > > +		return;
> > > +
> > > +	lockdep_assert_held(&display->fbc.sys_cache.lock);
> > > +
> > > +	/* Cache read enable is set by default */
> > > +	reg |= FBC_SYS_CACHE_READ_ENABLE;
> > > +
> > > +	intel_de_write(display,
> > > XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG,
> > > reg);
> > > +
> > > +	display->fbc.sys_cache.id = id;
> > > +}
> > > +
> > > +static void fbc_sys_cache_disable(const struct intel_fbc *fbc)
> > > +{
> > > +	struct intel_display *display = fbc->display;
> > > +	struct sys_cache_cfg *sys_cache = &display-
> > > >fbc.sys_cache;
> > > +
> > > +	mutex_lock(&sys_cache->lock);
> > > +	/* clear only if "fbc" reserved the cache */
> > > +	if (sys_cache->id == fbc->id)
> > > +		fbc_sys_cache_update_config(display, 0,
> > > FBC_SYS_CACHE_ID_NONE);
> > > +	mutex_unlock(&sys_cache->lock);
> > > +}
> > > +
> > > +static int fbc_sys_cache_limit(struct intel_display *display)
> > > +{
> > > +	/* Default 2MB for xe3p_lpd */
> > > +	if (DISPLAY_VER(display) == 35)
> > > +		return 2 * 1024 * 1024;
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static void fbc_sys_cache_enable(const struct intel_fbc *fbc)
> > > +{
> > > +	struct intel_display *display = fbc->display;
> > > +	struct sys_cache_cfg *sys_cache = &display-
> > > >fbc.sys_cache;
> > > +	int range, offset;
> > > +	u32 cfg;
> > > +
> > > +	if (!HAS_FBC_SYS_CACHE(display))
> > > +		return;
> > > +
> > > +	/* limit to be configured to the register in 64k byte
> > > chunks
> > > */
> > > +	range = fbc_sys_cache_limit(display) / (64 * 1024);
> > > +
> > > +	/* offset to be configured to the register in 4K byte
> > > chunks
> > > */
> > > +	offset = i915_gem_stolen_node_offset(fbc->compressed_fb)
> > > /
> > > (4 * 1024);
> > > +
> > > +	cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
> > > FBC_SYS_CACHEABLE_RANGE(range) |
> > > +	      FBC_SYS_CACHE_START_BASE(offset);
> > > +
> > > +	mutex_lock(&sys_cache->lock);
> > > +	/* update sys cache config only if sys cache is
> > > unassigned
> > > */
> > > +	if (sys_cache->id == FBC_SYS_CACHE_ID_NONE)
> > > +		fbc_sys_cache_update_config(display, cfg, fbc-
> > > >id);
> > > +	mutex_unlock(&sys_cache->lock);
> > > +}
> > > +
> > >  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
> > >  {
> > >  	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> > > @@ -967,6 +1032,11 @@ void intel_fbc_cleanup(struct intel_display
> > > *display)
> > >  
> > >  		kfree(fbc);
> > >  	}
> > > +
> > > +	mutex_lock(&display->fbc.sys_cache.lock);
> > > +	drm_WARN_ON(display->drm,
> > > +		    display->fbc.sys_cache.id !=
> > > FBC_SYS_CACHE_ID_NONE);
> > > +	mutex_unlock(&display->fbc.sys_cache.lock);
> > >  }
> > >  
> > >  static bool i8xx_fbc_stride_is_valid(const struct
> > > intel_plane_state
> > > *plane_state)
> > > @@ -1780,6 +1850,8 @@ static void __intel_fbc_disable(struct
> > > intel_fbc *fbc)
> > >  
> > >  	__intel_fbc_cleanup_cfb(fbc);
> > >  
> > > +	fbc_sys_cache_disable(fbc);
> > > +
> > >  	/* wa_18038517565 Enable DPFC clock gating after FBC
> > > disable
> > > */
> > >  	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
> > >  		fbc_compressor_clkgate_disable_wa(fbc, false);
> > > @@ -1972,6 +2044,8 @@ static void __intel_fbc_enable(struct
> > > intel_atomic_state *state,
> > >  
> > >  	intel_fbc_program_workarounds(fbc);
> > >  	intel_fbc_program_cfb(fbc);
> > > +
> > > +	fbc_sys_cache_enable(fbc);
> > >  }
> > >  
> > >  /**
> > > @@ -2212,6 +2286,10 @@ void intel_fbc_init(struct intel_display
> > > *display)
> > >  
> > >  	for_each_fbc_id(display, fbc_id)
> > >  		display->fbc.instances[fbc_id] =
> > > intel_fbc_create(display, fbc_id);
> > > +
> > > +	mutex_lock(&display->fbc.sys_cache.lock);
> > > +	display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE;
> > > +	mutex_unlock(&display->fbc.sys_cache.lock);
> > >  }
> > >  
> > >  /**
> > > @@ -2231,6 +2309,9 @@ void intel_fbc_sanitize(struct
> > > intel_display
> > > *display)
> > >  		if (intel_fbc_hw_is_active(fbc))
> > >  			intel_fbc_hw_deactivate(fbc);
> > >  	}
> > > +
> > > +	/* Ensure the sys cache usage config is clear as well */
> > > +	fbc_sys_cache_update_config(display, 0,
> > > FBC_SYS_CACHE_ID_NONE);
> > >  }
> > >  
> > >  static int intel_fbc_debugfs_status_show(struct seq_file *m,
> > > void
> > > *unused)
> > > @@ -2249,6 +2330,11 @@ static int
> > > intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
> > >  		seq_puts(m, "FBC enabled\n");
> > >  		seq_printf(m, "Compressing: %s\n",
> > >  			  
> > > str_yes_no(intel_fbc_is_compressing(fbc)));
> > > +
> > > +		mutex_lock(&display->fbc.sys_cache.lock);
> > > +		seq_printf(m, "Using system cache: %s\n",
> > > +			   str_yes_no(display->fbc.sys_cache.id
> > > ==
> > > fbc->id));
> > > +		mutex_unlock(&display->fbc.sys_cache.lock);
> > >  	} else {
> > >  		seq_printf(m, "FBC disabled: %s\n", fbc-
> > > > no_fbc_reason);
> > >  	}
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > index b1d0161a3196..d2d889fa4bed 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > > @@ -126,4 +126,14 @@
> > >  #define   FBC_REND_NUKE			REG_BIT(2)
> > >  #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
> > >  
> > > +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
> > > +#define  
> > > FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
> > > +#define  
> > > FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_STA
> > > RT_BASE_MASK,(base))
> > > +#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15,
> > > 4)
> > > +#define  
> > > FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE
> > > _RANGE_MASK,(range))
> > > +#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3,
> > > 2)
> > > +#define  
> > > FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_C
> > > ACHE_TAG_MASK, 0)
> > > +#define  
> > > FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG
> > > _MASK,3)
> > > +#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
> > > +
> > >  #endif /* __INTEL_FBC_REGS__ */
> > 
> 

[PATCH v5 2/3] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Vinod Govindapillai]

One of the FBC instances can utilize the reserved area of SoC
level cache for the fbc transactions to benefit reduced memory
system power especially in idle scenarios. Reserved area of the
system cache can be assigned to an fbc instance by configuring
the cacheability configuration register with offset of the
compressed frame buffer in stolen memoty of that fbc. There is
a limit to this reserved area which is programmable and for
xe3p_lpd the limit is defined as 2MB.

v2: - better to track fbc sys cache usage from intel_display level,
      sanitize the cacheability config register on probe (Matt)
    - limit this for integrated graphics solutions, confirmed that
      no default value set for cache range by hw (Gustavo)

v3: - changes related to the use of fbc substruct in intel_display
    - use intel_de_write() instead of intel_rmw() by hardcoding the
      default value fields

v4: - protect sys cache config accesses, sys cache usage status in
      debugfs per fbc instance (Jani)

v5: - mutex_init and missing mutex_lock in sanitize call

Bspec: 68881, 74722
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  7 ++
 .../drm/i915/display/intel_display_device.h   |  1 +
 drivers/gpu/drm/i915/display/intel_fbc.c      | 87 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 +++
 4 files changed, 105 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 58325f530670..0a1744b3b440 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -400,6 +400,13 @@ struct intel_display {
 
 	struct {
 		struct intel_fbc *instances[I915_MAX_FBCS];
+
+		/* xe3p_lpd+: FBC instance utilizing the system cache */
+		struct sys_cache_cfg {
+			/* Protect concurrecnt access to system cache configuration */
+			struct mutex lock;
+			enum intel_fbc_id id;
+		} sys_cache;
 	} fbc;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index b559ef43d547..b74cb69ccc85 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -173,6 +173,7 @@ struct intel_display_platforms {
 #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
 #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
 #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
+#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
 #define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
 #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >= 3)
 #define HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index dcdfcff80de3..cebde5db3dd7 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -71,6 +71,8 @@
 	for_each_fbc_id((__display), (__fbc_id)) \
 		for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
 
+#define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
+
 struct intel_fbc_funcs {
 	void (*activate)(struct intel_fbc *fbc);
 	void (*deactivate)(struct intel_fbc *fbc);
@@ -941,6 +943,69 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
 		fbc_compressor_clkgate_disable_wa(fbc, true);
 }
 
+static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg,
+					enum intel_fbc_id id)
+{
+	if (!HAS_FBC_SYS_CACHE(display))
+		return;
+
+	lockdep_assert_held(&display->fbc.sys_cache.lock);
+
+	/* Cache read enable is set by default */
+	reg |= FBC_SYS_CACHE_READ_ENABLE;
+
+	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg);
+
+	display->fbc.sys_cache.id = id;
+}
+
+static void fbc_sys_cache_disable(const struct intel_fbc *fbc)
+{
+	struct intel_display *display = fbc->display;
+	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
+
+	mutex_lock(&sys_cache->lock);
+	/* clear only if "fbc" reserved the cache */
+	if (sys_cache->id == fbc->id)
+		fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE);
+	mutex_unlock(&sys_cache->lock);
+}
+
+static int fbc_sys_cache_limit(struct intel_display *display)
+{
+	/* Default 2MB for xe3p_lpd */
+	if (DISPLAY_VER(display) == 35)
+		return 2 * 1024 * 1024;
+
+	return 0;
+}
+
+static void fbc_sys_cache_enable(const struct intel_fbc *fbc)
+{
+	struct intel_display *display = fbc->display;
+	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
+	int range, offset;
+	u32 cfg;
+
+	if (!HAS_FBC_SYS_CACHE(display))
+		return;
+
+	/* limit to be configured to the register in 64k byte chunks */
+	range = fbc_sys_cache_limit(display) / (64 * 1024);
+
+	/* offset to be configured to the register in 4K byte chunks */
+	offset = i915_gem_stolen_node_offset(fbc->compressed_fb) / (4 * 1024);
+
+	cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE | FBC_SYS_CACHEABLE_RANGE(range) |
+	      FBC_SYS_CACHE_START_BASE(offset);
+
+	mutex_lock(&sys_cache->lock);
+	/* update sys cache config only if sys cache is unassigned */
+	if (sys_cache->id == FBC_SYS_CACHE_ID_NONE)
+		fbc_sys_cache_update_config(display, cfg, fbc->id);
+	mutex_unlock(&sys_cache->lock);
+}
+
 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 {
 	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
@@ -967,6 +1032,11 @@ void intel_fbc_cleanup(struct intel_display *display)
 
 		kfree(fbc);
 	}
+
+	mutex_lock(&display->fbc.sys_cache.lock);
+	drm_WARN_ON(display->drm,
+		    display->fbc.sys_cache.id != FBC_SYS_CACHE_ID_NONE);
+	mutex_unlock(&display->fbc.sys_cache.lock);
 }
 
 static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
@@ -1780,6 +1850,8 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
 
 	__intel_fbc_cleanup_cfb(fbc);
 
+	fbc_sys_cache_disable(fbc);
+
 	/* wa_18038517565 Enable DPFC clock gating after FBC disable */
 	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
 		fbc_compressor_clkgate_disable_wa(fbc, false);
@@ -1972,6 +2044,8 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
 
 	intel_fbc_program_workarounds(fbc);
 	intel_fbc_program_cfb(fbc);
+
+	fbc_sys_cache_enable(fbc);
 }
 
 /**
@@ -2212,6 +2286,9 @@ void intel_fbc_init(struct intel_display *display)
 
 	for_each_fbc_id(display, fbc_id)
 		display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
+
+	mutex_init(&display->fbc.sys_cache.lock);
+	display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE;
 }
 
 /**
@@ -2231,6 +2308,11 @@ void intel_fbc_sanitize(struct intel_display *display)
 		if (intel_fbc_hw_is_active(fbc))
 			intel_fbc_hw_deactivate(fbc);
 	}
+
+	/* Ensure the sys cache usage config is clear as well */
+	mutex_lock(&display->fbc.sys_cache.lock);
+	fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE);
+	mutex_unlock(&display->fbc.sys_cache.lock);
 }
 
 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
@@ -2249,6 +2331,11 @@ static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
 		seq_puts(m, "FBC enabled\n");
 		seq_printf(m, "Compressing: %s\n",
 			   str_yes_no(intel_fbc_is_compressing(fbc)));
+
+		mutex_lock(&display->fbc.sys_cache.lock);
+		seq_printf(m, "Using system cache: %s\n",
+			   str_yes_no(display->fbc.sys_cache.id == fbc->id));
+		mutex_unlock(&display->fbc.sys_cache.lock);
 	} else {
 		seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
index b1d0161a3196..d2d889fa4bed 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -126,4 +126,14 @@
 #define   FBC_REND_NUKE			REG_BIT(2)
 #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
 
+#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
+#define   FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
+#define   FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
+#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15, 4)
+#define   FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
+#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3, 2)
+#define   FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
+#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
+#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
+
 #endif /* __INTEL_FBC_REGS__ */
-- 
2.43.0

Re: [PATCH v5 2/3] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Hogander, Jouni]

On Fri, 2025-11-28 at 13:35 +0200, Vinod Govindapillai wrote:
> One of the FBC instances can utilize the reserved area of SoC
> level cache for the fbc transactions to benefit reduced memory
> system power especially in idle scenarios. Reserved area of the
> system cache can be assigned to an fbc instance by configuring
> the cacheability configuration register with offset of the
> compressed frame buffer in stolen memoty of that fbc. There is
> a limit to this reserved area which is programmable and for
> xe3p_lpd the limit is defined as 2MB.

Maybe you could mention here wow it is decided which instance can use
the cache?

> 
> v2: - better to track fbc sys cache usage from intel_display level,
>       sanitize the cacheability config register on probe (Matt)
>     - limit this for integrated graphics solutions, confirmed that
>       no default value set for cache range by hw (Gustavo)
> 
> v3: - changes related to the use of fbc substruct in intel_display
>     - use intel_de_write() instead of intel_rmw() by hardcoding the
>       default value fields
> 
> v4: - protect sys cache config accesses, sys cache usage status in
>       debugfs per fbc instance (Jani)
> 
> v5: - mutex_init and missing mutex_lock in sanitize call
> 
> Bspec: 68881, 74722
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  7 ++
>  .../drm/i915/display/intel_display_device.h   |  1 +
>  drivers/gpu/drm/i915/display/intel_fbc.c      | 87
> +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 +++
>  4 files changed, 105 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 58325f530670..0a1744b3b440 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -400,6 +400,13 @@ struct intel_display {
>  
>  	struct {
>  		struct intel_fbc *instances[I915_MAX_FBCS];
> +
> +		/* xe3p_lpd+: FBC instance utilizing the system
> cache */
> +		struct sys_cache_cfg {
> +			/* Protect concurrecnt access to system
> cache configuration */
> +			struct mutex lock;
> +			enum intel_fbc_id id;
> +		} sys_cache;
>  	} fbc;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index b559ef43d547..b74cb69ccc85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -173,6 +173,7 @@ struct intel_display_platforms {
>  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >=
> 12 && HAS_DSC(__display))
>  #define
> HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >=
> 30)
> +#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >=
> 35 && !(__display)->platform.dgfx)
>  #define
> HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
>  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >=
> 3)
>  #define
> HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index dcdfcff80de3..cebde5db3dd7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -71,6 +71,8 @@
>  	for_each_fbc_id((__display), (__fbc_id)) \
>  		for_each_if((__fbc) = (__display)-
> >fbc.instances[(__fbc_id)])
>  
> +#define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
> +
>  struct intel_fbc_funcs {
>  	void (*activate)(struct intel_fbc *fbc);
>  	void (*deactivate)(struct intel_fbc *fbc);
> @@ -941,6 +943,69 @@ static void intel_fbc_program_workarounds(struct
> intel_fbc *fbc)
>  		fbc_compressor_clkgate_disable_wa(fbc, true);
>  }
>  
> +static void fbc_sys_cache_update_config(struct intel_display
> *display, u32 reg,
> +					enum intel_fbc_id id)
> +{
> +	if (!HAS_FBC_SYS_CACHE(display))
> +		return;
> +
> +	lockdep_assert_held(&display->fbc.sys_cache.lock);
> +
> +	/* Cache read enable is set by default */
> +	reg |= FBC_SYS_CACHE_READ_ENABLE;
> +
> +	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG,
> reg);
> +
> +	display->fbc.sys_cache.id = id;
> +}
> +
> +static void fbc_sys_cache_disable(const struct intel_fbc *fbc)
> +{
> +	struct intel_display *display = fbc->display;
> +	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;

How about early return in here as well? :

if (!HAS_FBC_SYS_CACHE(display))
		return;
> +
> +	mutex_lock(&sys_cache->lock);
> +	/* clear only if "fbc" reserved the cache */
> +	if (sys_cache->id == fbc->id)
> +		fbc_sys_cache_update_config(display, 0,
> FBC_SYS_CACHE_ID_NONE);
> +	mutex_unlock(&sys_cache->lock);
> +}
> +
> +static int fbc_sys_cache_limit(struct intel_display *display)
> +{
> +	/* Default 2MB for xe3p_lpd */

You could review all added comments in this patch and consider dropping
if not all but at least some of them. E.g. Do we really need
clarification saying 2 * 1024 * 1024 is 2MB? On the other hand you are
saying xe3p_lpd but then checking display version below. How xe3p_lpd
is related to display version 35?

Anyways the patch looks ok to me:

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> +	if (DISPLAY_VER(display) == 35)
> +		return 2 * 1024 * 1024;
> +
> +	return 0;
> +}
> +
> +static void fbc_sys_cache_enable(const struct intel_fbc *fbc)
> +{
> +	struct intel_display *display = fbc->display;
> +	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
> +	int range, offset;
> +	u32 cfg;
> +
> +	if (!HAS_FBC_SYS_CACHE(display))
> +		return;
> +
> +	/* limit to be configured to the register in 64k byte chunks
> */
> +	range = fbc_sys_cache_limit(display) / (64 * 1024);
> +
> +	/* offset to be configured to the register in 4K byte chunks
> */
> +	offset = i915_gem_stolen_node_offset(fbc->compressed_fb) /
> (4 * 1024);
> +
> +	cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
> FBC_SYS_CACHEABLE_RANGE(range) |
> +	      FBC_SYS_CACHE_START_BASE(offset);
> +
> +	mutex_lock(&sys_cache->lock);
> +	/* update sys cache config only if sys cache is unassigned
> */
> +	if (sys_cache->id == FBC_SYS_CACHE_ID_NONE)
> +		fbc_sys_cache_update_config(display, cfg, fbc->id);
> +	mutex_unlock(&sys_cache->lock);
> +}
> +
>  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>  {
>  	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> @@ -967,6 +1032,11 @@ void intel_fbc_cleanup(struct intel_display
> *display)
>  
>  		kfree(fbc);
>  	}
> +
> +	mutex_lock(&display->fbc.sys_cache.lock);
> +	drm_WARN_ON(display->drm,
> +		    display->fbc.sys_cache.id !=
> FBC_SYS_CACHE_ID_NONE);
> +	mutex_unlock(&display->fbc.sys_cache.lock);
>  }
>  
>  static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state
> *plane_state)
> @@ -1780,6 +1850,8 @@ static void __intel_fbc_disable(struct
> intel_fbc *fbc)
>  
>  	__intel_fbc_cleanup_cfb(fbc);
>  
> +	fbc_sys_cache_disable(fbc);
> +
>  	/* wa_18038517565 Enable DPFC clock gating after FBC disable
> */
>  	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
>  		fbc_compressor_clkgate_disable_wa(fbc, false);
> @@ -1972,6 +2044,8 @@ static void __intel_fbc_enable(struct
> intel_atomic_state *state,
>  
>  	intel_fbc_program_workarounds(fbc);
>  	intel_fbc_program_cfb(fbc);
> +
> +	fbc_sys_cache_enable(fbc);
>  }
>  
>  /**
> @@ -2212,6 +2286,9 @@ void intel_fbc_init(struct intel_display
> *display)
>  
>  	for_each_fbc_id(display, fbc_id)
>  		display->fbc.instances[fbc_id] =
> intel_fbc_create(display, fbc_id);
> +
> +	mutex_init(&display->fbc.sys_cache.lock);
> +	display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE;
>  }
>  
>  /**
> @@ -2231,6 +2308,11 @@ void intel_fbc_sanitize(struct intel_display
> *display)
>  		if (intel_fbc_hw_is_active(fbc))
>  			intel_fbc_hw_deactivate(fbc);
>  	}
> +
> +	/* Ensure the sys cache usage config is clear as well */
> +	mutex_lock(&display->fbc.sys_cache.lock);
> +	fbc_sys_cache_update_config(display, 0,
> FBC_SYS_CACHE_ID_NONE);
> +	mutex_unlock(&display->fbc.sys_cache.lock);
>  }
>  
>  static int intel_fbc_debugfs_status_show(struct seq_file *m, void
> *unused)
> @@ -2249,6 +2331,11 @@ static int
> intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
>  		seq_puts(m, "FBC enabled\n");
>  		seq_printf(m, "Compressing: %s\n",
>  			  
> str_yes_no(intel_fbc_is_compressing(fbc)));
> +
> +		mutex_lock(&display->fbc.sys_cache.lock);
> +		seq_printf(m, "Using system cache: %s\n",
> +			   str_yes_no(display->fbc.sys_cache.id ==
> fbc->id));
> +		mutex_unlock(&display->fbc.sys_cache.lock);
>  	} else {
>  		seq_printf(m, "FBC disabled: %s\n", fbc-
> >no_fbc_reason);
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> index b1d0161a3196..d2d889fa4bed 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -126,4 +126,14 @@
>  #define   FBC_REND_NUKE			REG_BIT(2)
>  #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
>  
> +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
> +#define  
> FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
> +#define  
> FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK,(base))
> +#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15, 4)
> +#define  
> FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK,(range))
> +#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3, 2)
> +#define  
> FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
> +#define  
> FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,3)
> +#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
> +
>  #endif /* __INTEL_FBC_REGS__ */

Re: [PATCH v5 2/3] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Govindapillai, Vinod]

Hi Jouni

Thanks for the review.

On Wed, 2025-12-03 at 13:12 +0000, Hogander, Jouni wrote:
> On Fri, 2025-11-28 at 13:35 +0200, Vinod Govindapillai wrote:
> > One of the FBC instances can utilize the reserved area of SoC
> > level cache for the fbc transactions to benefit reduced memory
> > system power especially in idle scenarios. Reserved area of the
> > system cache can be assigned to an fbc instance by configuring
> > the cacheability configuration register with offset of the
> > compressed frame buffer in stolen memoty of that fbc. There is
> > a limit to this reserved area which is programmable and for
> > xe3p_lpd the limit is defined as 2MB.
> 
> Maybe you could mention here wow it is decided which instance can use
> the cache?
> 
Ack
> > 
> > v2: - better to track fbc sys cache usage from intel_display level,
> >       sanitize the cacheability config register on probe (Matt)
> >     - limit this for integrated graphics solutions, confirmed that
> >       no default value set for cache range by hw (Gustavo)
> > 
> > v3: - changes related to the use of fbc substruct in intel_display
> >     - use intel_de_write() instead of intel_rmw() by hardcoding the
> >       default value fields
> > 
> > v4: - protect sys cache config accesses, sys cache usage status in
> >       debugfs per fbc instance (Jani)
> > 
> > v5: - mutex_init and missing mutex_lock in sanitize call
> > 
> > Bspec: 68881, 74722
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_display_core.h |  7 ++
> >  .../drm/i915/display/intel_display_device.h   |  1 +
> >  drivers/gpu/drm/i915/display/intel_fbc.c      | 87
> > +++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 +++
> >  4 files changed, 105 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> > b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 58325f530670..0a1744b3b440 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -400,6 +400,13 @@ struct intel_display {
> >  
> >  	struct {
> >  		struct intel_fbc *instances[I915_MAX_FBCS];
> > +
> > +		/* xe3p_lpd+: FBC instance utilizing the system
> > cache */
> > +		struct sys_cache_cfg {
> > +			/* Protect concurrecnt access to system
> > cache configuration */
> > +			struct mutex lock;
> > +			enum intel_fbc_id id;
> > +		} sys_cache;
> >  	} fbc;
> >  
> >  	struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index b559ef43d547..b74cb69ccc85 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -173,6 +173,7 @@ struct intel_display_platforms {
> >  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >=
> > 12 && HAS_DSC(__display))
> >  #define
> > HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)-
> > >fbc_mask != 0)
> >  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >=
> > 30)
> > +#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >=
> > 35 && !(__display)->platform.dgfx)
> >  #define
> > HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)-
> > >has_fpga_dbg)
> >  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >=
> > 3)
> >  #define
> > HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 ||
> > (__display)->platform.kabylake)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index dcdfcff80de3..cebde5db3dd7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -71,6 +71,8 @@
> >  	for_each_fbc_id((__display), (__fbc_id)) \
> >  		for_each_if((__fbc) = (__display)-
> > > fbc.instances[(__fbc_id)])
> >  
> > +#define FBC_SYS_CACHE_ID_NONE	I915_MAX_FBCS
> > +
> >  struct intel_fbc_funcs {
> >  	void (*activate)(struct intel_fbc *fbc);
> >  	void (*deactivate)(struct intel_fbc *fbc);
> > @@ -941,6 +943,69 @@ static void
> > intel_fbc_program_workarounds(struct
> > intel_fbc *fbc)
> >  		fbc_compressor_clkgate_disable_wa(fbc, true);
> >  }
> >  
> > +static void fbc_sys_cache_update_config(struct intel_display
> > *display, u32 reg,
> > +					enum intel_fbc_id id)
> > +{
> > +	if (!HAS_FBC_SYS_CACHE(display))
> > +		return;
> > +
> > +	lockdep_assert_held(&display->fbc.sys_cache.lock);
> > +
> > +	/* Cache read enable is set by default */
> > +	reg |= FBC_SYS_CACHE_READ_ENABLE;
> > +
> > +	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG,
> > reg);
> > +
> > +	display->fbc.sys_cache.id = id;
> > +}
> > +
> > +static void fbc_sys_cache_disable(const struct intel_fbc *fbc)
> > +{
> > +	struct intel_display *display = fbc->display;
> > +	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
> 
> How about early return in here as well? :
> 
> if (!HAS_FBC_SYS_CACHE(display))
> 		return;

Here (sys_cache->id == fbc->id) check should handle the same condition
as sys_cache->id will never be fbc-id if FBC_SYS_CACHE feature is not
supported. Jani was suggesting this in his comments in the previous
iteration.  

> > +
> > +	mutex_lock(&sys_cache->lock);
> > +	/* clear only if "fbc" reserved the cache */
> > +	if (sys_cache->id == fbc->id)
> > +		fbc_sys_cache_update_config(display, 0,
> > FBC_SYS_CACHE_ID_NONE);
> > +	mutex_unlock(&sys_cache->lock);
> > +}
> > +
> > +static int fbc_sys_cache_limit(struct intel_display *display)
> > +{
> > +	/* Default 2MB for xe3p_lpd */
> 
> You could review all added comments in this patch and consider
> dropping
> if not all but at least some of them. E.g. Do we really need
> clarification saying 2 * 1024 * 1024 is 2MB? On the other hand you
> are
> saying xe3p_lpd but then checking display version below. How xe3p_lpd
> is related to display version 35?

Yeah.. my intention was to explain that magic number 2MB as the default
for NVL. But you are right I could remove some of those comments as
those are anyway found from bspec.

Thanks
Vinod

> 
> Anyways the patch looks ok to me:
> 
> Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> 
> > +	if (DISPLAY_VER(display) == 35)
> > +		return 2 * 1024 * 1024;
> > +
> > +	return 0;
> > +}
> > +
> > +static void fbc_sys_cache_enable(const struct intel_fbc *fbc)
> > +{
> > +	struct intel_display *display = fbc->display;
> > +	struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache;
> > +	int range, offset;
> > +	u32 cfg;
> > +
> > +	if (!HAS_FBC_SYS_CACHE(display))
> > +		return;
> > +
> > +	/* limit to be configured to the register in 64k byte
> > chunks
> > */
> > +	range = fbc_sys_cache_limit(display) / (64 * 1024);
> > +
> > +	/* offset to be configured to the register in 4K byte
> > chunks
> > */
> > +	offset = i915_gem_stolen_node_offset(fbc->compressed_fb) /
> > (4 * 1024);
> > +
> > +	cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
> > FBC_SYS_CACHEABLE_RANGE(range) |
> > +	      FBC_SYS_CACHE_START_BASE(offset);
> > +
> > +	mutex_lock(&sys_cache->lock);
> > +	/* update sys cache config only if sys cache is unassigned
> > */
> > +	if (sys_cache->id == FBC_SYS_CACHE_ID_NONE)
> > +		fbc_sys_cache_update_config(display, cfg, fbc-
> > >id);
> > +	mutex_unlock(&sys_cache->lock);
> > +}
> > +
> >  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
> >  {
> >  	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> > @@ -967,6 +1032,11 @@ void intel_fbc_cleanup(struct intel_display
> > *display)
> >  
> >  		kfree(fbc);
> >  	}
> > +
> > +	mutex_lock(&display->fbc.sys_cache.lock);
> > +	drm_WARN_ON(display->drm,
> > +		    display->fbc.sys_cache.id !=
> > FBC_SYS_CACHE_ID_NONE);
> > +	mutex_unlock(&display->fbc.sys_cache.lock);
> >  }
> >  
> >  static bool i8xx_fbc_stride_is_valid(const struct
> > intel_plane_state
> > *plane_state)
> > @@ -1780,6 +1850,8 @@ static void __intel_fbc_disable(struct
> > intel_fbc *fbc)
> >  
> >  	__intel_fbc_cleanup_cfb(fbc);
> >  
> > +	fbc_sys_cache_disable(fbc);
> > +
> >  	/* wa_18038517565 Enable DPFC clock gating after FBC
> > disable
> > */
> >  	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
> >  		fbc_compressor_clkgate_disable_wa(fbc, false);
> > @@ -1972,6 +2044,8 @@ static void __intel_fbc_enable(struct
> > intel_atomic_state *state,
> >  
> >  	intel_fbc_program_workarounds(fbc);
> >  	intel_fbc_program_cfb(fbc);
> > +
> > +	fbc_sys_cache_enable(fbc);
> >  }
> >  
> >  /**
> > @@ -2212,6 +2286,9 @@ void intel_fbc_init(struct intel_display
> > *display)
> >  
> >  	for_each_fbc_id(display, fbc_id)
> >  		display->fbc.instances[fbc_id] =
> > intel_fbc_create(display, fbc_id);
> > +
> > +	mutex_init(&display->fbc.sys_cache.lock);
> > +	display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE;
> >  }
> >  
> >  /**
> > @@ -2231,6 +2308,11 @@ void intel_fbc_sanitize(struct intel_display
> > *display)
> >  		if (intel_fbc_hw_is_active(fbc))
> >  			intel_fbc_hw_deactivate(fbc);
> >  	}
> > +
> > +	/* Ensure the sys cache usage config is clear as well */
> > +	mutex_lock(&display->fbc.sys_cache.lock);
> > +	fbc_sys_cache_update_config(display, 0,
> > FBC_SYS_CACHE_ID_NONE);
> > +	mutex_unlock(&display->fbc.sys_cache.lock);
> >  }
> >  
> >  static int intel_fbc_debugfs_status_show(struct seq_file *m, void
> > *unused)
> > @@ -2249,6 +2331,11 @@ static int
> > intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
> >  		seq_puts(m, "FBC enabled\n");
> >  		seq_printf(m, "Compressing: %s\n",
> >  			  
> > str_yes_no(intel_fbc_is_compressing(fbc)));
> > +
> > +		mutex_lock(&display->fbc.sys_cache.lock);
> > +		seq_printf(m, "Using system cache: %s\n",
> > +			   str_yes_no(display->fbc.sys_cache.id ==
> > fbc->id));
> > +		mutex_unlock(&display->fbc.sys_cache.lock);
> >  	} else {
> >  		seq_printf(m, "FBC disabled: %s\n", fbc-
> > > no_fbc_reason);
> >  	}
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > index b1d0161a3196..d2d889fa4bed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > @@ -126,4 +126,14 @@
> >  #define   FBC_REND_NUKE			REG_BIT(2)
> >  #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
> >  
> > +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
> > +#define  
> > FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
> > +#define  
> > FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_START
> > _BASE_MASK,(base))
> > +#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15, 4)
> > +#define  
> > FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE_R
> > ANGE_MASK,(range))
> > +#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3, 2)
> > +#define  
> > FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_CAC
> > HE_TAG_MASK, 0)
> > +#define  
> > FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG_M
> > ASK,3)
> > +#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
> > +
> >  #endif /* __INTEL_FBC_REGS__ */
> 

[PATCH v4 3/3] drm/i915/fbc: Apply Wa_14025769978

[Vinod Govindapillai]

Disable cache read setting in the cacheability configuration
register as per the wa recommendation

Bspec: 79482, 74722, 68881
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c |  2 ++
 drivers/gpu/drm/i915/display/intel_display_wa.h |  1 +
 drivers/gpu/drm/i915/display/intel_fbc.c        | 10 ++++++++--
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index b2e71fa61c0a..a00af39f7538 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -72,6 +72,8 @@ bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa,
 		return IS_DISPLAY_VERx100(display, 1100, 1400);
 	case INTEL_DISPLAY_WA_15018326506:
 		return display->platform.battlemage;
+	case INTEL_DISPLAY_WA_14025769978:
+		return DISPLAY_VER(display) == 35;
 	default:
 		drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name);
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
index f648b00cb97d..a68c0bb7e516 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -27,6 +27,7 @@ enum intel_display_wa {
 	INTEL_DISPLAY_WA_14011503117,
 	INTEL_DISPLAY_WA_22014263786,
 	INTEL_DISPLAY_WA_15018326506,
+	INTEL_DISPLAY_WA_14025769978,
 };
 
 bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 85978196b607..84a1ab0bd418 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -951,8 +951,14 @@ static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg,
 
 	lockdep_assert_held(&display->fbc.sys_cache.lock);
 
-	/* Cache read enable is set by default */
-	reg |= FBC_SYS_CACHE_READ_ENABLE;
+	/*
+	 * Wa_14025769978:
+	 * Fixes: SoC hardware issue in read caching
+	 * Workaround: disable cache read setting which is enabled by default.
+	 */
+	if (!intel_display_wa(display, 14025769978))
+		/* Cache read enable is set by default */
+		reg |= FBC_SYS_CACHE_READ_ENABLE;
 
 	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg);
 
-- 
2.43.0

Re: [PATCH v4 3/3] drm/i915/fbc: Apply Wa_14025769978

[Hogander, Jouni]

On Thu, 2025-11-27 at 13:53 +0200, Vinod Govindapillai wrote:
> Disable cache read setting in the cacheability configuration
> register as per the wa recommendation

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> 
> Bspec: 79482, 74722, 68881
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_wa.c |  2 ++
>  drivers/gpu/drm/i915/display/intel_display_wa.h |  1 +
>  drivers/gpu/drm/i915/display/intel_fbc.c        | 10 ++++++++--
>  3 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index b2e71fa61c0a..a00af39f7538 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -72,6 +72,8 @@ bool __intel_display_wa(struct intel_display
> *display, enum intel_display_wa wa,
>  		return IS_DISPLAY_VERx100(display, 1100, 1400);
>  	case INTEL_DISPLAY_WA_15018326506:
>  		return display->platform.battlemage;
> +	case INTEL_DISPLAY_WA_14025769978:
> +		return DISPLAY_VER(display) == 35;
>  	default:
>  		drm_WARN(display->drm, 1, "Missing Wa number: %s\n",
> name);
>  		break;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h
> b/drivers/gpu/drm/i915/display/intel_display_wa.h
> index f648b00cb97d..a68c0bb7e516 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
> @@ -27,6 +27,7 @@ enum intel_display_wa {
>  	INTEL_DISPLAY_WA_14011503117,
>  	INTEL_DISPLAY_WA_22014263786,
>  	INTEL_DISPLAY_WA_15018326506,
> +	INTEL_DISPLAY_WA_14025769978,
>  };
>  
>  bool __intel_display_wa(struct intel_display *display, enum
> intel_display_wa wa, const char *name);
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 85978196b607..84a1ab0bd418 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -951,8 +951,14 @@ static void fbc_sys_cache_update_config(struct
> intel_display *display, u32 reg,
>  
>  	lockdep_assert_held(&display->fbc.sys_cache.lock);
>  
> -	/* Cache read enable is set by default */
> -	reg |= FBC_SYS_CACHE_READ_ENABLE;
> +	/*
> +	 * Wa_14025769978:
> +	 * Fixes: SoC hardware issue in read caching
> +	 * Workaround: disable cache read setting which is enabled
> by default.
> +	 */
> +	if (!intel_display_wa(display, 14025769978))
> +		/* Cache read enable is set by default */
> +		reg |= FBC_SYS_CACHE_READ_ENABLE;
>  
>  	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG,
> reg);
>  

✗ i915.CI.BAT: failure for drm/i915/display: Enable system cache support for FBC (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 14254 bytes --]

== Series Details ==

Series: drm/i915/display: Enable system cache support for FBC (rev2)
URL   : https://patchwork.freedesktop.org/series/157945/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17595 -> Patchwork_157945v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_157945v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_157945v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/index.html

Participating hosts (45 -> 44)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_157945v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - fi-ilk-650:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-ilk-650/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-ilk-650/igt@i915_module_load@load.html
    - bat-jsl-1:          [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-jsl-1/igt@i915_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-jsl-1/igt@i915_module_load@load.html
    - fi-bsw-n3050:       [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-bsw-n3050/igt@i915_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-bsw-n3050/igt@i915_module_load@load.html
    - bat-adlp-6:         [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-adlp-6/igt@i915_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-adlp-6/igt@i915_module_load@load.html
    - bat-arlh-2:         [PASS][9] -> [ABORT][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-arlh-2/igt@i915_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-arlh-2/igt@i915_module_load@load.html
    - fi-rkl-11600:       [PASS][11] -> [ABORT][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-rkl-11600/igt@i915_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-rkl-11600/igt@i915_module_load@load.html
    - fi-skl-6600u:       [PASS][13] -> [ABORT][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-skl-6600u/igt@i915_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-skl-6600u/igt@i915_module_load@load.html
    - bat-arlh-3:         [PASS][15] -> [ABORT][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-arlh-3/igt@i915_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-arlh-3/igt@i915_module_load@load.html
    - fi-pnv-d510:        [PASS][17] -> [ABORT][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-pnv-d510/igt@i915_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-pnv-d510/igt@i915_module_load@load.html
    - bat-dg1-7:          [PASS][19] -> [ABORT][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-dg1-7/igt@i915_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-dg1-7/igt@i915_module_load@load.html
    - bat-dg2-13:         [PASS][21] -> [ABORT][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-dg2-13/igt@i915_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-dg2-13/igt@i915_module_load@load.html
    - fi-glk-j4005:       [PASS][23] -> [ABORT][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-glk-j4005/igt@i915_module_load@load.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-glk-j4005/igt@i915_module_load@load.html
    - bat-adlp-9:         [PASS][25] -> [ABORT][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-adlp-9/igt@i915_module_load@load.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-adlp-9/igt@i915_module_load@load.html
    - bat-twl-2:          [PASS][27] -> [ABORT][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-twl-2/igt@i915_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-twl-2/igt@i915_module_load@load.html
    - bat-dg2-11:         [PASS][29] -> [ABORT][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-dg2-11/igt@i915_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-dg2-11/igt@i915_module_load@load.html
    - bat-rpls-4:         [PASS][31] -> [ABORT][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-rpls-4/igt@i915_module_load@load.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-rpls-4/igt@i915_module_load@load.html
    - fi-kbl-7567u:       [PASS][33] -> [ABORT][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-kbl-7567u/igt@i915_module_load@load.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-kbl-7567u/igt@i915_module_load@load.html
    - fi-cfl-8700k:       [PASS][35] -> [ABORT][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-cfl-8700k/igt@i915_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-cfl-8700k/igt@i915_module_load@load.html
    - bat-twl-1:          [PASS][37] -> [ABORT][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-twl-1/igt@i915_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-twl-1/igt@i915_module_load@load.html
    - fi-kbl-8809g:       [PASS][39] -> [ABORT][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-kbl-8809g/igt@i915_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-kbl-8809g/igt@i915_module_load@load.html
    - bat-jsl-5:          [PASS][41] -> [ABORT][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-jsl-5/igt@i915_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-jsl-5/igt@i915_module_load@load.html
    - bat-apl-1:          [PASS][43] -> [ABORT][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-apl-1/igt@i915_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-apl-1/igt@i915_module_load@load.html
    - bat-dg2-14:         [PASS][45] -> [ABORT][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-dg2-14/igt@i915_module_load@load.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-dg2-14/igt@i915_module_load@load.html
    - fi-elk-e7500:       [PASS][47] -> [ABORT][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-elk-e7500/igt@i915_module_load@load.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-elk-e7500/igt@i915_module_load@load.html
    - fi-bsw-nick:        [PASS][49] -> [ABORT][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-bsw-nick/igt@i915_module_load@load.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-bsw-nick/igt@i915_module_load@load.html
    - bat-kbl-2:          [PASS][51] -> [ABORT][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-kbl-2/igt@i915_module_load@load.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-kbl-2/igt@i915_module_load@load.html
    - bat-arls-5:         [PASS][53] -> [ABORT][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-arls-5/igt@i915_module_load@load.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-arls-5/igt@i915_module_load@load.html
    - bat-rplp-1:         [PASS][55] -> [ABORT][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-rplp-1/igt@i915_module_load@load.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-rplp-1/igt@i915_module_load@load.html
    - fi-tgl-1115g4:      [PASS][57] -> [ABORT][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-tgl-1115g4/igt@i915_module_load@load.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-tgl-1115g4/igt@i915_module_load@load.html
    - fi-cfl-guc:         [PASS][59] -> [ABORT][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-cfl-guc/igt@i915_module_load@load.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-cfl-guc/igt@i915_module_load@load.html
    - bat-mtlp-6:         [PASS][61] -> [ABORT][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-mtlp-6/igt@i915_module_load@load.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-mtlp-6/igt@i915_module_load@load.html
    - bat-mtlp-9:         [PASS][63] -> [ABORT][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-mtlp-9/igt@i915_module_load@load.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-mtlp-9/igt@i915_module_load@load.html
    - bat-arls-6:         [PASS][65] -> [ABORT][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-arls-6/igt@i915_module_load@load.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-arls-6/igt@i915_module_load@load.html
    - bat-dg2-9:          [PASS][67] -> [ABORT][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-dg2-9/igt@i915_module_load@load.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-dg2-9/igt@i915_module_load@load.html
    - fi-kbl-x1275:       [PASS][69] -> [ABORT][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-kbl-x1275/igt@i915_module_load@load.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-kbl-x1275/igt@i915_module_load@load.html
    - bat-adlp-11:        [PASS][71] -> [ABORT][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-adlp-11/igt@i915_module_load@load.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-adlp-11/igt@i915_module_load@load.html
    - fi-hsw-4770:        [PASS][73] -> [ABORT][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-hsw-4770/igt@i915_module_load@load.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-hsw-4770/igt@i915_module_load@load.html
    - fi-ivb-3770:        [PASS][75] -> [ABORT][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-ivb-3770/igt@i915_module_load@load.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-ivb-3770/igt@i915_module_load@load.html
    - bat-mtlp-8:         [PASS][77] -> [ABORT][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-mtlp-8/igt@i915_module_load@load.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-mtlp-8/igt@i915_module_load@load.html
    - bat-dg1-6:          [PASS][79] -> [ABORT][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-dg1-6/igt@i915_module_load@load.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-dg1-6/igt@i915_module_load@load.html
    - bat-dg2-8:          [PASS][81] -> [ABORT][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-dg2-8/igt@i915_module_load@load.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-dg2-8/igt@i915_module_load@load.html
    - fi-kbl-guc:         [PASS][83] -> [ABORT][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/fi-kbl-guc/igt@i915_module_load@load.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/fi-kbl-guc/igt@i915_module_load@load.html
    - bat-adls-6:         [PASS][85] -> [ABORT][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-adls-6/igt@i915_module_load@load.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-adls-6/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_157945v2 that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][87] ([i915#12061] / [i915#13929]) -> [DMESG-FAIL][88] ([i915#12061] / [i915#14204])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-atsm-1/igt@i915_selftest@live.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-atsm-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [DMESG-FAIL][89] ([i915#13929]) -> [DMESG-FAIL][90] ([i915#14204])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17595/bat-atsm-1/igt@i915_selftest@live@mman.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204


Build changes
-------------

  * Linux: CI_DRM_17595 -> Patchwork_157945v2

  CI-20190529: 20190529
  CI_DRM_17595: e7a767430515c3a6e8aee91c2a68cba8b06fe884 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8639: 2ce563031e6b2ec91479f6af8c326d25c15bdb26 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_157945v2: e7a767430515c3a6e8aee91c2a68cba8b06fe884 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v2/index.html

[-- Attachment #2: Type: text/html, Size: 15309 bytes --]

✗ Fi.CI.BUILD: failure for drm/i915/display: Enable system cache support for FBC (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Enable system cache support for FBC (rev3)
URL   : https://patchwork.freedesktop.org/series/157945/
State : failure

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/157945/revisions/3/mbox/ not applied
Applying: drm/i915/display: Use a sub-struct for fbc operations in intel_display
Applying: drm/i915/xe3p_lpd: Enable display use of system cache for FBC
error: git diff header lacks filename information when removing 1 leading pathname component (line 2)
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm/i915/xe3p_lpd: Enable display use of system cache for FBC
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

✗ i915.CI.BAT: failure for drm/i915/display: Enable system cache support for FBC (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3894 bytes --]

== Series Details ==

Series: drm/i915/display: Enable system cache support for FBC (rev4)
URL   : https://patchwork.freedesktop.org/series/157945/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17605 -> Patchwork_157945v4
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_157945v4 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_157945v4, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/index.html

Participating hosts (45 -> 44)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_157945v4:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_flink_basic@bad-open:
    - bat-adls-6:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/bat-adls-6/igt@gem_flink_basic@bad-open.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/bat-adls-6/igt@gem_flink_basic@bad-open.html

  * igt@i915_hangman@error-state-basic:
    - fi-glk-j4005:       [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/fi-glk-j4005/igt@i915_hangman@error-state-basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/fi-glk-j4005/igt@i915_hangman@error-state-basic.html

  
Known issues
------------

  Here are the changes found in Patchwork_157945v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests@dma_fence_chain:
    - bat-twl-2:          NOTRUN -> [SKIP][5] ([i915#15249])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/bat-twl-2/igt@dmabuf@all-tests@dma_fence_chain.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@reset:
    - bat-twl-2:          [ABORT][6] ([i915#14365]) -> [PASS][7] +1 other test pass
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/bat-twl-2/igt@i915_selftest@live@reset.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/bat-twl-2/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [DMESG-FAIL][8] ([i915#12061]) -> [PASS][9] +1 other test pass
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/bat-dg2-9/igt@i915_selftest@live@workarounds.html
    - bat-dg2-14:         [DMESG-FAIL][10] ([i915#12061]) -> [PASS][11] +1 other test pass
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/bat-dg2-14/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#14365]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14365
  [i915#15249]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15249


Build changes
-------------

  * Linux: CI_DRM_17605 -> Patchwork_157945v4

  CI-20190529: 20190529
  CI_DRM_17605: e1c1b3e03e356d1e20432dcb0d38ad44d5e92670 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8644: 069c5ee6eb658181e7264883c6c4fba41fc917a4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_157945v4: e1c1b3e03e356d1e20432dcb0d38ad44d5e92670 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/index.html

[-- Attachment #2: Type: text/html, Size: 4700 bytes --]

✓ i915.CI.BAT: success for drm/i915/display: Enable system cache support for FBC (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3553 bytes --]

== Series Details ==

Series: drm/i915/display: Enable system cache support for FBC (rev4)
URL   : https://patchwork.freedesktop.org/series/157945/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17605 -> Patchwork_157945v4
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/index.html

Participating hosts (45 -> 44)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_157945v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests@dma_fence_chain:
    - bat-twl-2:          NOTRUN -> [SKIP][1] ([i915#15249])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/bat-twl-2/igt@dmabuf@all-tests@dma_fence_chain.html

  * igt@gem_flink_basic@bad-open:
    - bat-adls-6:         [PASS][2] -> [INCOMPLETE][3] ([i915#15352])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/bat-adls-6/igt@gem_flink_basic@bad-open.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/bat-adls-6/igt@gem_flink_basic@bad-open.html

  * igt@i915_hangman@error-state-basic:
    - fi-glk-j4005:       [PASS][4] -> [INCOMPLETE][5] ([i915#15350])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/fi-glk-j4005/igt@i915_hangman@error-state-basic.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/fi-glk-j4005/igt@i915_hangman@error-state-basic.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@reset:
    - bat-twl-2:          [ABORT][6] ([i915#14365]) -> [PASS][7] +1 other test pass
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/bat-twl-2/igt@i915_selftest@live@reset.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/bat-twl-2/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [DMESG-FAIL][8] ([i915#12061]) -> [PASS][9] +1 other test pass
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/bat-dg2-9/igt@i915_selftest@live@workarounds.html
    - bat-dg2-14:         [DMESG-FAIL][10] ([i915#12061]) -> [PASS][11] +1 other test pass
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/bat-dg2-14/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#14365]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14365
  [i915#15249]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15249
  [i915#15350]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15350
  [i915#15352]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15352


Build changes
-------------

  * Linux: CI_DRM_17605 -> Patchwork_157945v4

  CI-20190529: 20190529
  CI_DRM_17605: e1c1b3e03e356d1e20432dcb0d38ad44d5e92670 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8644: 069c5ee6eb658181e7264883c6c4fba41fc917a4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_157945v4: e1c1b3e03e356d1e20432dcb0d38ad44d5e92670 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/index.html

[-- Attachment #2: Type: text/html, Size: 4342 bytes --]

✗ i915.CI.Full: failure for drm/i915/display: Enable system cache support for FBC (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 95619 bytes --]

== Series Details ==

Series: drm/i915/display: Enable system cache support for FBC (rev4)
URL   : https://patchwork.freedesktop.org/series/157945/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17605_full -> Patchwork_157945v4_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_157945v4_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_157945v4_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_157945v4_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
    - shard-rkl:          [PASS][1] -> [FAIL][2] +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_atomic_transition@plane-toggle-modeset-transition.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_flip@flip-vs-suspend@b-hdmi-a2.html

  
Known issues
------------

  Here are the changes found in Patchwork_157945v4_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@crc32:
    - shard-tglu-1:       NOTRUN -> [SKIP][4] ([i915#6230])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@api_intel_bb@crc32.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-tglu-1:       NOTRUN -> [SKIP][5] ([i915#11078])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_basic@multigpu-create-close:
    - shard-mtlp:         NOTRUN -> [SKIP][6] ([i915#7697])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][7] ([i915#13008])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          [PASS][8] -> [INCOMPLETE][9] ([i915#12392] / [i915#13356])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-6/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-lmem0-lmem0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-7/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-tglu-1:       NOTRUN -> [SKIP][10] ([i915#7697])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_isolation@preservation-s3:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][11] ([i915#13356]) +1 other test incomplete
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk10/igt@gem_ctx_isolation@preservation-s3.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-tglu:         NOTRUN -> [ABORT][12] ([i915#15317]) +3 other tests abort
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-4/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_exec_balancer@noheartbeat:
    - shard-mtlp:         NOTRUN -> [SKIP][13] ([i915#8555])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@gem_exec_balancer@noheartbeat.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-rkl:          NOTRUN -> [SKIP][14] ([i915#4525])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-mtlp:         NOTRUN -> [SKIP][15] ([i915#3711])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_exec_reloc@basic-gtt-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][16] ([i915#3281]) +2 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@gem_exec_reloc@basic-gtt-cpu.html

  * igt@gem_exec_reloc@basic-gtt-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][17] ([i915#3281]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@gem_exec_reloc@basic-gtt-wc.html

  * igt@gem_exec_suspend@basic-s3-devices:
    - shard-rkl:          [PASS][18] -> [ABORT][19] ([i915#15317]) +2 other tests abort
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-5/igt@gem_exec_suspend@basic-s3-devices.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@gem_exec_suspend@basic-s3-devices.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - shard-glk:          NOTRUN -> [INCOMPLETE][20] ([i915#13196] / [i915#13356]) +1 other test incomplete
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk8/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][21] ([i915#4860])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html

  * igt@gem_huc_copy@huc-copy:
    - shard-glk:          NOTRUN -> [SKIP][22] ([i915#2190])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk9/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-glk:          NOTRUN -> [SKIP][23] ([i915#4613])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk9/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-mtlp:         NOTRUN -> [SKIP][24] ([i915#4613])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-tglu-1:       NOTRUN -> [SKIP][25] ([i915#4613]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_pread@snoop:
    - shard-mtlp:         NOTRUN -> [SKIP][26] ([i915#3282])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@gem_pread@snoop.html

  * igt@gem_pread@uncached:
    - shard-rkl:          NOTRUN -> [SKIP][27] ([i915#3282]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@gem_pread@uncached.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-glk:          NOTRUN -> [WARN][28] ([i915#14702] / [i915#2658])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk6/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - shard-tglu:         [PASS][29] -> [ABORT][30] ([i915#15317]) +2 other tests abort
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-tglu-2/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-7/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html

  * igt@gem_softpin@noreloc-s3:
    - shard-glk:          NOTRUN -> [INCOMPLETE][31] ([i915#13809])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk9/igt@gem_softpin@noreloc-s3.html

  * igt@gem_tiled_pread_pwrite:
    - shard-mtlp:         NOTRUN -> [SKIP][32] ([i915#4079])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@gem_tiled_pread_pwrite.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap:
    - shard-mtlp:         NOTRUN -> [SKIP][33] ([i915#3297])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@gem_userptr_blits@map-fixed-invalidate-overlap.html

  * igt@gem_userptr_blits@relocations:
    - shard-mtlp:         NOTRUN -> [SKIP][34] ([i915#3281] / [i915#3297])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@gem_userptr_blits@relocations.html

  * igt@gen3_render_linear_blits:
    - shard-mtlp:         NOTRUN -> [SKIP][35] +5 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@gen3_render_linear_blits.html

  * igt@gen7_exec_parse@chained-batch:
    - shard-rkl:          NOTRUN -> [SKIP][36] +9 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@gen7_exec_parse@chained-batch.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-rkl:          NOTRUN -> [SKIP][37] ([i915#2527])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-tglu-1:       NOTRUN -> [SKIP][38] ([i915#2527] / [i915#2856])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-tglu:         NOTRUN -> [SKIP][39] ([i915#2527] / [i915#2856])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-4/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@i915_drm_fdinfo@busy-hang@ccs0:
    - shard-mtlp:         NOTRUN -> [SKIP][40] ([i915#14073]) +6 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@i915_drm_fdinfo@busy-hang@ccs0.html

  * igt@i915_drm_fdinfo@virtual-busy:
    - shard-mtlp:         NOTRUN -> [SKIP][41] ([i915#14118])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@i915_drm_fdinfo@virtual-busy.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-tglu-1:       NOTRUN -> [SKIP][42] ([i915#8399])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][43] ([i915#8399])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglu-1:       NOTRUN -> [WARN][44] ([i915#13790] / [i915#2681]) +1 other test warn
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rps@thresholds:
    - shard-mtlp:         NOTRUN -> [SKIP][45] ([i915#11681])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@i915_pm_rps@thresholds.html

  * igt@i915_query@hwconfig_table:
    - shard-tglu-1:       NOTRUN -> [SKIP][46] ([i915#6245])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@i915_query@hwconfig_table.html

  * igt@i915_selftest@live@workarounds:
    - shard-dg2:          [PASS][47] -> [DMESG-FAIL][48] ([i915#12061]) +1 other test dmesg-fail
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-1/igt@i915_selftest@live@workarounds.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-11/igt@i915_selftest@live@workarounds.html

  * igt@i915_suspend@debugfs-reader:
    - shard-rkl:          NOTRUN -> [ABORT][49] ([i915#15317]) +2 other tests abort
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@i915_suspend@debugfs-reader.html
    - shard-glk:          NOTRUN -> [INCOMPLETE][50] ([i915#4817])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk1/igt@i915_suspend@debugfs-reader.html
    - shard-dg2:          [PASS][51] -> [ABORT][52] ([i915#15317])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-3/igt@i915_suspend@debugfs-reader.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-6/igt@i915_suspend@debugfs-reader.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][53] ([i915#5190])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-tglu-1:       NOTRUN -> [SKIP][54] ([i915#12454] / [i915#12712])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-mtlp:         NOTRUN -> [SKIP][55] ([i915#3555])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
    - shard-tglu:         NOTRUN -> [SKIP][56] ([i915#9531])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-dg2:          [PASS][57] -> [FAIL][58] ([i915#5956])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-4/igt@kms_atomic_transition@plane-all-modeset-transition.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-1/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-tglu-1:       NOTRUN -> [SKIP][59] ([i915#1769] / [i915#3555])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [FAIL][60] ([i915#5956])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-1/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-tglu:         NOTRUN -> [SKIP][61] ([i915#5286])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-tglu-1:       NOTRUN -> [SKIP][62] ([i915#5286]) +2 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-rkl:          NOTRUN -> [SKIP][63] ([i915#5286]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-tglu:         NOTRUN -> [SKIP][64] +21 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-2/igt@kms_big_fb@linear-16bpp-rotate-270.html
    - shard-rkl:          NOTRUN -> [SKIP][65] ([i915#3638])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-mtlp:         NOTRUN -> [SKIP][66] ([i915#6187])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][67] ([i915#14098] / [i915#6095]) +15 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][68] ([i915#6095]) +31 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg1-16/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][69] ([i915#6095]) +9 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][70] ([i915#6095]) +4 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-mc-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][71] ([i915#10307] / [i915#6095]) +59 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-8/igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][72] ([i915#6095]) +44 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][73] ([i915#6095]) +23 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [ABORT][74] ([i915#15317]) +2 other tests abort
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-edp-1:
    - shard-mtlp:         [PASS][75] -> [ABORT][76] ([i915#15317]) +5 other tests abort
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-mtlp-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-edp-1.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-6/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-b-hdmi-a-4:
    - shard-dg1:          [PASS][77] -> [ABORT][78] ([i915#15317])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg1-17/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-b-hdmi-a-4.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg1-17/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-b-hdmi-a-4.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][79] ([i915#6095]) +7 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-11/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-dp-3.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][80] ([i915#12796]) +1 other test incomplete
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk8/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][81] ([i915#12313])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
    - shard-mtlp:         NOTRUN -> [SKIP][82] ([i915#12313])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-rkl:          NOTRUN -> [SKIP][83] ([i915#11151] / [i915#7828]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_chamelium_frames@hdmi-crc-single:
    - shard-tglu-1:       NOTRUN -> [SKIP][84] ([i915#11151] / [i915#7828]) +3 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_chamelium_frames@hdmi-crc-single.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-mtlp:         NOTRUN -> [SKIP][85] ([i915#11151] / [i915#7828]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@vga-hpd-after-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([i915#11151] / [i915#7828]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-4/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html

  * igt@kms_color@deep-color:
    - shard-tglu-1:       NOTRUN -> [SKIP][87] ([i915#3555] / [i915#9979])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_color@deep-color.html

  * igt@kms_colorop@plane-xr24-xr24-bt2020_oetf:
    - shard-mtlp:         NOTRUN -> [SKIP][88] ([i915#15343]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_colorop@plane-xr24-xr24-bt2020_oetf.html

  * igt@kms_colorop@plane-xr30-xr30-bt2020_inv_oetf-bt2020_oetf:
    - shard-tglu-1:       NOTRUN -> [SKIP][89] ([i915#15343]) +3 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_colorop@plane-xr30-xr30-bt2020_inv_oetf-bt2020_oetf.html

  * igt@kms_colorop@plane-xr30-xr30-pq_eotf:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#15343]) +3 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@kms_colorop@plane-xr30-xr30-pq_eotf.html

  * igt@kms_colorop@plane-xr30-xr30-srgb_inv_eotf:
    - shard-tglu:         NOTRUN -> [SKIP][91] ([i915#15343]) +1 other test skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-2/igt@kms_colorop@plane-xr30-xr30-srgb_inv_eotf.html

  * igt@kms_content_protection@content-type-change:
    - shard-tglu-1:       NOTRUN -> [SKIP][92] ([i915#6944] / [i915#9424])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][93] ([i915#3116] / [i915#3299])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_content_protection@dp-mst-lic-type-0.html
    - shard-mtlp:         NOTRUN -> [SKIP][94] ([i915#3299])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@lic-type-1:
    - shard-tglu:         NOTRUN -> [SKIP][95] ([i915#6944] / [i915#9424])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-4/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@suspend-resume:
    - shard-tglu-1:       NOTRUN -> [SKIP][96] ([i915#6944])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_content_protection@suspend-resume.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][97] ([i915#13049])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-tglu-1:       NOTRUN -> [SKIP][98] ([i915#3555]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-tglu-1:       NOTRUN -> [SKIP][99] ([i915#13049])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [ABORT][100] ([i915#15317]) +3 other tests abort
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-tglu-1:       NOTRUN -> [SKIP][101] ([i915#4103])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-tglu-1:       NOTRUN -> [SKIP][102] ([i915#13691])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-tglu-1:       NOTRUN -> [SKIP][103] ([i915#3840])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-tglu-1:       NOTRUN -> [SKIP][104] ([i915#3555] / [i915#3840])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-mtlp:         NOTRUN -> [SKIP][105] ([i915#3555] / [i915#3840])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_dsc@dsc-with-output-formats.html
    - shard-tglu:         NOTRUN -> [SKIP][106] ([i915#3555] / [i915#3840])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-tglu-1:       NOTRUN -> [SKIP][107] ([i915#3840] / [i915#9053])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@chamelium:
    - shard-tglu:         NOTRUN -> [SKIP][108] ([i915#2065] / [i915#4854])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-4/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-2x:
    - shard-rkl:          NOTRUN -> [SKIP][109] ([i915#1839])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][110] ([i915#3637] / [i915#9934]) +2 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-tglu:         NOTRUN -> [SKIP][111] ([i915#3637] / [i915#9934])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-4/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-plain-flip:
    - shard-rkl:          NOTRUN -> [SKIP][112] ([i915#9934]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][113] ([i915#12745] / [i915#4839] / [i915#6113])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk1/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@a-hdmi-a1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][114] ([i915#12745] / [i915#6113])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk1/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@a-hdmi-a4:
    - shard-dg1:          NOTRUN -> [ABORT][115] ([i915#15317])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg1-16/igt@kms_flip@flip-vs-suspend@a-hdmi-a4.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][116] ([i915#2672] / [i915#3555])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][117] ([i915#2587] / [i915#2672])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][118] ([i915#3555] / [i915#8810] / [i915#8813]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][119] ([i915#2587] / [i915#2672] / [i915#3555])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][120] ([i915#2587] / [i915#2672])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][121] ([i915#2672] / [i915#3555]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][122] ([i915#2672]) +1 other test skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][123] ([i915#8708]) +2 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][124] ([i915#10056])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk9/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][125] ([i915#5439])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-glk10:        NOTRUN -> [SKIP][126] +15 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
    - shard-mtlp:         NOTRUN -> [SKIP][127] ([i915#1825]) +5 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][128] +29 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
    - shard-tglu:         NOTRUN -> [SKIP][129] ([i915#15102]) +7 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-mtlp:         NOTRUN -> [SKIP][130] ([i915#10055])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][131] ([i915#15102]) +9 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][132] ([i915#15102] / [i915#3023]) +6 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-pwrite:
    - shard-rkl:          NOTRUN -> [SKIP][133] ([i915#1825]) +12 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-pwrite.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-rkl:          [PASS][134] -> [SKIP][135] ([i915#3555] / [i915#8228])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_hdr@static-toggle-dpms.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][136] ([i915#3555] / [i915#8228])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][137] ([i915#12388])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][138] ([i915#12339])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg2:          [PASS][139] -> [SKIP][140] ([i915#10656] / [i915#12388])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-11/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-8/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][141] ([i915#13522])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
    - shard-mtlp:         NOTRUN -> [SKIP][142] ([i915#13522])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-tglu-1:       NOTRUN -> [SKIP][143] ([i915#6301])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-glk:          NOTRUN -> [ABORT][144] ([i915#15317]) +2 other tests abort
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk6/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b:
    - shard-glk:          NOTRUN -> [INCOMPLETE][145] ([i915#13026])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][146] ([i915#3555]) +1 other test skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][147] ([i915#13958]) +1 other test skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-mtlp:         NOTRUN -> [SKIP][148] ([i915#13958])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation:
    - shard-glk:          NOTRUN -> [SKIP][149] +194 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk6/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][150] ([i915#12343])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-tglu:         NOTRUN -> [SKIP][151] ([i915#9685])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-4/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][152] ([i915#4281])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-dg2:          [PASS][153] -> [SKIP][154] ([i915#15073])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-11/igt@kms_pm_rpm@dpms-non-lpsp.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-4/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@system-suspend-idle:
    - shard-glk:          [PASS][155] -> [ABORT][156] ([i915#15317])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-glk9/igt@kms_pm_rpm@system-suspend-idle.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk8/igt@kms_pm_rpm@system-suspend-idle.html

  * igt@kms_prime@d3hot:
    - shard-tglu:         NOTRUN -> [SKIP][157] ([i915#6524])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_prime@d3hot.html
    - shard-mtlp:         NOTRUN -> [SKIP][158] ([i915#6524])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-2/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][159] ([i915#11520]) +4 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-glk8/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][160] ([i915#11520]) +2 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-tglu:         NOTRUN -> [SKIP][161] ([i915#11520]) +1 other test skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-tglu-1:       NOTRUN -> [SKIP][162] ([i915#11520]) +3 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-rkl:          NOTRUN -> [SKIP][163] ([i915#9683])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_psr2_su@page_flip-nv12.html
    - shard-tglu:         NOTRUN -> [SKIP][164] ([i915#9683])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-2/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@pr-sprite-plane-move:
    - shard-mtlp:         NOTRUN -> [SKIP][165] ([i915#9688]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-4/igt@kms_psr@pr-sprite-plane-move.html

  * igt@kms_psr@psr-sprite-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][166] ([i915#9732]) +4 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-2/igt@kms_psr@psr-sprite-mmap-cpu.html

  * igt@kms_psr@psr2-cursor-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#1072] / [i915#9732]) +6 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_psr@psr2-cursor-mmap-gtt.html

  * igt@kms_psr@psr2-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][168] ([i915#9732]) +9 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_psr@psr2-suspend.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-tglu-1:       NOTRUN -> [SKIP][169] ([i915#5289])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-tglu:         NOTRUN -> [SKIP][170] ([i915#3555]) +1 other test skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#8623])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-tglu-1:       NOTRUN -> [SKIP][172] ([i915#9906])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-tglu:         NOTRUN -> [SKIP][173] ([i915#2437] / [i915#9412])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-4/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [PASS][174] -> [FAIL][175] ([i915#4349]) +4 other tests fail
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-4/igt@perf_pmu@busy-double-start@vecs1.html

  * igt@perf_pmu@module-unload:
    - shard-tglu-1:       NOTRUN -> [FAIL][176] ([i915#14433])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-1/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-tglu:         NOTRUN -> [SKIP][177] ([i915#8516])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-rkl:          NOTRUN -> [SKIP][178] ([i915#9917])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@sriov_basic@enable-vfs-autoprobe-off.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@debugfs-forcewake-user:
    - shard-dg1:          [DMESG-WARN][179] ([i915#4423]) -> [PASS][180] +1 other test pass
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg1-17/igt@i915_pm_rpm@debugfs-forcewake-user.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg1-18/igt@i915_pm_rpm@debugfs-forcewake-user.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
    - shard-dg2:          [FAIL][181] ([i915#5956]) -> [PASS][182]
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-4/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-1/igt@kms_atomic_transition@plane-toggle-modeset-transition.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-a-edp-1:
    - shard-mtlp:         [ABORT][183] ([i915#15317]) -> [PASS][184] +2 other tests pass
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-mtlp-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-a-edp-1.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-mtlp-6/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-a-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-4:
    - shard-dg1:          [ABORT][185] ([i915#15317]) -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg1-17/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-4.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg1-17/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-4.html

  * igt@kms_color@deep-color:
    - shard-rkl:          [SKIP][187] ([i915#12655] / [i915#3555]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_color@deep-color.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_color@deep-color.html

  * igt@kms_cursor_crc@cursor-sliding-128x42:
    - shard-tglu:         [FAIL][189] ([i915#13566]) -> [PASS][190] +3 other tests pass
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-tglu-7/igt@kms_cursor_crc@cursor-sliding-128x42.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-3/igt@kms_cursor_crc@cursor-sliding-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-2:
    - shard-rkl:          [FAIL][191] ([i915#13566]) -> [PASS][192] +1 other test pass
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-3/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-2.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-2.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          [SKIP][193] ([i915#3555]) -> [PASS][194]
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-1/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          [SKIP][195] ([i915#3555] / [i915#8228]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-8/igt@kms_hdr@static-toggle.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-11/igt@kms_hdr@static-toggle.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2:          [SKIP][197] ([i915#6953] / [i915#9423]) -> [PASS][198]
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-8/igt@kms_plane_scaling@intel-max-src-size.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-rkl:          [SKIP][199] ([i915#15073]) -> [PASS][200]
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-8/igt@kms_pm_rpm@dpms-non-lpsp.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-7/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@system-suspend-idle:
    - shard-tglu:         [ABORT][201] ([i915#15317]) -> [PASS][202] +1 other test pass
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-tglu-4/igt@kms_pm_rpm@system-suspend-idle.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-9/igt@kms_pm_rpm@system-suspend-idle.html

  * igt@kms_vrr@negative-basic:
    - shard-dg2:          [SKIP][203] ([i915#3555] / [i915#9906]) -> [PASS][204]
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-8/igt@kms_vrr@negative-basic.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-11/igt@kms_vrr@negative-basic.html

  
#### Warnings ####

  * igt@api_intel_bb@blit-reloc-keep-cache:
    - shard-rkl:          [SKIP][205] ([i915#14544] / [i915#8411]) -> [SKIP][206] ([i915#8411])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@api_intel_bb@blit-reloc-keep-cache.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@api_intel_bb@blit-reloc-keep-cache.html

  * igt@api_intel_bb@crc32:
    - shard-rkl:          [SKIP][207] ([i915#6230]) -> [SKIP][208] ([i915#14544] / [i915#6230])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@api_intel_bb@crc32.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@api_intel_bb@crc32.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-rkl:          [SKIP][209] ([i915#11078]) -> [SKIP][210] ([i915#11078] / [i915#14544])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@device_reset@unbind-cold-reset-rebind.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-rkl:          [SKIP][211] ([i915#14544] / [i915#3555] / [i915#9323]) -> [SKIP][212] ([i915#3555] / [i915#9323])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@gem_ccs@ctrl-surf-copy.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          [SKIP][213] ([i915#7697]) -> [SKIP][214] ([i915#14544] / [i915#7697])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@gem_close_race@multigpu-basic-threads.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_exec_balancer@parallel-dmabuf-import-out-fence:
    - shard-rkl:          [SKIP][215] ([i915#14544] / [i915#4525]) -> [SKIP][216] ([i915#4525])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@gem_exec_balancer@parallel-dmabuf-import-out-fence.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@gem_exec_balancer@parallel-dmabuf-import-out-fence.html

  * igt@gem_exec_reloc@basic-cpu-wc-active:
    - shard-rkl:          [SKIP][217] ([i915#3281]) -> [SKIP][218] ([i915#14544] / [i915#3281]) +1 other test skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@gem_exec_reloc@basic-cpu-wc-active.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-wc-active.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - shard-rkl:          [SKIP][219] ([i915#14544] / [i915#3281]) -> [SKIP][220] ([i915#3281]) +3 other tests skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@gem_exec_reloc@basic-write-read-active.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_exec_schedule@semaphore-power:
    - shard-rkl:          [SKIP][221] ([i915#14544] / [i915#7276]) -> [SKIP][222] ([i915#7276])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@gem_exec_schedule@semaphore-power.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_lmem_swapping@basic:
    - shard-rkl:          [SKIP][223] ([i915#14544] / [i915#4613]) -> [SKIP][224] ([i915#4613])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@gem_lmem_swapping@basic.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-rkl:          [SKIP][225] ([i915#4613]) -> [SKIP][226] ([i915#14544] / [i915#4613]) +2 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@gem_lmem_swapping@parallel-random-verify.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_media_vme:
    - shard-rkl:          [SKIP][227] ([i915#14544] / [i915#284]) -> [SKIP][228] ([i915#284])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@gem_media_vme.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@gem_media_vme.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-rkl:          [SKIP][229] ([i915#3282]) -> [SKIP][230] ([i915#14544] / [i915#3282]) +4 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_readwrite@read-bad-handle:
    - shard-rkl:          [SKIP][231] ([i915#14544] / [i915#3282]) -> [SKIP][232] ([i915#3282])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@gem_readwrite@read-bad-handle.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@gem_readwrite@read-bad-handle.html

  * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
    - shard-rkl:          [SKIP][233] ([i915#8411]) -> [SKIP][234] ([i915#14544] / [i915#8411])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-rkl:          [INCOMPLETE][235] ([i915#13356]) -> [ABORT][236] ([i915#15317])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@gem_workarounds@suspend-resume-fd.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-rkl:          [SKIP][237] ([i915#2527]) -> [SKIP][238] ([i915#14544] / [i915#2527])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@gen9_exec_parse@bb-oversize.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-rkl:          [SKIP][239] ([i915#14544] / [i915#2527]) -> [SKIP][240] ([i915#2527])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-rkl:          [SKIP][241] ([i915#8399]) -> [SKIP][242] ([i915#14544] / [i915#8399])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@i915_pm_freq_api@freq-reset-multiple.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-rkl:          [SKIP][243] ([i915#14498] / [i915#14544]) -> [SKIP][244] ([i915#14498])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@i915_pm_rc6_residency@rc6-idle.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-rkl:          [ABORT][245] ([i915#15317]) -> [INCOMPLETE][246] ([i915#13356])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-5/igt@i915_pm_rpm@system-suspend-execbuf.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-3/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_power@sanity:
    - shard-rkl:          [SKIP][247] ([i915#14544] / [i915#7984]) -> [SKIP][248] ([i915#7984])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@i915_power@sanity.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@i915_power@sanity.html

  * igt@i915_query@hwconfig_table:
    - shard-rkl:          [SKIP][249] ([i915#6245]) -> [SKIP][250] ([i915#14544] / [i915#6245])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@i915_query@hwconfig_table.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@i915_query@hwconfig_table.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          [SKIP][251] ([i915#14544] / [i915#5723]) -> [SKIP][252] ([i915#5723])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@i915_query@test-query-geometry-subslices.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@i915_query@test-query-geometry-subslices.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-rkl:          [SKIP][253] ([i915#12454] / [i915#12712]) -> [SKIP][254] ([i915#12454] / [i915#12712] / [i915#14544])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-rkl:          [SKIP][255] ([i915#1769] / [i915#3555]) -> [SKIP][256] ([i915#14544] / [i915#1769] / [i915#3555])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-rkl:          [SKIP][257] ([i915#14544] / [i915#5286]) -> [SKIP][258] ([i915#5286]) +1 other test skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          [SKIP][259] ([i915#5286]) -> [SKIP][260] ([i915#14544] / [i915#5286]) +2 other tests skip
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-rkl:          [SKIP][261] ([i915#3638]) -> [SKIP][262] ([i915#14544] / [i915#3638]) +1 other test skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
    - shard-rkl:          [SKIP][263] -> [SKIP][264] ([i915#14544]) +9 other tests skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs:
    - shard-rkl:          [SKIP][265] ([i915#14098] / [i915#6095]) -> [SKIP][266] ([i915#14098] / [i915#14544] / [i915#6095]) +17 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-mc-ccs:
    - shard-rkl:          [SKIP][267] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][268] ([i915#14098] / [i915#6095]) +3 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-mc-ccs.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][269] ([i915#6095]) -> [SKIP][270] ([i915#14544] / [i915#6095]) +17 other tests skip
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_chamelium_frames@hdmi-crc-single:
    - shard-rkl:          [SKIP][271] ([i915#11151] / [i915#7828]) -> [SKIP][272] ([i915#11151] / [i915#14544] / [i915#7828]) +3 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_chamelium_frames@hdmi-crc-single.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_chamelium_frames@hdmi-crc-single.html

  * igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
    - shard-rkl:          [SKIP][273] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][274] ([i915#11151] / [i915#7828]) +1 other test skip
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html

  * igt@kms_colorop@plane-xr30-xr30-bt2020_inv_oetf-bt2020_oetf:
    - shard-rkl:          [SKIP][275] ([i915#15343]) -> [SKIP][276] ([i915#14544] / [i915#15343]) +3 other tests skip
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_colorop@plane-xr30-xr30-bt2020_inv_oetf-bt2020_oetf.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_colorop@plane-xr30-xr30-bt2020_inv_oetf-bt2020_oetf.html

  * igt@kms_colorop@plane-xr30-xr30-ctm_3x4_overdrive:
    - shard-rkl:          [SKIP][277] ([i915#14544] / [i915#15343]) -> [SKIP][278] ([i915#15343]) +2 other tests skip
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_colorop@plane-xr30-xr30-ctm_3x4_overdrive.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_colorop@plane-xr30-xr30-ctm_3x4_overdrive.html

  * igt@kms_content_protection@content-type-change:
    - shard-rkl:          [SKIP][279] ([i915#6944] / [i915#9424]) -> [SKIP][280] ([i915#14544] / [i915#6944] / [i915#9424])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_content_protection@content-type-change.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@suspend-resume:
    - shard-rkl:          [SKIP][281] ([i915#6944]) -> [SKIP][282] ([i915#14544] / [i915#6944])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_content_protection@suspend-resume.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_content_protection@suspend-resume.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-rkl:          [SKIP][283] ([i915#13049]) -> [SKIP][284] ([i915#13049] / [i915#14544])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_cursor_crc@cursor-random-512x512.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-rkl:          [SKIP][285] ([i915#14544] / [i915#3555]) -> [SKIP][286] ([i915#3555])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-max-size.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-rkl:          [SKIP][287] ([i915#14544] / [i915#4103]) -> [SKIP][288] ([i915#4103])
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-rkl:          [SKIP][289] ([i915#14544]) -> [SKIP][290] +13 other tests skip
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-rkl:          [SKIP][291] ([i915#4103]) -> [SKIP][292] ([i915#14544] / [i915#4103])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-rkl:          [SKIP][293] ([i915#13691]) -> [SKIP][294] ([i915#13691] / [i915#14544])
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_display_modes@extended-mode-basic.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-rkl:          [SKIP][295] ([i915#13707] / [i915#14544]) -> [SKIP][296] ([i915#13707])
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_dp_linktrain_fallback@dp-fallback.html
    - shard-dg1:          [SKIP][297] ([i915#13707] / [i915#4423]) -> [SKIP][298] ([i915#13707])
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg1-17/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg1-18/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-rkl:          [SKIP][299] ([i915#3840]) -> [SKIP][300] ([i915#14544] / [i915#3840])
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_dsc@dsc-fractional-bpp.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-rkl:          [SKIP][301] ([i915#3555] / [i915#3840]) -> [SKIP][302] ([i915#14544] / [i915#3555] / [i915#3840])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_dsc@dsc-with-formats.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-rkl:          [SKIP][303] ([i915#3840] / [i915#9053]) -> [SKIP][304] ([i915#14544] / [i915#3840] / [i915#9053])
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@psr1:
    - shard-rkl:          [SKIP][305] ([i915#14544] / [i915#658]) -> [SKIP][306] ([i915#658])
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_feature_discovery@psr1.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-rkl:          [SKIP][307] ([i915#9934]) -> [SKIP][308] ([i915#14544] / [i915#9934]) +2 other tests skip
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check:
    - shard-rkl:          [SKIP][309] ([i915#14544] / [i915#9934]) -> [SKIP][310] ([i915#9934]) +1 other test skip
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_flip@2x-wf_vblank-ts-check.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_flip@2x-wf_vblank-ts-check.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-rkl:          [SKIP][311] ([i915#2672] / [i915#3555]) -> [SKIP][312] ([i915#14544] / [i915#2672] / [i915#3555])
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
    - shard-rkl:          [SKIP][313] ([i915#2672]) -> [SKIP][314] ([i915#14544] / [i915#2672])
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-rkl:          [SKIP][315] ([i915#14544] / [i915#2672] / [i915#3555]) -> [SKIP][316] ([i915#2672] / [i915#3555])
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          [SKIP][317] ([i915#14544] / [i915#2672]) -> [SKIP][318] ([i915#2672])
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
    - shard-rkl:          [SKIP][319] ([i915#1825]) -> [SKIP][320] ([i915#14544] / [i915#1825]) +17 other tests skip
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][321] ([i915#14544] / [i915#1825]) -> [SKIP][322] ([i915#1825]) +10 other tests skip
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-rkl:          [SKIP][323] ([i915#5439]) -> [SKIP][324] ([i915#14544] / [i915#5439])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
    - shard-dg2:          [SKIP][325] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][326] ([i915#15102] / [i915#3458]) +1 other test skip
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
    - shard-rkl:          [SKIP][327] ([i915#15102] / [i915#3023]) -> [SKIP][328] ([i915#14544] / [i915#15102] / [i915#3023]) +8 other tests skip
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render:
    - shard-dg2:          [SKIP][329] ([i915#15102] / [i915#3458]) -> [SKIP][330] ([i915#10433] / [i915#15102] / [i915#3458])
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][331] ([i915#14544] / [i915#15102]) -> [SKIP][332] ([i915#15102])
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][333] ([i915#15102]) -> [SKIP][334] ([i915#14544] / [i915#15102])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
    - shard-rkl:          [SKIP][335] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][336] ([i915#15102] / [i915#3023]) +3 other tests skip
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-rkl:          [SKIP][337] ([i915#12339]) -> [SKIP][338] ([i915#12339] / [i915#14544])
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_joiner@basic-ultra-joiner.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          [SKIP][339] ([i915#6301]) -> [SKIP][340] ([i915#14544] / [i915#6301])
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_panel_fitting@legacy.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-rkl:          [SKIP][341] ([i915#13958]) -> [SKIP][342] ([i915#13958] / [i915#14544]) +1 other test skip
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_plane_multiple@2x-tiling-4.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-rkl:          [SKIP][343] ([i915#12343]) -> [SKIP][344] ([i915#12343] / [i915#14544])
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_pm_backlight@brightness-with-dpms.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-rkl:          [SKIP][345] ([i915#14544] / [i915#9685]) -> [SKIP][346] ([i915#9685])
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          [SKIP][347] ([i915#14544] / [i915#3828]) -> [SKIP][348] ([i915#3828])
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_pm_dc@dc5-retention-flops.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-8/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         [SKIP][349] ([i915#15128]) -> [SKIP][350] ([i915#4281])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-tglu-6/igt@kms_pm_dc@dc9-dpms.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-tglu-5/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [SKIP][351] ([i915#15073]) -> [SKIP][352] ([i915#14544] / [i915#15073])
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_pm_rpm@dpms-lpsp.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-rkl:          [SKIP][353] ([i915#11520] / [i915#14544]) -> [SKIP][354] ([i915#11520]) +2 other tests skip
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][355] ([i915#11520]) -> [SKIP][356] ([i915#11520] / [i915#14544]) +3 other tests skip
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-rkl:          [SKIP][357] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][358] ([i915#1072] / [i915#9732]) +9 other tests skip
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_psr@fbc-psr2-sprite-render.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@psr2-suspend:
    - shard-rkl:          [SKIP][359] ([i915#1072] / [i915#9732]) -> [SKIP][360] ([i915#1072] / [i915#14544] / [i915#9732]) +9 other tests skip
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_psr@psr2-suspend.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_psr@psr2-suspend.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-rkl:          [SKIP][361] ([i915#5289]) -> [SKIP][362] ([i915#14544] / [i915#5289])
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-rkl:          [SKIP][363] ([i915#3555]) -> [SKIP][364] ([i915#14544] / [i915#3555]) +1 other test skip
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@kms_setmode@invalid-clone-single-crtc.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-rkl:          [SKIP][365] ([i915#9906]) -> [SKIP][366] ([i915#14544] / [i915#9906])
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@kms_vrr@flip-basic-fastset.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-rkl:          [SKIP][367] ([i915#14544] / [i915#2437] / [i915#9412]) -> [SKIP][368] ([i915#2437] / [i915#9412])
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@kms_writeback@writeback-check-output-xrgb2101010.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@prime_vgem@basic-fence-read:
    - shard-rkl:          [SKIP][369] ([i915#3291] / [i915#3708]) -> [SKIP][370] ([i915#14544] / [i915#3291] / [i915#3708])
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-7/igt@prime_vgem@basic-fence-read.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@fence-write-hang:
    - shard-rkl:          [SKIP][371] ([i915#3708]) -> [SKIP][372] ([i915#14544] / [i915#3708])
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-4/igt@prime_vgem@fence-write-hang.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-6/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each:
    - shard-rkl:          [SKIP][373] ([i915#14544] / [i915#9917]) -> [SKIP][374] ([i915#9917])
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17605/shard-rkl-6/igt@sriov_basic@enable-vfs-bind-unbind-each.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/shard-rkl-4/igt@sriov_basic@enable-vfs-bind-unbind-each.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
  [i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
  [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
  [i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
  [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12796]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12796
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13196
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13790
  [i915#13809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13809
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
  [i915#14433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14433
  [i915#14498]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14498
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14702]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14702
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15128]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15128
  [i915#15317]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15317
  [i915#15343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15343
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2065]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2065
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3711
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7276
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8810]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8810
  [i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
  [i915#9979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9979


Build changes
-------------

  * Linux: CI_DRM_17605 -> Patchwork_157945v4

  CI-20190529: 20190529
  CI_DRM_17605: e1c1b3e03e356d1e20432dcb0d38ad44d5e92670 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8644: 069c5ee6eb658181e7264883c6c4fba41fc917a4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_157945v4: e1c1b3e03e356d1e20432dcb0d38ad44d5e92670 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v4/index.html

[-- Attachment #2: Type: text/html, Size: 130177 bytes --]